I-JESD204C Intel FPGA IP kanye ne-ADI AD9081 MxFE ADC Interoperability Report

Ulwazi Lomkhiqizo

Umkhiqizo okukhulunywa ngawo encwadini yomsebenzisi iJESD204C Intel FPGA IP. Kuyingxenye yezingxenyekazi zekhompuyutha ezisetshenziswa ngokuhambisana ne-Intel Agilex I-Series F-Tile Demo Board kanye ne-ADI AD9081-FMCA-EBZ EVM. I-IP iqiniswa kumodi ye-Duplex kodwa kusetshenziswa indlela yomamukeli kuphela. Ikhiqiza iwashi lokuxhumanisa elingu-375 MHz kanye newashi lozimele elingu-375 MHz. Ukusethwa kwezingxenyekazi zekhompuyutha zokuhlola ukusebenzisana kwe-ADC kuboniswa kuMfanekiso 1. I-IP idinga ukuthi i-SYSREF inikezwe ijeneretha yewashi ethola iwashi ledivayisi ye-JESD204C Intel FPGA IP.

Imiyalo yokusetshenziswa komkhiqizo

Ukusethwa kwe-Hardware
Ukusetha i-Hardware yokusebenzisa i-JESD204C Intel FPGA IP, landela lezi zinyathelo:

1. Xhuma i-ADI AD9081-FMCA-EBZ EVM kusixhumi se-FMC+ se-Intel Agilex I-Series F-Tile Demo Board.
2. Qinisekisa ukuthi isignali ye-SYSREF inikezwa ijeneretha yewashi ethola iwashi ledivayisi ye-JESD204C Intel FPGA IP.

Incazelo Yesistimu
Umdwebo wezinga lesistimu ubonisa ukuthi amamojula ahlukene axhunywe kanjani kulo mklamo. Kuhlanganisa i-Intel Agilex-I F-tile Demo Board, Intel Agilex F-tile Device, Top-Level RTL, Platform Designer System, Pattern Generator, Pattern Checker, F-Tile JESD204C Duplex IP Core, namawashi ahlukahlukene kanye nezindawo zokusebenzelana.

I-Interoperability Methodology
Isendlalelo Sesixhumanisi Somamukeli
Le ndawo yokuhlola ihlanganisa izimo zokuhlola zokuvumelanisa unhlokweni (i-SHA) nokuqondanisa kwe-multiblock (EMBA) okunwetshiwe. I-JESD204C Intel FPGA IP ifunda amarejista kusuka kungqimba lwesixhumanisi sedatha ngesikhathi sokuhlolwa, iwabhale kulogi files, futhi iwaqinisekise ukuze kudlule imibandela emibhalweni ye-TCL.

I-JESD204C Intel® FPGA IP kanye ne-ADI AD9081 MxFE* Umbiko Wokusebenzisana we-ADC wamadivayisi e-Intel® Agilex™ F-tile

I-JESD204C Intel® FPGA IP iyisixhumi esibonakalayo se-serial interface esibonakalayo (IP).
I-JESD204C Intel FPGA IP ihlolwe ihadiwe ngamadivayisi amaningana akhethiwe we-JESD204C athobelana ne-analog-to-digital converter (ADC).
Lo mbiko ugqamisa ukusebenzisana kwe-JESD204C Intel FPGA IP ne-AD9081 Mixed Signal Front End (MxFE*) module yokuhlola (EVM) evela ku-Analog Devices Inc. (ADI). Izigaba ezilandelayo zichaza indlela yokuphuma kwezingxenyekazi zekhompuyutha kanye nemiphumela yokuhlolwa.

Ulwazi Oluhlobene
F-tile JESD204C Intel FPGA IP Umhlahlandlela Womsebenzisi

Izingxenyekazi zekhompuyutha nezidingo zeSoftware
Ukuhlolwa kokusebenzisana kudinga izingxenyekazi zekhompuyutha ezilandelayo: Izingxenyekazi zekhompuyutha

• I-Intel Agilex™ I-Series F-tile Demo Board (AGIB027R29A1E2VR0) ene-adaptha yamandla engu-12V
• Amadivayisi e-Analog (ADI) AD9081 MxFE* EVM (AD9081-FMCA-EBZ, Rev C)
• I-Skywork Si5345-D Evaluation Board (Si5345-D-EVB)
• I-SMA owesilisa kuya kowesilisa we-SMP
• Intambo ye-SMP yesilisa ukuya ku-SMP

Isofthiwe

• Isoftware ye-Intel Quartus® Prime Pro Edition engu-21.4
• AD9081_API inguqulo 1.1.0 noma entsha (uhlelo lokusebenza lwe-Linux, luyadingeka ekucushweni kwe-AD9081 EVM)

Ulwazi Oluhlobene

• AD9081/AD9082 Umhlahlandlela Womsebenzisi Wokuthuthukiswa Kwesistimu
• I-Skyworks Si5345-D Umhlahlandlela Womsebenzisi Webhodi Lokuhlola

Ukusethwa kwe-Hardware
I-JESD204C Intel FPGA IP ifakwe kumodi ye-Duplex kodwa kusetshenziswa indlela yomamukeli kuphela. Ku-FCLK_MULP =1, WIDTH_MULP = 8, S = 1, i-PLL eyinhloko ikhiqiza iwashi lesixhumanisi elingu-375 MHz kanye newashi lozimele elingu-375 MHz.
I-Intel Agilex I-Series F-Tile Demo Board isetshenziswa ne-ADI AD9081-FMCA-EBZ EVM exhunywe kusixhumi se-FMC+ sebhodi lokuthuthukisa. Ukusethwa kwezingxenyekazi zekhompuyutha zokuhlola ukusebenzisana kwe-ADC kuboniswa kumfanekiso Wokusethwa Kwezingxenyekazi zekhompuyutha.- • I-AD9081-FMCA-EBZ EVM ithola amandla ku-Intel Agilex I-Series F-Tile Demo Board ngesixhumi se-FMC+.

• I-F-tile transceiver kanye ne-JESD204C Intel FPGA IP core PLL amawashi ahlinzekwa yi-Si5345-D-EVB nge-SMA kuya kukhebula le-SMP. Setha i-MUX_DIP_SW0 iye phezulu ku-Agilex-I F-Tile Demo Board ukuze uqinisekise ukuthi i-U22 ithatha i-CLKIN1 exhunywe kukhebuli ye-SMP.
• I-Si5345-D-EVB inikeza iwashi eliyireferensi kujeneretha yewashi ehlelekayo ye-HMC7044 ekhona ku-AD9081 EVM ngekhebuli ye-SMP kuye kwe-SMP.
• Iwashi lokuphatha le-JESD204C Intel FPGA IP core lihlinzekwa yi-Silicon Labs Si5332 generator yewashi ehlelekayo ekhona ku-Intel Agilex I-Series F-tile Demo Board.
• Ijeneretha yewashi ehlelekayo ye-HMC7044 inikeza iwashi lereferensi yedivayisi ye-AD9081. I-loop ekhiyiwe ngesigaba (PLL) ekhona kudivayisi ye-AD9081 ikhiqiza ama-ADC adingekayo.ampiwashi elingenasici elisuka ewashini eliyireferensi yedivayisi.
• Ku-Subclass 1, ijeneretha yewashi ye-HMC7044 ikhiqiza isignali ye-SYSREF yedivayisi ye-AD9081 kanye neye-JESD204C Intel FPGA IP ngesixhumi se-FMC+.

Chate: I-Intel incoma i-SYSREF ukuthi inikezwe ijeneretha yewashi ethola iwashi ledivayisi ye-JESD204C Intel FPGA IP.

Incazelo Yesistimu

Umdwebo olandelayo wezinga lesistimu ubonisa ukuthi amamojula ahlukene axhunywe kanjani kulo mklamo.

Umfanekiso 2. Umdwebo Wesistimu

Amanothi:

1. M inombolo yeziguquli.
2. U-S inombolo yokudlulisela u-sampkancane isiguquli ngozimele ngamunye.
3. I-WIDTH_MULP iyisiphindaphindi sobubanzi bedatha phakathi kwesendlalelo sohlelo lokusebenza nesendlalelo sokuthutha.
4. N inombolo yokuguqulwa kwamabhithi kusiguquli ngasinye.
5. I-CS inombolo yamabhithi okulawula ngokuguqulwa ngakunye sampLes.

Kulokhu kusetha, isiboneloample L = 8, M = 4, kanye no-F = 1, izinga ledatha lemizila ye-transceiver lingu-24.75 Gbps.
I-Si5332 OUT1 ikhiqiza iwashi elingu-100 MHz ukuya ku-mgmt_clk. I-Si5345-D-EVB ikhiqiza amaza ewashi amabili, 375 MHz kanye no-100 MHz. I-375 MHz inikezwa ku-multiplexer eshumekiwe ku-Intel Agilex I-Series F-tile Demo Board ngembobo ye-J19 SMA. Iwashi elikhiphayo le-multiplexer eshumekiwe lishayela iwashi lereferensi le-F-tile transceiver (refclk_xcvr) kanye ne-JESD204C Intel FPGA IP core PLL yewashi (refclk_core). 100 MHz kusukela ku-Si5345-D-EVB ixhunywe kujeneretha yewashi ehlelekayo ye-HMC7044 ekhona ku-AD9081 EVM njengokufakwayo kwewashi
(EXT_HMCREF).

I-HCM7044 ikhiqiza isignali ye-SYSREF yezikhathi ezithile engu-11.71875 MHz ngesixhumi se-FMC.
I-JESD204C Intel FPGA IP ifakwe kumodi ye-Duplex kodwa kusetshenziswa indlela yomamukeli kuphela.

I-Interoperability Methodology
Isigaba esilandelayo sichaza izinjongo zokuhlolwa, inqubo, kanye nemibandela yokuphasa. Ukuhlolwa kuhlanganisa lezi zindawo ezilandelayo:

• Isendlalelo sesixhumanisi somamukeli
• Isendlalelo sokuthutha umamukeli

Isendlalelo Sesixhumanisi Somamukeli
Le ndawo yokuhlola ihlanganisa izimo zokuhlola zokuvumelanisa unhlokweni (i-SHA) nokuqondanisa kwe-multiblock (EMBA) okunwetshiwe.
Ekuqalisweni kwesixhumanisi, ngemva kokusetha kabusha umamukeli, i-JESD204C Intel FPGA IP iqala ukufuna ukusakazwa kwesihloko sokuvumelanisa esisakazwa idivayisi. Amarejista alandelayo asuka kusendlalelo sesixhumanisi sedatha afundwa ngesikhathi sokuhlolwa, abhalwe kulogi files, futhi yaqinisekiswa indlela yokuphasa ngemibhalo ye-TCL.

Ulwazi Oluhlobene
F-tile JESD204C Intel FPGA IP Umhlahlandlela Womsebenzisi

Vumelanisa Ukuqondanisa Kanhlokweni (SHA)
Ithebula 1. Vumelanisa Izimo Zokuhlola Ukuqondanisa Isihloko

Ikesi Lokuhlola	Inhloso	Incazelo	Imibandela Yokudlulisa
I-SHA.1	Hlola ukuthi i-Sync Header Lock iyagonyelwa yini ngemva kokuqedwa kokulandelana kokusetha kabusha.	Amasignali alandelayo afundwa kumarejista: I-CDR_Lock ifundwa kurejista ethi rx_status3 (0x8C). SH_Locked ifundwa kurejista ye-rx_status4 (0x90). jrx_sh_err_status ifundwa kurejista rx_err_status (0x60).	I-CDR_Lock kanye nokuthi SH_LOCK kufanele kugonyelwe phezulu okuhambisana nenani lemizila. jrx_sh_err_status kufanele kube  Izinkambu ze-bit ku-jrx_sh_err_status zihlola okuthi sh_unlock_err, rx_gb_overflow_err, rx_gb_underflow_err, invalid_sync_header, src_rx_alarm, syspll_lock_err, kanye ne-cdr_locked_err.
I-SHA.2	Hlola isimo se-Header Lock yokuvumelanisa ngemva kokuba ukukhiya kwesihloko sokuvumelanisa kufinyelelwe (noma phakathi nesigaba Esinwetshiwe Sokuqondanisa I-Multi-Block) futhi izinzile.	invalid_sync_header ifundelwa isimo sokukhiya Unhlokweni kusuka kurejista (0x60[8]).	invalid_sync_header isimo kufanele sibe ngu-0.

Ukuqondanisa Okunwetshiwe kwe-Multiblock (EMBA)

Ithebula 2. Izimo Ezinwetshiwe Zokuhlola Ukuqondanisa Kwe-Multiblock

Ikesi Lokuhlola		Inhloso		Incazelo		Imibandela Yokudlulisa
EMBA.1		Hlola ukuthi i-Multiblock Lock Enwetshiwe igonyelwa kuphela ngemva kokugomela kokuthi Vumelanisa Ukukhiya Kwesihloko.		Amasignali alandelayo afundwa kumarejista:		Inani elingu-EMB_Locked_1 kufanele lilingane no-1 ohambisana nomzila ngamunye. EMB_Lock_err kufanele kube ngu-0.
	Ikesi Lokuhlola		Inhloso		Incazelo		Imibandela Yokudlulisa
					I-EMB_Locked_1 ifundwa kurejista ye-rx_status5 (0x94). I-EMB_Lock_err ifundwa kurejista rx_err_status (0x60[19]).
	EMBA.2		Hlola ukuthi isimo se-Extended Multiblock Lock sizinzile yini (ngemuva kokukhiywa kwe-multiblock enwetshiwe noma kuze kudedelwe isigcinalwazi esinwebekayo) ngaphandle kokuvinjwa okuningi okungavumelekile.		invalid_eomb_eoemb ifundwa kurejista ethi rx_err_status (0x60[10:9]).		invalid_eomb_eoemb kufanele kube “00”.
	EMBA.3		Hlola ukuhleleka komzila.		Amanani alandelayo afundwa kumarejista: elastic_buf_over_flow ifundwa kurejista rx_err_status (0x60[20]). elastic_buf_full ifundwa kurejista rx_status6 (0x98).		elastic_buf_over_flow kufanele kube ngu-0. I-elastic_buf_full value kufanele ilingane no-1 ohambisana nomzila ngamunye.

Isendlalelo Sezokuthutha Somamukeli (TL)
Ukuhlola ubuqotho bedatha yokusakaza kwedatha yokulayisha okukhokhelwayo ngomamukeli (RX) JESD204C Intel FPGA IP kanye nesendlalelo sezokuthutha, i-ADC ilungiselelwe ukuthi ramp/iphethini yokuhlola ye-PRBS. I-ADC futhi isethwe ukuthi isebenze ngokucushwa okufanayo njengoba kusethwe ku-JESD204C Intel FPGA IP. I-ramp/Isihloli se-PRBS endwangu ye-FPGA sihlola i-ramp/PRBS idatha ubuqotho umzuzu owodwa. Irejista ye-IP ye-RX JESD204C Intel FPGA IP rx_err ivotelwa ngokuqhubekayo ngenani elinguziro umzuzu owodwa.
Isibalo esingezansi sibonisa ukusethwa kokuhlolwa komqondo ukuze kuhlolwe ubuqotho bedatha.

Umfanekiso 3. Ukuhlola Ubuqotho Bedatha Ngokusebenzisa i-Ramp/PRBS15 Checker

Ithebula 3. Amacala Okuhlolwa Kwezingqimba Zokuthutha

Ikesi Lokuhlola	Inhloso	Incazelo	Imibandela Yokudlulisa
TL.1	Hlola imephu yesendlalelo sezokuthutha seshaneli yedatha usebenzisa u-ramp iphethini yokuhlola.	I-Data_mode isethelwe ku-Ramp_imodi. Amasignali alandelayo afundwa kumarejista: crc_err ifundwa kokuthi rx_err_status (0x60[14]).  jrx_patchk_data_error ifundwa kurejista ye-tst_err0.	crc_err kufanele ibe phansi ukuze idlule. jrx_patchk_data_error kufanele ibe phansi.
TL.2	Hlola imephu yesendlalelo sezokuthutha sesiteshi sedatha usebenzisa iphethini yokuhlola ye-PRBS15.	Imodi_yedatha isethwe ku-prbs_mode. Amanani alandelayo afundwa kumarejista: crc_err ifundwa kokuthi rx_err_status (0x60[14]). jrx_patchk_data_error ifundwa kurejista ye-tst_err0.	crc_err kufanele ibe phansi ukuze idlule. jrx_patchk_data_error kufanele ibe phansi.

I-JESD204C Intel FPGA IP ne-ADC Configurations
Amapharamitha we-JESD204C Intel FPGA IP (L, M, no-F) kulokhu kuthenga izingxenyekazi zekhompuyutha asekelwa ngokomdabu idivayisi ye-AD9081. Izinga ledatha ye-transceiver, sampiwashi le-ling, namanye amapharamitha we-JESD204C athobelana nezimo zokusebenza ze-AD908D1.
Ukuhlolwa kokuphuma kwezingxenyekazi zekhompyutha kusebenzisa i-JESD204C Intel FPGA IP ngokucushwa kwepharamitha elandelayo.

Ukulungiselelwa komhlaba wonke kwakho konke ukucushwa:

• E = 1
• CF = 0
• CS = 0
• Isigaba esingaphansi = 1
• FCLK_MULP = 1
• WIDTH_MULP = 8
• SH_CONFIG = CRC-12
• Iwashi Lokuphatha le-FPGA (MHz) = 100

Imiphumela Yokuhlola
Ithebula elilandelayo liqukethe imiphumela engaba khona kanye nencazelo yayo.

Ithebula 4. Incazelo Yemiphumela

Umphumela	Incazelo
PASS	Idivayisi Ingaphansi Kokuhlolwa (DUT) yaqashelwa ukubonisa ukuziphatha okuhambisanayo.
PASS namazwana	I-DUT yaqashelwa ukuthi ikhombise ukuziphatha okuhambisanayo. Nokho, incazelo eyengeziwe yalesi simo ifakiwe (isibample: ngenxa yemikhawulo yesikhathi, ingxenye kuphela yokuhlola eyenziwe).

Umphumela	Incazelo
FAIL	I-DUT yaqashelwa ukuthi ikhombise ukuziphatha okungahambisani nalokho.
Isexwayiso	I-DUT yaqashelwa ukuthi ikhombise ukuziphatha okunganconywa.
Bheka kumazwana	Kusukela ekuqapheliseni, ukudlula okuvumelekile noma ukufeyila akukwazanga ukunqunywa. Incazelo eyengeziwe yalesi simo ifakiwe.

Ithebula elilandelayo libonisa imiphumela yamacala okuhlola okuthi SHA.1, SHA.2, EMBA.1, EMBA.2, EMBA.3, TL.1, kanye ne-TL.2 ngamavelu alandelanayo angu-L, M, F, isilinganiso sedatha, sampiwashi elining, iwashi lesixhumanisi, namafrikhwensi we-SYSREF.

Ithebula 5. Umphumela Wezimo Zokuhlola SHA.1, SHA.2, EMBA.1, EMBA.2, EMBA.3, TL.1, kanye ne-TL.2

Cha.	L	M	F	S	HD	E	N	NP	I-ADC SampIwashi elide (MHz)	Iwashi Ledivayisi ye-FPGA (MHz)	I-FPGA Iwashi lozimele (MHz)	I-FPGA Xhuma Iwashi (MHz)	I-Lane Rate (Gbps)	Umphumela
1	8	4	1	1	0	1	16	16	3000.00	375.00	375.00	375.00	24.75	Dlula

Amazwana Omphumela Wokuhlola
Esimeni ngasinye sokuhlola, i-RX JESD204C Intel FPGA IP isungula ngempumelelo ukuvumelanisa kwesihloko, ukuqondanisa okunwetshiwe kwama-multiblock, futhi kuze kufike esigabeni sedatha yomsebenzisi.
Ayikho inkinga yobuqotho bedatha ebonwa yi-Ramp kanye nesihloli se-PRBS sokucushwa kwe-JESD okumboza yonke imizila ebonakalayo, futhi akukho ukuhlolwa kokuphindaphindeka komjikelezo (CRC) kanye nephutha lokulinganisa komyalo liyabonwa.
Phakathi nemijikelezo ethile yamandla, iphutha ledeski lomzila lingase livele ngokulungiselelwa kwepharamitha. Ukuze ugweme leli phutha, amanani e-LEMC offset kufanele ahlelwe noma ungakwenza lokhu ngokuzenzakalelayo ngenqubo yokushanela yokulinganisa. Ukuze uthole ulwazi olwengeziwe ngamavelu asemthethweni we-LEMC offset, bheka i-RBD Tuning Mechanism ku-F-tile JESD204C IP User Guide.

Ulwazi Oluhlobene
I-RBD Tuning Mechanism

Isifinyezo
Lo mbiko ubonisa ukuqinisekiswa kwe-JESD204C Intel FPGA IP kanye nesixhumi esibonakalayo sikagesi se-PHY ngedivayisi ye-AD9081/9082 (R2 Silicon) efika ku-24.75 Gbps ye-ADC. Ukucushwa okuphelele nokusethwa kwehadiwe kuboniswa ukunikeza ukuzethemba ekusebenzisaneni nasekusebenzeni kwalawa madivayisi womabili.

Umlando Wokubuyekezwa Kombhalo we-AN 927: JESD204C Intel FPGA IP kanye ne-ADI AD9081 MxFE* Umbiko Wokusebenzisana we-ADC we-Intel Agilex F-Tile Devices

Inguqulo Yedokhumenti	Izinguquko
2022.04.25	Ukukhishwa kokuqala.

AN 876: JESD204C Intel® FPGA IP kanye ne-ADI AD9081 MxFE* Umbiko Wokusebenzisana we-ADC wamadivayisi e-Intel® Agilex® F-Tile

Amadokhumenti / Izinsiza

i-intel JESD204C Intel FPGA IP kanye ne-ADI AD9081 MxFE ADC Interoperability Report [pdf] Umhlahlandlela Womsebenzisi I-JESD204C Intel FPGA IP kanye ne-ADI AD9081 MxFE ADC Interoperability Report, JESD204C, Intel FPGA IP kanye ne-ADI AD9081 MxFE ADC Interoperability Report

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