JESD204C Intel FPGA IP ati ADI AD9081 MxFE ADC Interoperability.

ọja Alaye

Ọja ti a tọka si ninu afọwọṣe olumulo jẹ JESD204C Intel FPGA IP. O jẹ paati ohun elo ti o lo ni apapo pẹlu Intel Agilex I-Series F-Tile Demo Board ati ADI AD9081-FMCA-EBZ EVM. IP naa ti wa ni ese ni ipo Duplex ṣugbọn ọna olugba nikan ni a lo. O ṣe agbejade aago ọna asopọ 375 MHz ati aago fireemu 375 MHz kan. Eto ohun elo fun idanwo interoperability ADC ni nọmba 1. IP nilo SYSREF lati pese nipasẹ olupilẹṣẹ aago ti o ṣe orisun aago ohun elo JESD204C Intel FPGA IP.

Awọn ilana Lilo ọja

Hardware Oṣo
Lati ṣeto ohun elo fun lilo JESD204C Intel FPGA IP, tẹle awọn igbesẹ wọnyi:

1. So ADI AD9081-FMCA-EBZ EVM si FMC + asopo ti Intel Agilex I-Series F-Tile Ririnkiri Board.
2. Rii daju pe ifihan SYSREF ti pese nipasẹ olupilẹṣẹ aago ti o ṣe orisun aago ohun elo JESD204C Intel FPGA IP.

System Apejuwe
Aworan-ipele eto fihan bi awọn modulu oriṣiriṣi ṣe sopọ ni apẹrẹ yii. O pẹlu Intel Agilex-I F-tile Demo Board, Intel Agilex F-tile Device, Top-Level RTL, Platform Designer System, Pattern Generator, Pattern Checker, F-Tile JESD204C Duplex IP Core, ati orisirisi awọn aago ati awọn atọkun.

Ilana Interoperability
Olugba Data Link Layer
Agbegbe idanwo yii ni wiwa awọn ọran idanwo fun titete akọsori amuṣiṣẹpọ (SHA) ati titete multiblock ti o gbooro (EMBA). JESD204C Intel FPGA IP n ka awọn iforukọsilẹ lati Layer ọna asopọ data lakoko idanwo naa, kọ wọn sinu log files, ati pe o jẹri wọn fun gbigbe awọn ibeere nipasẹ awọn iwe afọwọkọ TCL.

JESD204C Intel® FPGA IP ati ADI AD9081 MxFE* ADC Interoperability Ijabọ fun awọn Ẹrọ F-tile Intel® Agilex™

JESD204C Intel® FPGA IP jẹ aaye-si-ojuami ni wiwo ni wiwo ohun-ini ọgbọn (IP).
JESD204C Intel FPGA IP ti jẹ idanwo ohun elo pẹlu ọpọlọpọ awọn ohun elo JESD204C ifaramọ afọwọṣe-si-oni oluyipada (ADC) pupọ.
Iroyin yii ṣe afihan interoperability ti JESD204C Intel FPGA IP pẹlu AD9081 Mixed Signal Front End (MxFE *) module igbelewọn (EVM) lati Awọn Ẹrọ Analog Inc. (ADI). Awọn apakan atẹle n ṣapejuwe ilana isanwo ohun elo ati awọn abajade idanwo.

Alaye ti o jọmọ
F-tile JESD204C Intel FPGA IP Itọsọna olumulo

Hardware ati Software Awọn ibeere
Idanwo interoperability nilo hardware wọnyi ati awọn irinṣẹ sọfitiwia: Hardware

• Intel Agilex™ I-Series F-tile Demo Board (AGIB027R29A1E2VR0) pẹlu ohun ti nmu badọgba agbara 12V
• Awọn ẹrọ Analog (ADI) AD9081 MxFE* EVM (AD9081-FMCA-EBZ, Rev C)
• Skywork Si5345-D Board Igbelewọn (Si5345-D-EVB)
• SMA akọ to SMP akọ
• SMP akọ to SMP USB

Software

• Ẹya sọfitiwia Intel Quartus® Prime Pro Edition 21.4
• AD9081_API version 1.1.0 tabi tuntun (ohun elo Linux, ti o nilo fun iṣeto AD9081 EVM)

Alaye ti o jọmọ

• AD9081/AD9082 Itọsọna olumulo Idagbasoke Eto
• Skyworks Si5345-D Igbelewọn Board User Itọsọna

Hardware Oṣo
JESD204C Intel FPGA IP ti wa ni kiakia ni ipo Duplex ṣugbọn ọna olugba nikan ni a lo. Fun FCLK_MULP = 1, WIDTH_MULP = 8, S = 1, PLL mojuto n ṣe agbekalẹ aago ọna asopọ 375 MHz ati aago fireemu 375 MHz kan.
An Intel Agilex I-Series F-Tile Demo Board ni a lo pẹlu ADI AD9081-FMCA-EBZ EVM ti o ni asopọ si asopọ FMC + ti igbimọ idagbasoke. Iṣeto ohun elo fun idanwo interoperability ADC jẹ afihan ni nọmba Iṣeto Hardware.- • AD9081-FMCA-EBZ EVM n gba agbara lati Intel Agilex I-Series F-Tile Demo Board nipasẹ asopọ FMC +.

• transceiver F-tile ati JESD204C Intel FPGA IP mojuto awọn aago itọkasi PLL jẹ ipese nipasẹ Si5345-D-EVB nipasẹ SMA si okun SMP. Ṣeto MUX_DIP_SW0 si giga lori Agilex-I F-Tile Demo Board lati rii daju pe U22 n mu CLKIN1 ti o ni asopọ si okun SMP.
• Si5345-D-EVB n pese aago itọkasi si HMC7044 olupilẹṣẹ aago eleto ti o wa ninu AD9081 EVM nipasẹ SMP si okun SMP.
• Aago iṣakoso fun JESD204C Intel FPGA IP mojuto ti pese nipasẹ Silicon Labs Si5332 olupilẹṣẹ aago ti eto ti o wa ninu Intel Agilex I-Series F-tile Demo Board.
• Olupilẹṣẹ aago eto HMC7044 n pese aago itọkasi ẹrọ AD9081. Loop titiipa alakoso (PLL) ti o wa ninu ẹrọ AD9081 n ṣe agbejade awọn ADC ti o fẹampaago ling lati aago itọkasi ẹrọ.
• Fun Subclass 1, olupilẹṣẹ aago HMC7044 ṣe ipilẹṣẹ ifihan agbara SYSREF fun ẹrọ AD9081 ati fun JESD204C Intel FPGA IP nipasẹ asopo FMC+.

Rarate: Intel ṣeduro SYSREF lati pese nipasẹ olupilẹṣẹ aago ti o ṣe orisun aago ẹrọ JESD204C Intel FPGA IP.

System Apejuwe

Aworan-ipele eto atẹle fihan bi awọn oriṣiriṣi awọn modulu ṣe sopọ ni apẹrẹ yii.

Olusin 2. Eto aworan atọka

Awọn akọsilẹ:

1. M jẹ nọmba awọn oluyipada.
2. S jẹ nọmba ti s ti a firanṣẹamples fun oluyipada fun fireemu.
3. WIDTH_MULP jẹ isodipupo iwọn data laarin Layer ohun elo ati Layer gbigbe.
4. N jẹ nọmba awọn die-die iyipada fun oluyipada.
5. CS jẹ nọmba awọn iwọn iṣakoso fun iyipada samples.

Ninu iṣeto yii, fun example L = 8, M = 4, ati F = 1, iye data ti awọn ọna transceiver jẹ 24.75 Gbps.
Si5332 OUT1 ṣe ipilẹṣẹ aago 100 MHz si mgmt_clk. Si5345-D-EVB n ṣe awọn igbohunsafẹfẹ aago meji, 375 MHz ati 100 MHz. 375 MHz ti wa ni ipese si multiplexer ti a fi sinu Intel Agilex I-Series F-tile Demo Board nipasẹ ibudo J19 SMA. Aago abajade ti multiplexer ti a fi sii n ṣe awakọ aago itọkasi transceiver F-tile (refclk_xcvr) ati aago itọkasi JESD204C Intel FPGA IP mojuto PLL (refclk_core). 100 MHz lati Si5345-D-EVB ti sopọ si HMC7044 olupilẹṣẹ aago ti eto ti o wa ninu AD9081 EVM gẹgẹbi titẹ sii aago
(EXT_HMCREF).

HCM7044 ṣe ipilẹṣẹ ifihan SYSREF igbakọọkan ti 11.71875 MHz nipasẹ Asopọ FMC.
JESD204C Intel FPGA IP ti wa ni kiakia ni ipo Duplex ṣugbọn ọna olugba nikan ni a lo.

Ilana Interoperability
Abala ti o tẹle n ṣe apejuwe awọn ibi-afẹde idanwo, ilana, ati awọn ibeere gbigbe. Idanwo naa ni awọn agbegbe wọnyi:

• Layer data ọna asopọ olugba
• Layer gbigbe olugba

Olugba Data Link Layer
Agbegbe idanwo yii ni wiwa awọn ọran idanwo fun titete akọsori amuṣiṣẹpọ (SHA) ati titete multiblock ti o gbooro (EMBA).
Lori ọna asopọ bẹrẹ, lẹhin atunto olugba, JESD204C Intel FPGA IP bẹrẹ wiwa ṣiṣan akọsori amuṣiṣẹpọ ti o tan kaakiri nipasẹ ẹrọ naa. Awọn iforukọsilẹ atẹle lati Layer ọna asopọ data ni a ka lakoko idanwo, ti a kọ sinu log files, ati rii daju fun gbigbe awọn ibeere nipasẹ awọn iwe afọwọkọ TCL.

Alaye ti o jọmọ
F-tile JESD204C Intel FPGA IP Itọsọna olumulo

Titete Akọsori Amuṣiṣẹpọ (SHA)
Table 1. Sync akọsori titete Igbeyewo igba

Ọran Idanwo	Idi	Apejuwe	Ilana ti o kọja
SHA.1	Ṣayẹwo boya Titiipa akọsori amuṣiṣẹpọ ti jẹri lẹhin ipari ti ọna atunto.	Awọn ifihan agbara wọnyi ni a ka lati awọn iforukọsilẹ: CDR_Lock ti wa ni kika lati iforukọsilẹ rx_status3 (0x8C). SH_Locked ti wa ni kika lati rx_status4 (0x90) forukọsilẹ. jrx_sh_err_status ti wa ni kika lati iforukọsilẹ rx_err_status (0x60).	CDR_Lock ati SH_LOCK yẹ ki o jẹri si giga ti o baamu si nọmba awọn ọna. jrx_sh_err_status yẹ ki o jẹ  Awọn aaye bit ni jrx_sh_err_status sọwedowo fun sh_unlock_err, rx_gb_overflow_err, rx_gb_underflow_err, invalid_sync_header, src_rx_alarm, syspll_lock_err, ati cdr_locked_err.
SHA.2	Ṣayẹwo ipo Titiipa Akọsori Amuṣiṣẹpọ lẹhin titiipa akọsori amuṣiṣẹpọ ti waye (tabi lakoko apakan Imudara Dina pupọ) ati iduroṣinṣin.	invalid_sync_header jẹ kika fun ipo titiipa akọsori amuṣiṣẹpọ lati iforukọsilẹ (0x60[8]).	Ipo invalid_sync_header yẹ ki o jẹ 0.

Titesiwaju Multiblock (EMBA)

Table 2. Afikun Multiblock titete Igbeyewo igba

Ọran Idanwo		Idi		Apejuwe		Ilana ti o kọja
EMBA.1		Ṣayẹwo boya Titiipa Multiblock Extended nikan lẹhin iṣeduro ti Titiipa Akọsori Amuṣiṣẹpọ.		Awọn ifihan agbara wọnyi ni a ka nipasẹ awọn iforukọsilẹ:		Iye EMB_Locked_1 yẹ ki o dọgba si 1 ti o baamu si oju-ọna kọọkan. EMB_Lock_err yẹ ki o jẹ 0.
	Ọran Idanwo		Idi		Apejuwe		Ilana ti o kọja
					EMB_Locked_1 ti wa ni kika lati iforukọsilẹ rx_status5 (0x94). EMB_Lock_err ti wa ni kika lati rx_err_status (0x60[19]) forukọsilẹ.
	EMBA.2		Ṣayẹwo boya Ipo Titiipa Multiblock ti gbooro jẹ iduroṣinṣin (lẹhin titiipa multiblock ti o gbooro sii tabi titi ti ifipamọ rirọ yoo ti tu silẹ) pẹlu ko si multiblock ti ko tọ.		invalid_eomb_eoemb ti wa ni kika lati rx_err_status (0x60[10:9]) forukọsilẹ.		invalid_eomb_eoemb yẹ ki o jẹ "00".
	EMBA.3		Ṣayẹwo titete ọna.		Awọn iye wọnyi ni a ka lati awọn iforukọsilẹ: elastic_buf_over_flow ti wa ni kika lati rx_err_status (0x60 [20]) forukọsilẹ. elastic_buf_full ti wa ni kika lati rx_status6 (0x98) forukọsilẹ.		elastic_buf_over_flow yẹ ki o jẹ 0. Iye elastic_buf_full yẹ ki o dọgba si 1 ti o baamu si ọna kọọkan.

Layer Gbigbe olugba (TL)
Lati ṣayẹwo iduroṣinṣin data ti ṣiṣan data isanwo nipasẹ olugba (RX) JESD204C Intel FPGA IP ati Layer irinna, ADC ti tunto lati r.amp/ PRBS igbeyewo Àpẹẹrẹ. ADC naa tun ṣeto lati ṣiṣẹ pẹlu iṣeto kanna bi a ti ṣeto ninu JESD204C Intel FPGA IP. Awọn ramp/ PRBS checker ni FPGA fabric sọwedowo awọn ramp/ PRBS data iyege fun iseju kan. Iforukọsilẹ RX JESD204C Intel FPGA IP rx_err jẹ idibo nigbagbogbo fun iye odo fun iṣẹju kan.
Nọmba ti o wa ni isalẹ fihan iṣeto idanwo imọran fun ṣiṣe ayẹwo iyege data.

Aworan 3. Ṣayẹwo Iwa Integrity Data Lilo Ramp/ PRBS15 Oluyẹwo

Table 3. Transport Layer Igbeyewo igba

Ọran Idanwo	Idi	Apejuwe	Ilana ti o kọja
TL.1	Ṣayẹwo awọn gbigbe Layer maapu ti awọn data ikanni lilo ramp awoṣe igbeyewo.	Data_mode ti ṣeto si Ramp_mode. Awọn ifihan agbara wọnyi ni a ka nipasẹ awọn iforukọsilẹ: crc_err ti wa ni kika lati rx_err_status (0x60 [14]).  jrx_patchk_data_error ti wa ni kika lati tst_err0 forukọsilẹ.	crc_err yẹ ki o jẹ kekere lati kọja. jrx_patchk_data_error yẹ ki o jẹ kekere.
TL.2	Ṣayẹwo maapu Layer gbigbe ti ikanni data nipa lilo ilana idanwo PRBS15.	Data_mode ti ṣeto si prbs_mode. Awọn iye wọnyi ni a ka lati awọn iforukọsilẹ: crc_err ti wa ni kika lati rx_err_status (0x60 [14]). jrx_patchk_data_error ti wa ni kika lati tst_err0 forukọsilẹ.	crc_err yẹ ki o jẹ kekere lati kọja. jrx_patchk_data_error yẹ ki o jẹ kekere.

JESD204C Intel FPGA IP ati ADC atunto
Awọn paramita IP JESD204C Intel FPGA (L, M, ati F) ninu isanwo ohun elo yii jẹ atilẹyin abinibi nipasẹ ẹrọ AD9081. Oṣuwọn data transceiver , sampling aago, ati awọn miiran JESD204C paramita ni ibamu pẹlu awọn AD908D1 awọn ipo iṣẹ.
Idanwo isanwo ohun elo n ṣe imuse JESD204C Intel FPGA IP pẹlu iṣeto paramita atẹle.

Eto agbaye fun gbogbo iṣeto:

• E = 1
• CF = 0
• CS = 0
• Ipin-ipin = 1
• FCLK_MULP = 1
• WIDTH_MULP = 8
• SH_CONFIG = CRC-12
• Aago Isakoso FPGA (MHz) = 100

Awọn abajade Idanwo
Tabili ti o tẹle ni awọn abajade ti o ṣeeṣe ati itumọ wọn.

Table 4. Results Definition

Abajade	Itumọ
KỌJA	Ẹrọ Labẹ Idanwo (DUT) ni a ṣe akiyesi lati ṣafihan ihuwasi ibaramu.
Pass pẹlu comments	A ṣe akiyesi DUT lati ṣafihan ihuwasi ibaramu. Sibẹsibẹ, alaye afikun ti ipo naa wa (fun apẹẹrẹample: nitori awọn idiwọn akoko, apakan kan ti idanwo naa ni a ṣe).

Abajade	Itumọ
KUNA	A ṣe akiyesi DUT lati ṣafihan ihuwasi ti ko ni ibamu.
Ikilo	A ṣe akiyesi DUT lati ṣafihan ihuwasi ti ko ṣeduro.
Tọkasi comments	Lati awọn akiyesi, iwe-iwọle to wulo tabi ikuna ko le ṣe ipinnu. Alaye afikun ti ipo naa wa.

Tabili ti o tẹle fihan awọn abajade fun awọn ọran idanwo SHA.1, SHA.2, EMBA.1, EMBA.2, EMBA.3, TL.1, ati TL.2 pẹlu awọn iye oniwun ti L, M, F, oṣuwọn data, sampaago ling, aago ọna asopọ, ati awọn igbohunsafẹfẹ SYSREF.

Tabili 5. Abajade fun Awọn ọran Idanwo SHA.1, SHA.2, EMBA.1, EMBA.2, EMBA.3, TL.1, ati TL.2

Rara.	L	M	F	S	HD	E	N	NP	ADC Sampaago ling (MHz)	Aago Ẹrọ FPGA (MHz)	FPGA Aago fireemu (MHz)	FPGA Aago ọna asopọ (MHz)	Oṣuwọn Lane (Gbps)	Abajade
1	8	4	1	1	0	1	16	16	3000.00	375.00	375.00	375.00	24.75	Kọja

Igbeyewo Esi Comments
Ninu ọran idanwo kọọkan, RX JESD204C Intel FPGA IP ni ifijišẹ ṣe idasile titete akọsori amuṣiṣẹpọ, titete multiblock ti o gbooro, ati titi di ipele data olumulo.
Ko si ọran iduroṣinṣin data ti a ṣe akiyesi nipasẹ Ramp ati oluṣayẹwo PRBS fun awọn atunto JESD ti o bo gbogbo awọn ọna ti ara, tun ko si ayẹwo isanpada cyclic (CRC) ati aṣiṣe ni ibamu aṣẹ ni a ṣe akiyesi.
Lakoko awọn iyipo agbara kan, aṣiṣe deskew ọna le han pẹlu awọn atunto paramita. Lati yago fun aṣiṣe yii, awọn iye aiṣedeede LEMC yẹ ki o wa ni siseto tabi o le ṣe adaṣe eyi pẹlu ilana gbigba odiwọn. Fun alaye diẹ sii lori awọn iye ofin ti aiṣedeede LEMC, tọka si Ilana Tuning RBD ni Itọsọna olumulo F-tile JESD204C IP.

Alaye ti o jọmọ
RBD Tuning Mechanism

Lakotan
Ijabọ yii fihan afọwọsi ti JESD204C Intel FPGA IP ati wiwo itanna PHY pẹlu ẹrọ AD9081/9082 (R2 Silicon) to 24.75 Gbps fun ADC. Iṣeto ni pipe ati iṣeto ohun elo ni a fihan lati pese igbẹkẹle ninu interoperability ati iṣẹ ti awọn ẹrọ meji naa.

Itan Atunyẹwo Iwe-ipamọ fun AN 927: JESD204C Intel FPGA IP ati ADI AD9081 MxFE* ADC Interoperability Ijabọ fun Awọn ẹrọ Agilex F-Tile

Ẹya Iwe aṣẹ	Awọn iyipada
2022.04.25	Itusilẹ akọkọ.

AN 876: JESD204C Intel® FPGA IP ati ADI AD9081 MxFE* ADC Interoperability Iroyin fun Intel® Agilex® F-Tile Devices

Awọn iwe aṣẹ / Awọn orisun

intel JESD204C Intel FPGA IP ati ADI AD9081 MxFE ADC Interoperability. [pdf] Itọsọna olumulo JESD204C Intel FPGA IP ati ADI AD9081 MxFE ADC Interoperability Ijabọ, JESD204C, Intel FPGA IP ati ADI AD9081 MxFE ADC Interoperability Iroyin

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