JESD204C Intel FPGA IP uye ADI AD9081 MxFE ADC Interoperability Report User Guide

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1 JESD204C Intel FPGA IP uye ADI AD9081 MxFE ADC Interoperability Report

2 Product Information

3 Mirayiridzo Yekushandiswa Kwechigadzirwa

4 JESD204C Intel® FPGA IP uye ADI AD9081 MxFE* ADC Interoperability Report yeIntel® Agilex™ F-tile Devices

4.1 Tsanangudzo Yehurongwa

5 Zvinyorwa / Zvishandiso

5.1 References

JESD204C Intel FPGA IP uye ADI AD9081 MxFE ADC Interoperability Report

Product Information

Chigadzirwa chinorehwa mubhuku remushandisi ndeye JESD204C Intel FPGA IP. Icho chikamu chehardware chinoshandiswa pamwe chete neIntel Agilex I-Series F-Tile Demo Board uye iyo ADI AD9081-FMCA-EBZ EVM. Iyo IP inomisikidzwa muDuplex modhi asi nzira yekugamuchira ndiyo chete inoshandiswa. Iyo inogadzira 375 MHz yekubatanidza wachi uye 375 MHz furemu wachi. The hardware setup yeADC interoperability test inoratidzwa muFigure 1. IP inoda kuti SYSREF ipiwe newachi jenareta inopa JESD204C Intel FPGA IP mudziyo wachi.

Mirayiridzo Yekushandiswa Kwechigadzirwa

Hardware Setup
Kumisikidza hardware yekushandisa iyo JESD204C Intel FPGA IP, tevera matanho aya:

Batanidza iyo ADI AD9081-FMCA-EBZ EVM kuFMC + yekubatanidza yeIntel Agilex I-Series F-Tile Demo Board.
Ita shuwa kuti chiratidzo cheSYSREF chinopihwa newachi jenareta inopa iyo JESD204C Intel FPGA IP mudziyo wachi.

Tsanangudzo Yehurongwa
Iyo system-level dhizaini inoratidza kuti akasiyana mamodule akabatana sei mune iyi dhizaini. Inosanganisira Intel Agilex-I F-tile Demo Board, Intel Agilex F-tile Device, Top-Level RTL, Platform Designer System, Pattern Generator, Pattern Checker, F-Tile JESD204C Duplex IP Core, uye wachi dzakasiyana-siyana uye nzvimbo dzekutarisana.

Interoperability Methodology
Receiver Data Link Layer
Iyi nharaunda yekuyedza inovhara nyaya dzebvunzo dzesync musoro kurongeka (SHA) uye yakawedzera multiblock alignment (EMBA). Iyo JESD204C Intel FPGA IP inoverenga marejista kubva kune data link layer panguva yebvunzo, inoanyora mu log. files, uye inovaona kuti vapfuure maitiro kuburikidza neTCL zvinyorwa.

JESD204C Intel® FPGA IP uye ADI AD9081 MxFE* ADC Interoperability Report yeIntel® Agilex™ F-tile Devices

Iyo JESD204C Intel® FPGA IP ndeyekumhanya-mhanya-kusvika-kunongedzera serial interface intellectual property (IP).
Iyo JESD204C Intel FPGA IP yakaedzwa-hardware ine akati wandei akasarudzwa JESD204C anoenderana analog-to-digital converter (ADC) zvishandiso.
Chirevo ichi chinoratidza kudyidzana kweJESD204C Intel FPGA IP neAD9081 Mixed Signal Front End (MxFE*) evaluation module (EVM) kubva kuAnalog Devices Inc. (ADI). Zvikamu zvinotevera zvinotsanangura nzira yekutarisa hardware uye mhinduro dzebvunzo.

Related Information
F-tile JESD204C Intel FPGA IP User Guide

Hardware uye Software Zvinodiwa
Iyo yekudyidzana bvunzo inoda zvinotevera Hardware uye software maturusi: Hardware

Intel Agilex™ I-Series F-tile Demo Board (AGIB027R29A1E2VR0) ine 12V simba adapta

Analog Devices (ADI) AD9081 MxFE* EVM (AD9081-FMCA-EBZ, Rev C)
Skywork Si5345-D Evaluation Board (Si5345-D-EVB)

SMA murume kune SMP murume
SMP murume kune SMP tambo

Software

Intel Quartus® Prime Pro Edition software shanduro 21.4

AD9081_API vhezheni 1.1.0 kana nyowani (Linux application, inodiwa kune AD9081 EVM kumisikidza)

Related Information

AD9081/AD9082 Sisitimu Yekuvandudza Mushandisi Gwaro
Skyworks Si5345-D Yekuongorora Bhodhi Rekushandisa Guide

Hardware Setup
Iyo JESD204C Intel FPGA IP inomisikidzwa muDuplex modhi asi nzira yekugamuchira ndiyo chete inoshandiswa. KuFCLK_MULP =1, WIDTH_MULP = 8, S = 1, iyo core PLL inogadzira 375 MHz yekubatanidza wachi uye 375 MHz furemu wachi.
Iyo Intel Agilex I-Series F-Tile Demo Board inoshandiswa neADI AD9081-FMCA-EBZ EVM yakabatana neFMC+ yekubatanidza yebhodhi rekusimudzira. The hardware setup yeADC interoperability test inoratidzwa muHardware Setup figure.- • Iyo AD9081-FMCA-EBZ EVM inotora simba kubva kuIntel Agilex I-Series F-Tile Demo Board kuburikidza neFMC+ connector.

Iyo F-tile transceiver uye JESD204C Intel FPGA IP core PLL referensi wachi inopihwa neSi5345-D-EVB kuburikidza neSMA kune SMP tambo. Seta MUX_DIP_SW0 kumusoro paAgilex-I F-Tile Demo Board kuona kuti U22 iri kutora CLKIN1 yakabatana netambo yeSMP.

Iyo Si5345-D-EVB inopa chinongedzo wachi kune HMC7044 programmable wachi jenareta iripo muAD9081 EVM kuburikidza neSMP kune SMP tambo.
Iyo yekutarisira wachi yeJESD204C Intel FPGA IP musimboti inopihwa neSilicon Labs Si5332 programmable wachi jenareta iripo muIntel Agilex I-Series F-tile Demo Board.

Iyo HMC7044 programmable wachi jenareta inopa iyo AD9081 mudziyo referensi wachi. Iyo phase-yakiyiwa loop (PLL) iripo muAD9081 mudziyo inogadzira inodiwa ADC s.ampLing wachi kubva pachigadzirwa chekutarisa wachi.
Kune Subclass 1, iyo HMC7044 wachi jenareta inogadzira iyo SYSREF chiratidzo cheAD9081 mudziyo uye yeJESD204C Intel FPGA IP kuburikidza neFMC + yekubatanidza.

Aihwate: Intel inokurudzira iyo SYSREF kuti ipiwe newachi jenareta inopa iyo JESD204C Intel FPGA IP mudziyo wachi.

Tsanangudzo Yehurongwa

Iyi inotevera system-level dhizaini inoratidza kuti akasiyana ma module akabatana sei mune iyi dhizaini.

Mufananidzo 2. Dhiyagiramu yeSystem

Notes:

M ndiyo nhamba yevashanduri.
S ndiyo nhamba yeanoparidzirwa sampzvishoma pa converter per furemu.
WIDTH_MULP ndiyo inowedzeredza data yehupamhi pakati pechishandiso layer uye yekutakura layer.
N ndiyo nhamba yemabhiti ekushandura pashanduro.
CS ndiyo nhamba yekudzora mabhiti pashanduko samples.

Mugadziriro iyi, semuenzanisoample L = 8, M = 4, uye F = 1, nhamba ye data yemigwagwa ye transceiver ndeye 24.75 Gbps.
Iyo Si5332 OUT1 inogadzira 100 MHz wachi kusvika mgmt_clk. Si5345-D-EVB inogadzira mawachi maviri, 375 MHz uye 100 MHz. Iyo 375 MHz inopihwa kune yakadzamirirwa multiplexer muIntel Agilex I-Series F-tile Demo Board kuburikidza neJ19 SMA port. Iyo inobuda wachi yeyakamisikidzwa multiplexer inotyaira iyo F-tile transceiver referensi wachi (refclk_xcvr) uye JESD204C Intel FPGA IP core PLL referensi wachi (refclk_core). 100 MHz kubva kuSi5345-D-EVB yakabatana neHMC7044 programmable wachi jenareta iripo muAD9081 EVM sekuisa wachi.
(EXT_HMCREF).

Iyo HCM7044 inogadzira periodic SYSREF chiratidzo che11.71875 MHz kuburikidza neFMC Connector.
Iyo JESD204C Intel FPGA IP inomisikidzwa muDuplex modhi asi nzira yekugamuchira ndiyo chete inoshandiswa.

Interoperability Methodology
Chikamu chinotevera chinotsanangura zvinangwa zvebvunzo, maitiro, uye maitiro ekupasa. Muedzo unobata nzvimbo dzinotevera:

Receiver data link layer
Receiver transport layer

Receiver Data Link Layer
Iyi nharaunda yekuyedza inovhara nyaya dzebvunzo dzesync musoro kurongeka (SHA) uye yakawedzera multiblock alignment (EMBA).
Pane chinongedzo tanga kumusoro, mushure mekugashira patsva, iyo JESD204C Intel FPGA IP inotanga kutsvaga sync musoro rwizi runofambiswa nemudziyo. Aya anotevera marejista kubva ku data link layer anoverengwa panguva yebvunzo, yakanyorwa mu log files, uye yakavimbiswa kupasa nzira kuburikidza neTCL zvinyorwa.

Related Information
F-tile JESD204C Intel FPGA IP User Guide

Sync Header Alignment (SHA)
Tafura 1. Sync Header Alignment Test Cases

Test Case	Chinangwa	Tsanangudzo	Kupfuura Criteria
SHA.1	Tarisa kana Sync Header Lock yakasimbiswa mushure mekupedzwa kwekutevedzana kwekugadzirisa.	Aya masaini anotevera anoverengwa kubva kumarejista: CDR_Lock inoverengwa kubva murejista rx_status3 (0x8C). SH_Locked inoverengwa kubva parx_status4 (0x90) register. jrx_sh_err_status inoverengwa kubva murejista rx_err_status (0x60).	CDR_Lock uye SH_LOCK zvinofanirwa kusimbisirwa kumusoro zvinoenderana nehuwandu hwemigwagwa. jrx_sh_err_status inofanira kuva Iyo bit fields mu jrx_sh_err_status inotarisa sh_unlock_err, rx_gb_overflow_err, rx_gb_underflow_err, invalid_sync_header, src_rx_alarm, syspll_lock_err, uye cdr_locked_err.
SHA.2	Tarisa Sync Header Lock mamiriro mushure mekubatanidza musoro kukiya kwaitwa (kana panguva yeYakawedzerwa Multi-Block Alignment chikamu) uye yakagadzikana.	invalid_sync_header inoverengerwa Sync Header kukiya mamiriro kubva kurejista (0x60[8]).	invalid_sync_header mamiriro anofanira kunge ari 0.

Yakawedzerwa Multiblock Alignment (EMBA)

Tafura 2. Yakawedzerwa Multiblock Alignment Test Cases

Test Case		Chinangwa		Tsanangudzo		Kupfuura Criteria
EMBA.1		Tarisa kana iyo Yakawedzerwa Multiblock Lock yakasimbiswa chete mushure mekutaura kweSync Header Lock.		Aya masaini anotevera anoverengwa kuburikidza nerejista:		Huwandu hweEMB_Locked_1 hunofanira kuenzana ne1 inoenderana neimwe nzira. EMB_Lock_err inofanira kuva 0.

	Test Case		Chinangwa		Tsanangudzo		Kupfuura Criteria
					EMB_Locked_1 inoverengwa kubva murejista rx_status5 (0x94). EMB_Lock_err inoverengwa kubva mugwaro re rx_err_status (0x60[19]).
	EMBA.2		Tarisa kana iyo Yakawedzerwa Multiblock Lock chimiro yakagadzikana (mushure mekuwedzera multiblock kukiya kana kusvika iyo elastic buffer yaburitswa) pamwe chete isina invalid multiblock.		invalid_eomb_eoemb inoverengwa kubva kurx_err_status (0x60[10:9]) register.		invalid_eomb_eoemb inofanira kunge iri "00".
	EMBA.3		Tarisa kurongeka kwenzira.		Izvi zvinotevera zvakakosha zvinoverengwa kubva kumarejista: elastic_buf_over_flow inoverengwa kubva kurx_err_status (0x60[20]) register. elastic_buf_full inoverengwa kubva kurx_status6 (0x98) rejista.		elastic_buf_over_flow inofanira kuva 0. Iyo elastic_buf_full value inofanirwa kuenzana ne1 inoenderana neimwe nzira.

Receiver Transport Layer (TL)
Kuti utarise kutendeseka kwedhata rekubhadhara data rwizi kuburikidza neanogamuchira (RX) JESD204C Intel FPGA IP uye yekufambisa layer, iyo ADC inogadzirirwa r.amp/ PRBS bvunzo patani. Iyo ADC yakaiswa zvakare kuti ishande neiyo dhizaini seyakaiswa muJESD204C Intel FPGA IP. The ramp/ PRBS cheki mumucheka weFPGA inotarisa iyo ramp/ PRBS data kutendeseka kweminiti imwe. Iyo RX JESD204C Intel FPGA IP rejista rx_err inovhoterwa ichienderera kune zero kukosha kweminiti imwe.
Nhamba iri pazasi inoratidza iyo conceptual test setup yekutarisa kutendeseka kwedata.

Mufananidzo 3. Data Integrity Check Uchishandisa Ramp/PRBS15 Checker

Tafura 3. Transport Layer Test Cases

Test Case

Chinangwa

Tsanangudzo

Kupfuura Criteria

TL.1

Tarisa iyo yekutakura layer yemepu ye data chiteshi uchishandisa ramp test pattern.

Data_mode yakaiswa kuRamp_modhi.

Aya masaini anotevera anoverengwa kuburikidza nerejista:

crc_err inoverengwa kubva ku rx_err_status (0x60[14]).
jrx_patchk_data_error inoverengwa kubva mukunyoresa tst_err0.

crc_err inofanira kunge yakaderera kuti ipfuure.
jrx_patchk_data_error inofanira kunge yakaderera.

TL.2

Tarisa dhizaini yekutakura mepu yechiteshi chedata uchishandisa PRBS15 bvunzo patani.

Data_mode yakaiswa kune prbs_mode.

Izvi zvinotevera zvakakosha zvinoverengwa kubva kumarejista:

crc_err inoverengwa kubva ku rx_err_status (0x60[14]).
jrx_patchk_data_error inoverengwa kubva mukunyoresa tst_err0.

crc_err inofanira kunge yakaderera kuti ipfuure.
jrx_patchk_data_error inofanira kunge yakaderera.

JESD204C Intel FPGA IP uye ADC Configurations
Iyo JESD204C Intel FPGA IP paramita (L, M, uye F) mune iyi hardware yekutarisa inotsigirwa neiyo AD9081 mudziyo. The transceiver data rate, sampling wachi, uye mamwe JESD204C paramita anotevedzera AD908D1 kushanda mamiriro.
Iyo hardware yekuongorora yekuongorora inoshandisa iyo JESD204C Intel FPGA IP neinotevera paramende kumisikidzwa.

Global setting yezvese zvigadziriso:

E = mazana matanhatu

CF = 0
CS = 0
Subclass = 1

FCLK_MULP = 1
WIDTH_MULP = 8
SH_CONFIG = CRC-12

FPGA Management Clock (MHz) = 100

Test Results
Tafura inotevera ine zvingangoitika uye tsananguro yavo.

Tafura 4. Migumisiro Tsanangudzo

Mhedzisiro	Tsanangudzo
PASS	Chishandiso Chiri Muedzo (DUT) chakacherechedzwa kuratidza hunhu hunoenderana.
PASS nemashoko	DUT yakacherechedzwa kuratidza hunhu hunoenderana. Nekudaro, imwe tsananguro yekuwedzera yemamiriro ezvinhu inosanganisirwa (example: nekuda kwekugumira nguva, chikamu cheyedzo chete chakaitwa).

Mhedzisiro	Tsanangudzo
FAIL	DUT yakacherechedzwa kuratidza maitiro asina kuenderana.
Yambiro	DUT yakacherechedzwa kuratidza hunhu husingakurudzirwe.
Tarisa kune zvakataurwa	Kubva pane zvakaonekwa, kupasa kwakakodzera kana kukundikana hakugone kuzivikanwa. Imwe tsananguro yokuwedzera yemamiriro acho ezvinhu inosanganisirwa.

Tafura inotevera inoratidza mhedzisiro yenyaya dzebvunzo SHA.1, SHA.2, EMBA.1, EMBA.2, EMBA.3, TL.1, uye TL.2 ine ma values eL, M, F, data rate, sampLing wachi, chinongedzo wachi, uye SYSREF frequency.

Table 5. Zvabuda paTest Cases SHA.1, SHA.2, EMBA.1, EMBA.2, EMBA.3, TL.1, and TL.2

Aihwa.	L	M	F	S	HD	E	N	NP	ADC SampLing Clock (MHz)	FPGA Device Clock (MHz)	FPGA Frame Clock (MHz)	FPGA Batanidza Wachi (MHz)	Lane Rate (Gbps)	Mhedzisiro
1	8	4	1	1	0	1	16	16	3000.00	375.00	375.00	375.00	24.75	Pass

Test Result Comments
Muchiitiko chega chega chekuyedza, iyo RX JESD204C Intel FPGA IP inobudirira kumisikidza iyo sync musoro kurongeka, yakawedzera multiblock kurongeka, uye kusvika mushandisi data chikamu.
Hapana data yekuvimbika nyaya inocherechedzwa neRamp uye PRBS cheki cheJESD zvigadziriso zvinofukidza nzira dzese dzemuviri, zvakare hapana cyclic redundancy cheki (CRC) uye kukanganisa kwekuraira kunoonekwa.
Munguva yemamwe magetsi emagetsi, lane deskew kukanganisa inogona kuoneka ine parameter zvigadziriso. Kuti udzivise chikanganiso ichi, iyo LEMC yekubvisa tsika dzinofanirwa kurongwa kana iwe unogona otomatiki izvi neiyo calibration yekutsvaira maitiro. Kuti uwane rumwe ruzivo nezve kukosha kwemutemo kweLEMC kubviswa, tarisa kuRBD Tuning Mechanism muF-tile JESD204C IP Mushandisi Wekushandisa.

Related Information
RBD Tuning Mechanism

Summary
Chirevo ichi chinoratidza kusimbiswa kweJESD204C Intel FPGA IP uye PHY yemagetsi interface ine AD9081/9082 (R2 Silicon) mudziyo unosvika 24.75 Gbps yeADC. Iyo yakazara gadziriso uye kuseta kwehardware inoratidzwa kupa chivimbo mukudyidzana uye kuita kwemidziyo miviri.

Gwaro Rekudzokorora Nhoroondo yeAN 927: JESD204C Intel FPGA IP uye ADI AD9081 MxFE * ADC Kupindirana Chirevo cheIntel Agilex F-Tile Devices

Document Version	Kuchinja
2022.04.25	Kusunungurwa kwekutanga.

AN 876: JESD204C Intel® FPGA IP uye ADI AD9081 MxFE* ADC Interoperability Report yeIntel® Agilex® F-Tile Devices

Zvinyorwa / Zvishandiso

intel JESD204C Intel FPGA IP uye ADI AD9081 MxFE ADC Interoperability Report [pdf] Bhuku reMushandisi
JESD204C Intel FPGA IP uye ADI AD9081 MxFE ADC Interoperability Report, JESD204C, Intel FPGA IP uye ADI AD9081 MxFE ADC Interoperability Report

References

User Manual