JESD204C Intel FPGA IP ndi ADI AD9081 MxFE ADC Interoperability Report

Zambiri Zamalonda

Zomwe zikutchulidwa m'buku la ogwiritsa ntchito ndi JESD204C Intel FPGA IP. Ndi gawo la hardware lomwe limagwiritsidwa ntchito molumikizana ndi Intel Agilex I-Series F-Tile Demo Board ndi ADI AD9081-FMCA-EBZ EVM. IP imakhazikitsidwa mu Duplex mode koma njira yokhayo yolandirira ndiyomwe imagwiritsidwa ntchito. Imapanga wotchi yolumikizira ya 375 MHz ndi wotchi ya chimango ya 375 MHz. Kukonzekera kwa hardware kwa kuyesa kwa mgwirizano wa ADC kukuwonetsedwa mu Chithunzi 1. IP imafuna SYSREF kuti iperekedwe ndi jenereta ya wotchi yomwe imatulutsa wotchi ya chipangizo cha JESD204C Intel FPGA IP.

Malangizo Ogwiritsira Ntchito Zogulitsa

Kukonzekera kwa Hardware
Kukhazikitsa zida zogwiritsira ntchito JESD204C Intel FPGA IP, tsatirani izi:

1. Lumikizani ADI AD9081-FMCA-EBZ EVM ku cholumikizira cha FMC+ cha Intel Agilex I-Series F-Tile Demo Board.
2. Onetsetsani kuti chizindikiro cha SYSREF chikuperekedwa ndi jenereta ya wotchi yomwe imatulutsa wotchi ya chipangizo cha JESD204C Intel FPGA IP.

Kufotokozera Kwadongosolo
Chojambula chamtundu wadongosolo chikuwonetsa momwe ma module osiyanasiyana amalumikizirana pamapangidwe awa. Zimaphatikizapo Intel Agilex-I F-tile Demo Board, Intel Agilex F-tile Device, Top-Level RTL, Platform Designer System, Pattern Generator, Pattern Checker, F-Tile JESD204C Duplex IP Core, ndi mawotchi osiyanasiyana ndi mawonekedwe.

Interoperability Njira
Receiver Data Link Layer
Dera loyesererali limakhudza mayeso a kulunzanitsa mutu wamutu (SHA) ndi kulumikizana kowonjezera kwa ma block block (EMBA). JESD204C Intel FPGA IP imawerenga zolembetsa kuchokera pa data link layer panthawi ya mayeso, ndikuzilemba mu log. files, ndikuwatsimikizira kuti adutsa muzolemba za TCL.

JESD204C Intel® FPGA IP ndi ADI AD9081 MxFE* ADC Interoperability Report ya Intel® Agilex™ F-tile Devices

JESD204C Intel® FPGA IP ndi chida chothamanga kwambiri chofikira ku point serial interface intellectual property (IP).
JESD204C Intel FPGA IP yayesedwa ndi zida zingapo zosankhidwa za JESD204C zogwirizana ndi analog-to-digital converter (ADC).
Lipotili likuwunikira kugwirizana kwa JESD204C Intel FPGA IP ndi AD9081 Mixed Signal Front End (MxFE *) evaluation module (EVM) yochokera ku Analog Devices Inc. (ADI). Magawo otsatirawa akufotokoza njira yolipirira hardware ndi zotsatira zoyesa.

Zambiri Zogwirizana
F-tile JESD204C Intel FPGA IP User Guide

Zofunikira pa Hardware ndi Mapulogalamu
Mayeso ogwirizana amafunikira zida zotsatirazi ndi zida zamapulogalamu: Hardware

• Intel Agilex™ I-Series F-tile Demo Board (AGIB027R29A1E2VR0) yokhala ndi adaputala yamagetsi ya 12V
• Zida za Analogi (ADI) AD9081 MxFE* EVM (AD9081-FMCA-EBZ, Rev C)
• Skywork Si5345-D Evaluation Board (Si5345-D-EVB)
• SMA wamwamuna kupita ku SMP wamwamuna
• SMP wamwamuna kupita ku chingwe cha SMP

Mapulogalamu

• Pulogalamu ya Intel Quartus® Prime Pro Edition 21.4
• AD9081_API mtundu 1.1.0 kapena watsopano (pulogalamu ya Linux, yofunikira pakusintha kwa AD9081 EVM)

Zambiri Zogwirizana

• AD9081/AD9082 System Development User Guide
• Skyworks Si5345-D Evaluation Board User Guide

Kukonzekera kwa Hardware
JESD204C Intel FPGA IP imakhazikitsidwa mu Duplex mode koma njira yokhayo yolandila ndiyomwe imagwiritsidwa ntchito. Kwa FCLK_MULP =1, WIDTH_MULP = 8, S = 1, PLL yapakati imapanga wotchi yolumikizira ya 375 MHz ndi wotchi ya 375 MHz.
Intel Agilex I-Series F-Tile Demo Board imagwiritsidwa ntchito ndi ADI AD9081-FMCA-EBZ EVM yolumikizidwa ndi cholumikizira cha FMC + cha board yachitukuko. Kukonzekera kwa hardware kwa kuyesa kwa mgwirizano wa ADC kukuwonetsedwa muzithunzi za Hardware Setup.- • AD9081-FMCA-EBZ EVM imatenga mphamvu kuchokera ku Intel Agilex I-Series F-Tile Demo Board kudzera pa FMC + cholumikizira.

• Mawotchi a F-tile transceiver ndi JESD204C Intel FPGA IP core PLL mawotchi amaperekedwa ndi Si5345-D-EVB kudzera pa SMA kupita ku chingwe cha SMP. Khazikitsani MUX_DIP_SW0 pamwamba pa Agilex-I F-Tile Demo Board kuti muwonetsetse kuti U22 ikutenga CLKIN1 yolumikizidwa ndi chingwe cha SMP.
• Si5345-D-EVB imapereka wotchi yowunikira kwa HMC7044 jenereta yosinthika ya wotchi yomwe ilipo mu AD9081 EVM kudzera pa SMP kupita ku chingwe cha SMP.
• Wotchi yoyang'anira ya JESD204C Intel FPGA IP core imaperekedwa ndi Silicon Labs Si5332 jenereta yosinthika yopezeka mu Intel Agilex I-Series F-tile Demo Board.
• Wotchi yosinthika ya HMC7044 imapereka wotchi yolozera chipangizo cha AD9081. Phase-locked loop (PLL) yomwe ilipo mu chipangizo cha AD9081 imapanga ma ADC omwe amafunidwa.ampLing wotchi yochokera pa wotchi yolozera chipangizocho.
• Kwa Subclass 1, jenereta ya wotchi ya HMC7044 imapanga chizindikiro cha SYSREF pa chipangizo cha AD9081 ndi JESD204C Intel FPGA IP kudzera pa cholumikizira cha FMC +.

Ayite: Intel imalimbikitsa SYSREF kuti iperekedwe ndi jenereta ya wotchi yomwe imatulutsa wotchi ya chipangizo cha JESD204C Intel FPGA IP.

Kufotokozera Kwadongosolo

Chojambula chotsatira cha dongosololi chikuwonetsa momwe ma modules osiyanasiyana amagwirizanirana pamapangidwe awa.

Chithunzi 2. Chithunzi cha System

Zolemba:

1. M ndi chiwerengero cha otembenuza.
2. S ndi chiwerengero cha sampzochepa pa Converter pa chimango.
3. WIDTH_MULP ndiye chochulukitsira data m'lifupi pakati pa gawo la pulogalamu ndi mayendedwe.
4. N ndi chiwerengero cha kutembenuka bits pa Converter.
5. CS ndi chiwerengero cha ma control bits pa kutembenuka samples.

Pakukhazikitsa uku, mwachitsanzoample L = 8, M = 4, ndi F = 1, mlingo wa data wa misewu ya transceiver ndi 24.75 Gbps.
Si5332 OUT1 imapanga wotchi ya 100 MHz mpaka mgmt_clk. Si5345-D-EVB imapanga maulendo awiri a wotchi, 375 MHz ndi 100 MHz. 375 MHz imaperekedwa ku multiplexer ophatikizidwa mu Intel Agilex I-Series F-tile Demo Board kudzera pa doko la J19 SMA. Wotchi yotulutsa ya multiplexer yophatikizidwa imayendetsa wotchi ya F-tile transceiver (refclk_xcvr) ndi JESD204C Intel FPGA IP core PLL wotchi (refclk_core). 100 MHz kuchokera ku Si5345-D-EVB yolumikizidwa ndi jenereta ya wotchi ya HMC7044 yomwe ikupezeka mu AD9081 EVM ngati cholowetsa wotchi.
(EXT_HMCREF).

HCM7044 imapanga chizindikiro cha SYSREF cha 11.71875 MHz kudzera pa FMC Connector.
JESD204C Intel FPGA IP imakhazikitsidwa mu Duplex mode koma njira yokhayo yolandila ndiyomwe imagwiritsidwa ntchito.

Interoperability Njira
Gawo lotsatirali likufotokoza zolinga za mayeso, ndondomeko, ndi njira zopambana. Mayesowa akukhudza magawo awa:

• Chigawo cha ulalo wa data yolandila
• Receiver transport layer

Receiver Data Link Layer
Dera loyesererali limakhudza mayeso a kulunzanitsa mutu wamutu (SHA) ndi kulumikizana kowonjezera kwa ma block block (EMBA).
Pa ulalo woyambira, wolandila atayambiranso, JESD204C Intel FPGA IP imayamba kuyang'ana mtsinje wolumikizira mutu womwe umafalitsidwa ndi chipangizocho. Ma regista otsatirawa kuchokera ku data link layer amawerengedwa panthawi ya mayeso, olembedwa mu log files, ndikutsimikiziridwa kuti adutse muzolemba za TCL.

Zambiri Zogwirizana
F-tile JESD204C Intel FPGA IP User Guide

Kuyanjanitsa Mutu Wamutu (SHA)
Table 1. Lunzanitsa Milandu Yoyesa Kulinganiza kwa Mutu

Mlandu Woyesera	Cholinga	Kufotokozera	Njira Zodutsa
SHA.1	Yang'anani ngati Sync Header Lock imatsimikiziridwa mukamaliza kutsata kukonzanso.	Zizindikiro zotsatirazi zimawerengedwa kuchokera m'marejista: CDR_Lock imawerengedwa kuchokera mu kaundula rx_status3 (0x8C). SH_Locked imawerengedwa kuchokera ku rx_status4 (0x90). jrx_sh_err_status imawerengedwa kuchokera ku rx_err_status (0x60).	CDR_Lock ndi SH_LOCK ziyenera kutsimikiziridwa kuti ndizokwera molingana ndi kuchuluka kwa mayendedwe. jrx_sh_err_status iyenera kukhala  Bit fields mu jrx_sh_err_status cheke sh_unlock_err, rx_gb_overflow_err, rx_gb_underflow_err, invalid_sync_header, src_rx_alarm, syspll_lock_err, ndi cdr_locked_err.
SHA.2	Yang'anani momwe Sync Header Lock ilili mukatha kulunzanitsa kutseka kwamutu kukwaniritsidwa (kapena pagawo lowonjezera la Multi-Block Alignment) ndikukhazikika.	invalid_sync_header imawerengedwa ngati Sync Header lock kuchokera ku register (0x60[8]).	invalid_sync_header udindo uyenera kukhala 0.

Kuwonjezera Multiblock Alignment (EMBA)

Table 2. Milandu Yowonjezereka Yoyeserera Kulinganiza kwa Multiblock

Mlandu Woyesera		Cholinga		Kufotokozera		Njira Zodutsa
EMBA.1		Yang'anani ngati Chotsekera Chowonjezera cha Multiblock chikutsimikiziridwa pokhapokha atatsimikizira Sync Header Lock.		Zizindikiro zotsatirazi zimawerengedwa kudzera m'marejista:		Mtengo wa EMB_Locked_1 uyenera kukhala wofanana ndi 1 wofanana ndi msewu uliwonse. EMB_Lock_err iyenera kukhala 0.
	Mlandu Woyesera		Cholinga		Kufotokozera		Njira Zodutsa
					EMB_Locked_1 imawerengedwa kuchokera mu kaundula rx_status5 (0x94). EMB_Lock_err imawerengedwa kuchokera mu kaundula rx_err_status (0x60[19]).
	EMBA.2		Yang'anani ngati mawonekedwe a Extended Multiblock Lock ali okhazikika (pambuyo pa loko yotalikirapo kapena mpaka buffer yotanuka itatulutsidwa) popanda kutsekereza kolakwika.		invalid_eomb_eoemb imawerengedwa kuchokera mu kaundula rx_err_status (0x60[10:9]).		invalid_eomb_eoemb iyenera kukhala "00".
	EMBA.3		Yang'anani momwe msewu uliri.		Mfundo zotsatirazi zimawerengedwa kuchokera m'marejista: elastic_buf_over_flow imawerengedwa kuchokera ku rx_err_status (0x60[20]) rejista. elastic_buf_full imawerengedwa kuchokera ku rx_status6 (0x98).		elastic_buf_over_flow iyenera kukhala 0. Elastic_buf_full value iyenera kukhala yofanana ndi 1 yofanana ndi njira iliyonse.

Receiver Transport Layer (TL)
Kuti muwone kukhulupirika kwa data yamtundu wa data yolipira kudzera pa wolandila (RX) JESD204C Intel FPGA IP ndi gawo la zoyendera, ADC idasinthidwa kukhala r.amp/ PRBS chitsanzo choyesera. ADC imayikidwanso kuti igwire ntchito ndi kasinthidwe komweko monga kukhazikitsidwa mu JESD204C Intel FPGA IP. The ramp/ PRBS chowunikira mu nsalu ya FPGA imayang'ana ramp/ PRBS data kukhulupirika kwa mphindi imodzi. RX JESD204C Intel FPGA IP registry rx_err imasankhidwa mosalekeza pamtengo wa zero kwa mphindi imodzi.
Chithunzi chili m'munsichi chikuwonetsa kukhazikitsidwa kwa mayeso oyesa kuwunika kukhulupirika kwa data.

Chithunzi 3. Data Integrity Check Pogwiritsa ntchito Ramp/PRBS15 Checker

Table 3. Transport Layer Test Cases

Mlandu Woyesera	Cholinga	Kufotokozera	Njira Zodutsa
TL.1	Onani mapu a mayendedwe a mayendedwe a data pogwiritsa ntchito ramp chitsanzo choyesera.	Data_mode yakhazikitsidwa ku Ramp_modi. Zizindikiro zotsatirazi zimawerengedwa kudzera m'marejista: crc_err imawerengedwa kuchokera ku rx_err_status (0x60[14]).  jrx_patchk_data_error imawerengedwa kuchokera patsamba la tst_err0.	crc_err iyenera kukhala yotsika kuti idutse. jrx_patchk_data_error iyenera kukhala yotsika.
TL.2	Yang'anani mapu a mayendedwe a njira ya data pogwiritsa ntchito PRBS15 test pattern.	Data_mode yakhazikitsidwa ku prbs_mode. Mfundo zotsatirazi zimawerengedwa kuchokera m'marejista: crc_err imawerengedwa kuchokera ku rx_err_status (0x60[14]). jrx_patchk_data_error imawerengedwa kuchokera patsamba la tst_err0.	crc_err iyenera kukhala yotsika kuti idutse. jrx_patchk_data_error iyenera kukhala yotsika.

JESD204C Intel FPGA IP ndi ADC Configurations
Magawo a JESD204C Intel FPGA IP (L, M, ndi F) pakutuluka kwa hardware uku amathandizidwa ndi chipangizo cha AD9081. Mtengo wa data wa transceiver, sampling wotchi, ndi magawo ena a JESD204C amagwirizana ndi machitidwe opangira AD908D1.
Kuyesa kwa hardware kumagwiritsira ntchito JESD204C Intel FPGA IP ndi kasinthidwe kotsatira.

Zokonda zapadziko lonse lapansi pazosintha zonse:

• E = 1
• CF = 0
• CS = 0
• Gulu = 1
• FCLK_MULP = 1
• WIDTH_MULP = 8
• SH_CONFIG = CRC-12
• FPGA Management Clock (MHz) = 100

Zotsatira za mayeso
Gome lotsatirali lili ndi zotsatira zomwe zingatheke komanso tanthauzo lake.

Table 4. Tanthauzo la Zotsatira

Zotsatira	Tanthauzo
PASS	Device Under Test (DUT) idawonedwa kuti iwonetse machitidwe ofanana.
PASS ndi ndemanga	DUT idawonedwa kuti ikuwonetsa machitidwe ofanana. Komabe, mafotokozedwe owonjezera a momwe zinthu ziliri akuphatikizidwa (mwachitsanzoample: chifukwa cha kuchepa kwa nthawi, gawo limodzi lokha la kuyezetsa lidachitidwa).

Zotsatira	Tanthauzo
ZOLEPHERA	DUT idawonedwa kuti ikuwonetsa machitidwe osatsata.
Chenjezo	DUT idawonedwa kuti ikuwonetsa machitidwe osavomerezeka.
Onani ndemanga	Kuchokera paziwonetsero, chiphaso chovomerezeka kapena kulephera sikungadziwike. Kufotokozera kowonjezereka kwa mkhalidwewo kumaphatikizidwa.

Gome lotsatirali likuwonetsa zotsatira za mayeso a SHA.1, SHA.2, EMBA.1, EMBA.2, EMBA.3, TL.1, ndi TL.2 okhala ndi ma L, M, F, kuchuluka kwa data, sampwotchi yaling'ono, wotchi yolumikizira, ndi ma frequency a SYSREF.

Table 5. Zotsatira za Mayeso SHA.1, SHA.2, EMBA.1, EMBA.2, EMBA.3, TL.1, and TL.2

Ayi.	L	M	F	S	HD	E	N	NP	ADC SampLing Clock (MHz)	FPGA Chipangizo Clock (MHz)	FPGA Wotchi ya chimango (MHz)	FPGA Lumikizani Clock (MHz)	Mtengo wa Lane (Gbps)	Zotsatira
1	8	4	1	1	0	1	16	16	3000.00	375.00	375.00	375.00	24.75	Pitani

Ndemanga Zazotsatira
Pachiyeso chilichonse choyesa, RX JESD204C Intel FPGA IP imakhazikitsa bwino kulumikizika kwa mutu, kukulitsa ma block block ambiri, komanso mpaka gawo la data la ogwiritsa ntchito.
Palibe vuto la kukhulupirika kwa data lomwe limawonedwa ndi Ramp ndi chowunikira cha PRBS pamasinthidwe a JESD omwe amaphimba mayendedwe onse amthupi, komanso palibe cheke cha cyclic redundancy chekeni (CRC) ndi kulakwitsa kwa lamulo kumawonedwa.
Panthawi ina yamagetsi, vuto la deskew lane likhoza kuwoneka ndi makonzedwe a parameter. Kuti mupewe cholakwika ichi, LEMC offset values ​​iyenera kukonzedwa kapena mutha kusintha izi ndi njira yosesa. Kuti mumve zambiri pamalamulo a LEMC offset, onani RBD Tuning Mechanism mu F-tile JESD204C IP User Guide.

Zambiri Zogwirizana
RBD Tuning Mechanism

Chidule
Lipotili likuwonetsa kutsimikizika kwa mawonekedwe amagetsi a JESD204C Intel FPGA IP ndi PHY ndi chipangizo cha AD9081/9082 (R2 Silicon) mpaka 24.75 Gbps ya ADC. Kukonzekera kwathunthu ndi kukhazikitsidwa kwa hardware kumasonyezedwa kuti apereke chidaliro mu kugwirizana ndi machitidwe a zipangizo ziwirizi.

Mbiri Yokonzanso Zolemba za AN 927: JESD204C Intel FPGA IP ndi ADI AD9081 MxFE* ADC Interoperability Report ya Intel Agilex F-Tile Devices

Document Version	Zosintha
2022.04.25	Kutulutsidwa koyamba.

AN 876: JESD204C Intel® FPGA IP ndi ADI AD9081 MxFE* ADC Interoperability Report ya Intel® Agilex® F-Tile Devices

Zolemba / Zothandizira

Intel JESD204C Intel FPGA IP ndi ADI AD9081 MxFE ADC Interoperability Report [pdf] Buku Logwiritsa Ntchito JESD204C Intel FPGA IP ndi ADI AD9081 MxFE ADC Interoperability Report, JESD204C, Intel FPGA IP ndi ADI AD9081 MxFE ADC Interoperability Report

Maumboni

• Buku Logwiritsa Ntchito