JESD204C Intel FPGA IP ma le ADI AD9081 MxFE ADC Interoperability Lipoti Taiala

Mataupu lalafi

1 JESD204C Intel FPGA IP ma le ADI AD9081 MxFE ADC Interoperability Lipoti

2 Fa'amatalaga o oloa

3 Fa'atonuga o le Fa'aaogaina o Mea

4 JESD204C Intel® FPGA IP ma le ADI AD9081 MxFE* ADC Interoperability Lipoti mo Intel® Agilex™ F-tile Devices

4.1 Fa'amatalaga Fa'atonu

5 Pepa / Punaoa

5.1 Fa'asinomaga

JESD204C Intel FPGA IP ma le ADI AD9081 MxFE ADC Interoperability Lipoti

Fa'amatalaga o oloa

O le oloa o loʻo taʻua i le tusi faʻaoga o le JESD204C Intel FPGA IP. O se vaega o meafaigaluega e faʻaaogaina faʻatasi ma le Intel Agilex I-Series F-Tile Demo Board ma le ADI AD9081-FMCA-EBZ EVM. O le IP o loʻo faʻaalia i le Duplex mode ae naʻo le auala e faʻaaogaina e faʻaaogaina. E fa'atupuina se uati feso'ota'iga 375 MHz ma se uati fa'avaa 375 MHz. O le seti meafaigaluega mo le suʻega faʻafesoʻotaʻi ADC o loʻo faʻaalia i le Ata 1. O le IP e manaʻomia le SYSREF e tuʻuina atu e le generator uati e maua mai ai le uati masini JESD204C Intel FPGA IP.

Fa'atonuga o le Fa'aaogaina o Mea

Seti Meafaigaluega
Ina ia setiina meafaigaluega mo le faʻaaogaina o le JESD204C Intel FPGA IP, mulimuli i laasaga nei:

Faʻafesoʻotaʻi le ADI AD9081-FMCA-EBZ EVM i le FMC + fesoʻotaʻiga o le Intel Agilex I-Series F-Tile Demo Board.
Ia mautinoa o loʻo tuʻuina atu le faailo SYSREF e le gaosiga o le uati lea e maua mai ai le JESD204C Intel FPGA IP device clock.

Fa'amatalaga Fa'atonu
O lo'o fa'aalia e le fa'asologa o faiga fa'aoga le feso'ota'iina o modules eseese i lenei mamanu. E aofia ai le Intel Agilex-I F-tile Demo Board, Intel Agilex F-tile Device, Top-Level RTL, Platform Designer System, Pattern Generator, Pattern Checker, F-Tile JESD204C Duplex IP Core, ma uati eseese ma fesoʻotaʻiga.

Metotia Felagolagomai
Layer Link Link Receiver
Ole vaega lea ole su'ega e aofia ai fa'ata'ita'iga mo le sync header alignment (SHA) ma le extended multiblock alignment (EMBA). O le JESD204C Intel FPGA IP e faitau tusi resitala mai le faʻamaumauga o fesoʻotaʻiga i le taimi o le suʻega, tusi i totonu o le ogalaau. files, ma fa'amaonia i latou mo le pasia o ta'iala i tusitusiga TCL.

JESD204C Intel® FPGA IP ma le ADI AD9081 MxFE* ADC Interoperability Lipoti mo Intel® Agilex™ F-tile Devices

O le JESD204C Intel® FPGA IP o se fa'asologa maualuga o le fa'asologa o le fa'asologa o mea tau le atamai (IP).
O le JESD204C Intel FPGA IP sa fa'ata'ita'iina i masini fa'atasi ma le tele o masini fa'aliliu analog-i-numera (ADC) ua filifilia.
O lenei lipoti o loʻo faʻamaonia ai le felagolagomai o le JESD204C Intel FPGA IP faʻatasi ma le AD9081 Mixed Signal Front End (MxFE *) suʻesuʻega module (EVM) mai Analog Devices Inc. (ADI). O vaega o lo'o mulimuli mai o lo'o fa'amatalaina ai le auala e siaki ai meafaigaluega ma fa'ai'uga o su'ega.

Fa'amatalaga Fa'atatau
F-tile JESD204C Intel FPGA IP Taiala mo Tagata

Meafaigaluega ma Polokalama Manaoga
O le su'ega felagolagoma'i e mana'omia ai masini ma mea faigaluega faakomepiuta nei: Meafaigaluega

Intel Agilex™ I-Series F-tile Demo Board (AGIB027R29A1E2VR0) faʻatasi ma le 12V faʻapipiʻi eletise

Mea Fa'atusa (ADI) AD9081 MxFE* EVM (AD9081-FMCA-EBZ, Rev C)
Skywork Si5345-D Komiti Iloiloga (Si5345-D-EVB)

SMA male ile SMP male
SMP male i SMP uaea

Polokalama

Intel Quartus® Prime Pro Edition polokalame polokalame 21.4

AD9081_API version 1.1.0 po'o le fou (Linux application, mana'omia mo AD9081 EVM configuration)

Fa'amatalaga Fa'atatau

AD9081/AD9082 Fa'atonuga Fa'aoga Fa'atonu
Skyworks Si5345-D Evaluation Board Guide Guide

Seti Meafaigaluega
O le JESD204C Intel FPGA IP o loʻo faʻapipiʻiina i le Duplex mode ae naʻo le auala e maua ai e faʻaaogaina. Mo FCLK_MULP =1, WIDTH_MULP = 8, S = 1, o le PLL autu e maua ai le 375 MHz feso'ota'iga uati ma le 375 MHz fa'avaa uati.
O le Intel Agilex I-Series F-Tile Demo Board o loʻo faʻaaogaina ma le ADI AD9081-FMCA-EBZ EVM e fesoʻotaʻi ma le fesoʻotaʻiga FMC + o le laupapa atinaʻe. O le seti meafaigaluega mo le suʻega interoperability ADC o loʻo faʻaalia i le Setup Setup figure.- • O le AD9081-FMCA-EBZ EVM e maua mai le mana mai le Intel Agilex I-Series F-Tile Demo Board e ala i le FMC + connector.

O le F-tile transceiver ma le JESD204C Intel FPGA IP core PLL reference Clocks o loʻo tuʻuina atu e Si5345-D-EVB e ala i SMA i SMP cable. Set MUX_DIP_SW0 i le maualuga i luga ole Agilex-I F-Tile Demo Board ina ia mautinoa o loʻo ave e U22 le CLKIN1 e fesoʻotaʻi i le SMP cable.

O le Si5345-D-EVB o loʻo tuʻuina atu se uati faʻasino i le HMC7044 programmable clock generator o loʻo iai i le AD9081 EVM e ala i SMP i SMP cable.
O le uati pulega mo le JESD204C Intel FPGA IP autu o loʻo tuʻuina atu e Silicon Labs Si5332 polokalama faʻapipiʻi uati o loʻo iai i le Intel Agilex I-Series F-tile Demo Board.

O le HMC7044 programmable clock generator e maua ai le AD9081 device reference clock. O le vaega loka loka (PLL) o loʻo iai i le masini AD9081 e faʻatupuina ai le ADC manaʻomia.ampling uati mai le uati faasinoga masini.
Mo le Vasega 1, o le HMC7044 uati fa'atupuina le fa'ailoga SYSREF mo le masini AD9081 ma mo le JESD204C Intel FPGA IP e ala i le feso'ota'iga FMC +.

Leaitu: Ua fautuaina e Intel le SYSREF e tuʻuina atu e le faʻaputuga o le uati e maua mai ai le uati masini JESD204C Intel FPGA IP.

Fa'amatalaga Fa'atonu

O lo'o fa'aalia i lalo le fa'asologa o le fa'aogaina o modules eseese i lenei mamanu.

Ata 2. Ata Fa'atonu

Fa'amatalaga:

M o le numera o tagata liliu.
S o le numera o s fa'aliliuinaamples i le tagata liliu i le faavaa.
WIDTH_MULP o le fa'ateleina o le lautele o fa'amatalaga i le va o le fa'aoga fa'aoga ma le felauaiga.
N o le numera o pa'u fa'aliliuga i le tagata liliu.
O le CS o le numera o pusi fa'atonutonu i le liua samples.

I lenei seti, mo example L = 8, M = 4, ma le F = 1, o le fuainumera o faʻamatalaga o laina transceiver e 24.75 Gbps.
Ole Si5332 OUT1 e fa'atupuina le 100 MHz uati ile mgmt_clk. Si5345-D-EVB e fa'atupuina laina e lua uati, 375 MHz ma le 100 MHz. O le 375 MHz o loʻo tuʻuina atu i le multiplexer faʻapipiʻi i le Intel Agilex I-Series F-tile Demo Board e ala i le J19 SMA port. O le uati o le fa'apipi'i fa'apipi'i e fa'asolo ai le F-tile transceiver reference clock (refclk_xcvr) ma le JESD204C Intel FPGA IP core PLL reference clock (refclk_core). 100 MHz mai le Si5345-D-EVB o loʻo fesoʻotaʻi atu i le HMC7044 programmable clock generator o loʻo iai i le AD9081 EVM e avea ma faʻaoga uati.
(EXT_HMCREF).

O le HCM7044 e maua ai se faailo SYSREF faavaitaimi o le 11.71875 MHz e ala i le FMC Connector.
O le JESD204C Intel FPGA IP o loʻo faʻapipiʻiina i le Duplex mode ae naʻo le auala e maua ai e faʻaaogaina.

Metotia Felagolagomai
O le vaega o loʻo mulimuli mai o loʻo faʻamatalaina ai sini o suʻega, faʻagasologa, ma le pasi. O le su'ega e aofia ai vaega nei:

Laega feso'ota'iga o fa'amaumauga
La'au felauaiga fa'ameamea

Layer Link Link Receiver
Ole vaega lea ole su'ega e aofia ai fa'ata'ita'iga mo le sync header alignment (SHA) ma le extended multiblock alignment (EMBA).
I luga ole fesoʻotaʻiga amata, pe a maeʻa le toe setiina o le tali, o le JESD204C Intel FPGA IP e amata ona suʻe mo le sync header stream lea e lafoina e le masini. O resitara nei mai fa'amaumauga feso'ota'iga o lo'o faitau i le taimi o le su'ega, tusia i totonu o le ogalaau files, ma fa'amaonia mo le pasia o ta'iala ile TCL scripts.

Fa'amatalaga Fa'atatau
F-tile JESD204C Intel FPGA IP Taiala mo Tagata

Fa'atonu Ulutala (SHA)
Fuafuaga 1. Tu'ufa'atasi Su'ega Fa'asologa o Ulutala

Su'ega Su'ega	Fa'amoemoe	Fa'amatalaga	Tulaga Fa'ailoga
SHA.1	Siaki pe fa'amauina le Loka Ulutala Sync pe a mae'a le fa'asologa o le toe setiina.	O fa'ailoga nei e faitau mai tusi resitala: CDR_Lock e faitau mai le rx_status3 (0x8C) resitala. SH_Locked e faitau mai le rx_status4 (0x90) resitala. jrx_sh_err_status e faitau mai le rx_err_status (0x60) resitala.	CDR_Lock ma SH_LOCK e tatau ona fa'amauina i le maualuga e fetaui ma le numera o laina. jrx_sh_err_status e tatau ona Ole fasi fanua ile jrx_sh_err_status siaki mo sh_unlock_err, rx_gb_overflow_err, rx_gb_underflow_err, invalid_sync_header, src_rx_alarm, syspll_lock_err, ma cdr_locked_err.
SHA.2	Siaki le Sync Header Lock tulaga pe a uma le sync header loka ua ausia (po'o le taimi o le Extended Multi-Block Alignment phase) ma mautu.	invalid_sync_header ua faitau mo le Sync Header loka loka mai le resitala (0x60[8]).	e tatau ona 0 le tulaga invalid_sync_header.

Fa'aopoopoina le Fa'atonuga Tele poloka (EMBA)

Fuafuaga 2. Su'ega Su'ega Fa'avasegaga Fa'atele Block

Su'ega Su'ega		Fa'amoemoe		Fa'amatalaga		Tulaga Fa'ailoga
EMBA.1		Siaki pe na'o le fa'aupuga o le Loka Fa'aulu Fa'aopoopo e fa'aopoopoina.		O fa'ailoga nei e faitau i tusi resitala:		Ole tau EMB_Locked_1 e tatau ona tutusa ma le 1 e fetaui ma laina ta'itasi. EMB_Lock_err e tatau ona 0.

	Su'ega Su'ega		Fa'amoemoe		Fa'amatalaga		Tulaga Fa'ailoga
					EMB_Locked_1 o lo'o faitau mai le rx_status5 (0x94) resitala. EMB_Lock_err e faitau mai le rx_err_status (0x60[19]) resitala.
	EMBA.2		Siaki pe o mautu le tulaga o le Loka Fa'atele (pe a uma le loka fa'atele po'o se'i tu'u le pa'u elasiti) fa'atasi ai ma le leai o ni poloka fa'aletonu e le aoga.		invalid_eomb_eoemb e faitau mai le rx_err_status (0x60[10:9]) resitala.		invalid_eomb_eoemb e tatau ona “00”.
	EMBA.3		Siaki le laina laina.		O tau nei e faitau mai tusi resitala: elastic_buf_over_flow e faitau mai le rx_err_status (0x60[20]) resitala. elastic_buf_full e faitau mai le tusi resitala rx_status6 (0x98).		elastic_buf_over_flow e tatau ona 0. Ole tau elastic_buf_full e tatau ona tutusa ma le 1 e fetaui ma laina taʻitasi.

Lava Fe'avea'i Receiver (TL)
Ina ia siaki le faʻamaoni o faʻamaumauga o le faʻasologa o faʻamaumauga o totogi e ala i le tagata e taliaina (RX) JESD204C Intel FPGA IP ma le felauaiga o felauaiga, ua faʻatulagaina le ADC i ramp/PRBS mamanu su'ega. O loʻo faʻatulagaina foi le ADC e faʻaogaina i le faatulagaga tutusa e pei ona faʻatulagaina i le JESD204C Intel FPGA IP. O le ramp/ PRBS siaki i le ie FPGA siaki le ramp/PRBS fa'amaoni fa'amaumauga mo le minute e tasi. O le RX JESD204C Intel FPGA IP resitara rx_err o lo'o su'esu'eina faifaipea mo le tau leai mo le minute e tasi.
O le ata o lo'o i lalo o lo'o fa'aalia ai le fa'atonuga o su'ega mo le siakiina o fa'amaumauga.

Ata 3. Su'esu'ega Fa'amaoni Fa'aaogāina o le Ramp/PRBS15 Siaki

Laulau 3. Tulaga Fa'ata'ita'i Fa'alava'au

Su'ega Su'ega

Fa'amoemoe

Fa'amatalaga

Tulaga Fa'ailoga

TL.1

Siaki le faafanua o le felauaiga o le alalaupapa o faamatalaga e faaaoga ai le ramp mamanu su'ega.

Data_mode ua seti ile Ramp_faiga.

O fa'ailoga nei e faitau i tusi resitala:

crc_err e faitau mai le rx_err_status (0x60[14]).
jrx_patchk_data_error e faitau mai le tusi resitala tst_err0.

crc_err e tatau ona maualalo e pasi.
jrx_patchk_data_error e tatau ona maualalo.

TL.2

Siaki le fa'afanua o le felauaiga o le alalaupapa fa'amatalaga e fa'aaoga ai le PRBS15 su'ega mamanu.

Data_mode ua seti ile pbs_mode.

O tau nei e faitau mai tusi resitala:

crc_err e faitau mai le rx_err_status (0x60[14]).
jrx_patchk_data_error e faitau mai le tusi resitala tst_err0.

crc_err e tatau ona maualalo e pasi.
jrx_patchk_data_error e tatau ona maualalo.

JESD204C Intel FPGA IP ma ADC Configurations
O le JESD204C Intel FPGA IP tapulaʻa (L, M, ma F) i totonu o lenei masini siaki siaki e lagolagoina e le masini AD9081. O le fua faatatau o faamatalaga transceiver, sampuati ling, ma isi JESD204C tapula'a ia tausisia tulaga fa'aoga AD908D1.
Ole su'ega ole su'ega meafaigaluega e fa'atino ai le JESD204C Intel FPGA IP fa'atasi ai ma le fa'asologa o fa'asologa o lo'o i lalo.

Fa'atonuga fa'avaomalo mo fa'atulagaga uma:

E = 1

CF = 0
CS = 0
Vasega laiti = 1

FCLK_MULP = 1
WIDTH_MULP = 8
SH_CONFIG = CRC-12

FPGA Pulega Uati (MHz) = 100

I'uga o Su'ega
O le laulau o lo'o i lalo o lo'o i ai fa'ai'uga e mafai ma o latou fa'amatalaga.

Laulau 4. Fa'amatalaga Fa'ai'uga

I'uga	Uiga
PASI	O le Device Under Test (DUT) na mata'ituina e fa'aalia le amio fa'atatau.
PASS ma fa'amatalaga	O le DUT na mata'ituina e fa'aalia le amio fa'atatau. Ae ui i lea, o se faʻamatalaga faaopoopo o le tulaga o loʻo aofia ai (example: ona o taimi faatapulaa, na o se vaega o le suʻega na faia).

I'uga	Uiga
FAI	O le DUT na mata'ituina e fa'aalia amioga e le o fa'atatau.
Lapataiga	O le DUT na matauina e faʻaalia amioga e le fautuaina.
Va'ai i fa'amatalaga	Mai fa'amatalaga, e le'i mafai ona fa'amauina se pasi aoga po'o se pa'u. O loʻo iai se faʻamatalaga faaopoopo o le tulaga.

O le siata o loʻo i lalo o loʻo faʻaalia ai faʻaiʻuga mo suʻega SHA.1, SHA.2, EMBA.1, EMBA.2, EMBA.3, TL.1, ma TL.2 faʻatasi ai ma tau faʻatatau o le L, M, F, faʻamaumauga, sampuati ling, uati so'o, ma alaleo SYSREF.

Laulau 5. I'uga mo Su'ega Su'ega SHA.1, SHA.2, EMBA.1, EMBA.2, EMBA.3, TL.1, ma TL.2

Leai.	L	M	F	S	HD	E	N	NP	ADC SampUati ling (MHz)	FPGA Device Clock (MHz)	FPGA Uati Fa'avaa (MHz)	FPGA So'oga Uati (MHz)	Auala fua (Gbps)	I'uga
1	8	4	1	1	0	1	16	16	3000.00	375.00	375.00	375.00	24.75	Pasa

Fa'amatalaga I'uga o Su'ega
I fa'ata'ita'iga ta'itasi, o le RX JESD204C Intel FPGA IP e fa'atūina manuia le fa'aogaina o le fa'auluuluga, fa'alautele le fa'aogaina o multiblock, ma se'ia o'o i le vaega o fa'amaumauga a tagata.
E leai se fa'afitauli fa'amaumauga o lo'o matauina e le Ramp ma le PRBS siaki mo fa'atonuga a le JESD e aofia uma ai auala fa'aletino, e leai fo'i se siaki fa'aletonu o le ta'amilosaga (CRC) ma le fa'atonuga o le fa'atonuga o lo'o matauina.
I le taimi o ta'amilosaga o le eletise, e ono aliali mai se mea sese o le kesi o le laina fa'atasi ma fa'asologa o parakalafa. Ina ia aloese mai lenei mea sese, o le LEMC offset values e tatau ona faʻapolokalame pe mafai ona e faʻaogaina lenei mea i le faʻasologa o le saluina. Mo nisi fa'amatalaga i tulaga fa'aletulafono o le LEMC offset, fa'asino ile RBD Tuning Mechanism ile F-tile JESD204C IP User Guide.

Fa'amatalaga Fa'atatau
RBD Fa'atonu Mechanism

Aotelega
O lenei lipoti o loʻo faʻaalia ai le faʻamaoniaina o le JESD204C Intel FPGA IP ma le PHY eletise eletise ma le AD9081/9082 (R2 Silicon) masini e oʻo atu i le 24.75 Gbps mo ADC. O le faʻatulagaina atoatoa ma le faʻatulagaina o meafaigaluega o loʻo faʻaalia e tuʻuina atu ai le mautinoa i le felagolagomaʻi ma le faʻatinoga o masini e lua.

Tala'aga Toe Iloiloga o Pepa mo AN 927: JESD204C Intel FPGA IP ma le ADI AD9081 MxFE* ADC Interoperability Lipoti mo Intel Agilex F-Tile Devices

Fa'amatalaga Fa'amaumauga	Suiga
2022.04.25	Fa'asalalauga muamua.

AN 876: JESD204C Intel® FPGA IP ma le ADI AD9081 MxFE* ADC Interoperability Lipoti mo Intel® Agilex® F-Tile Devices

Pepa / Punaoa

intel JESD204C Intel FPGA IP ma ADI AD9081 MxFE ADC Interoperability Lipoti [pdf] Taiala mo Tagata Fa'aoga
JESD204C Intel FPGA IP ma le ADI AD9081 MxFE ADC Interoperability Lipoti, JESD204C, Intel FPGA IP ma le ADI AD9081 MxFE ADC Interoperability Lipoti

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