JESD204C Intel FPGA IP kunye ne-ADI AD9081 MxFE iNgxelo yokusebenzisana kwe-ADC
Ulwazi lweMveliso
Imveliso ekubhekiswa kuyo kwincwadi yomsebenzisi yiJESD204C Intel FPGA IP. Iyingxenye ye-hardware esetyenziswa ngokubambisana ne-Intel Agilex I-Series F-Tile Demo Board kunye ne-ADI AD9081-FMCA-EBZ EVM. I-IP imiselwe kwimowudi yeDuplex kodwa yindlela yomamkeli kuphela esetyenziswayo. Ivelisa iwotshi yekhonkco ye-375 MHz kunye ne-375 MHz isakhelo sewotshi. Ukuseta i-hardware yovavanyo lokusebenzisana kwe-ADC iboniswe kuMfanekiso 1. I-IP ifuna ukuba i-SYSREF ibonelelwe yijenereyitha yewotshi evelisa iwotshi yesixhobo se-JESD204C Intel FPGA IP.
Imiyalelo yokusetyenziswa kwemveliso
Ukuseta i-Hardware
Ukuseta ihardware yokusebenzisa iJESD204C Intel FPGA IP, landela la manyathelo:
- Qhagamshela i-ADI AD9081-FMCA-EBZ EVM kwi-FMC + ikhonkco ye-Intel Agilex I-Series F-Tile Demo Board.
- Qinisekisa ukuba isignali ye-SYSREF ibonelelwa yiwotshi yejenereyitha evelisa i-JESD204C Intel FPGA IP isixhobo iwotshi.
Inkcazo yeNkqubo
Umzobo wenqanaba lenkqubo ubonisa indlela iimodyuli ezahlukeneyo ezidityaniswe ngayo kolu yilo. Iquka iBhodi yeDemo ye-Intel Agilex-I-F-tile, i-Intel Agilex F-tile Device, i-Top-Level RTL, iNkqubo yoMyili wePlatform, i-Pattern Generator, i-Pattern Checker, i-F-Tile JESD204C Duplex IP Core, kunye neewashi ezahlukeneyo kunye ne-interfaces.
Indlela yokuSebenza
Umamkeli weDatha yeLink
Lo mmandla wovavanyo ugubungela iimeko zovavanyo zolungelelwaniso lweheader sync (SHA) kunye nolungelelwaniso olwandisiweyo lweebhloko ezininzi (EMBA). I-JESD204C Intel FPGA IP ifunda iirejista ukusuka kwikhonkco yedatha ngexesha lovavanyo, ibhale kwilog files, kwaye uyaziqinisekisa ukulungiselela ukuphumelela iikhrayitheriya kwiincwadi zeempendulo ze-TCL.
I-JESD204C Intel® FPGA IP kunye ne-ADI AD9081 MxFE* Ingxelo ye-ADC yokusebenzisana kwi-Intel® Agilex™ F-tile Devices
I-JESD204C Intel® FPGA IP yi-high-speed point-to-point serial interface yepropathi yengqondo (IP).
I-JESD204C Intel FPGA IP iye yavavanywa ngezixhobo ezininzi ezikhethiweyo zeJESD204C ezihambelanayo ne-analog-to-digital converter (ADC).
Le ngxelo igxininisa ukusebenzisana kwe-JESD204C Intel FPGA IP kunye ne-AD9081 Mixed Signal Front End (MxFE *) imodyuli yokuvavanya (EVM) esuka kwi-Analog Devices Inc. (ADI). La macandelo alandelayo achaza indlela yokuphuma kwehardware kunye neziphumo zovavanyo.
Ulwazi olunxulumeneyo
F-tile JESD204C Intel FPGA IP User Guide
IiMfuno zeHardware kunye neSoftware
Uvavanyo lokusebenzisana lufuna ezi zixhobo zilandelayo zehardware kunye nesoftware: Hardware
- Intel Agilex™ I-Series F-tile Demo Board (AGIB027R29A1E2VR0) ene-12V iadaptha yamandla
- Izixhobo ze-Analog (ADI) AD9081 MxFE* EVM (AD9081-FMCA-EBZ, Rev C)
- Ibhodi yoVavanyo ye-Skywork Si5345-D (Si5345-D-EVB)
- I-SMA eyindoda ukuya kwi-SMP eyindoda
- I-SMP indoda ukuya kwintambo ye-SMP
Isoftware
- Intel Quartus® Prime Pro Edition software version 21.4
- AD9081_API uguqulelo 1.1.0 okanye entsha (usetyenziso lweLinux, olufunekayo kuqwalaselo lwe-AD9081 EVM)
Ulwazi olunxulumeneyo
- AD9081/AD9082 Isikhokelo soPhuhliso lweSixokelelwano soMsebenzisi
- ISikhokelo soMsebenzisi weBhodi yoVavanyo lweSkyworks Si5345-D
Ukuseta i-Hardware
I-JESD204C Intel FPGA IP ifakwe kwimodi ye-Duplex kodwa kuphela indlela yokufumana isetyenziswa. I-FCLK_MULP =1, WIDTH_MULP = 8, S = 1, i-PLL engundoqo ivelisa i-clock ye-375 MHz kunye ne-375 MHz isakhelo.
Ibhodi yeDemo ye-Intel Agilex I-Series F-Tile isetyenziswe kunye ne-ADI AD9081-FMCA-EBZ EVM exhunywe kwi-FMC + ikhonkco yebhodi yophuhliso. Ukuseta i-hardware yovavanyo lokusebenzisana kwe-ADC kuboniswe kwi-Hardware Setup figure.- • I-AD9081-FMCA-EBZ EVM ifumana amandla kwi-Intel Agilex I-Series F-Tile Demo Board ngokusebenzisa i-FMC + isixhumi.
- I-transceiver ye-F-tile kunye ne-JESD204C Intel FPGA IP iiwotshi ze-PLL ezisisiseko ze-PLL zinikezelwa yi-Si5345-D-EVB nge-SMA ukuya kwintambo ye-SMP. Misela i-MUX_DIP_SW0 ukuya phezulu kwiBhodi yeDemo ye-Agilex-I F-Tile ukuqinisekisa ukuba i-U22 ithatha i-CLKIN1 eqhagamshelwe kwikhebula le-SMP.
- I-Si5345-D-EVB ibonelela ngewotshi yereferensi kwi-HMC7044 ijenereyitha yewotshi ecwangcisiweyo ekhoyo kwi-AD9081 EVM nge-SMP ukuya kwintambo ye-SMP.
- Iwashi yokulawula ye-JESD204C Intel FPGA IP core inikezelwa yi-Silicon Labs Si5332 i-clock generator generator ekhoyo kwi-Intel Agilex I-Series F-tile Demo Board.
- I-HMC7044 yewotshi ecwangcisiweyo yejenereyitha ibonelela ngewotshi yereferensi yesixhobo se-AD9081. I-loop evaliweyo yesigaba (PLL) ekhoyo kwisixhobo se-AD9081 ivelisa i-ADC efunwayo.ampIkloko ye-ling kwiwotshi yereferensi yesixhobo.
- Kwi-Subclass 1, i-HMC7044 clock generator yenza isignali ye-SYSREF yesixhobo se-AD9081 kunye ne-JESD204C Intel FPGA IP ngokusebenzisa i-FMC + ikhonkco.
Hayite: I-Intel icebisa i-SYSREF ukuba ibonelelwe yiwotshi yejenereyitha eyenza i-JESD204C Intel FPGA IP isixhobo iwotshi.
Inkcazo yeNkqubo
Umzobo olandelayo wenqanaba lenkqubo ubonisa indlela iimodyuli ezahlukeneyo ezidityaniswe ngayo kolu yilo.
Umzobo 2. Umzobo weNkqubo 
Amanqaku:
- M linani labaguquli.
- S linani lee-s ezigqithisiweyoampumguquli ngokwesakhelo ngasinye.
- I-WIDTH_MULP yi-multiplier yedatha yobubanzi phakathi komgangatho wesicelo kunye nomaleko wothutho.
- I-N linani lamasuntswana oguqulelo ngoguqulelo ngalunye.
- I-CS linani lamasuntswana olawulo kwinguquko nganye samples.
Kolu cwangciso, umzekeloample L = 8, M = 4, kunye ne-F = 1, izinga ledatha yeendlela ze-transceiver yi-24.75 Gbps.
I-Si5332 OUT1 yenza i-100 MHz iwotshi ukuya kwi-mgmt_clk. I-Si5345-D-EVB ivelisa iifrikhwensi zewotshi ezimbini, i-375 MHz kunye ne-100 MHz. I-375 MHz inikezelwa kwi-multiplexer efakwe kwi-Intel Agilex I-Series F-tile Demo Board ngokusebenzisa i-J19 SMA port. Ikloko yemveliso ye-multiplexer edibeneyo iqhuba iwotshi yereferensi ye-F-tile ye-transceiver (refclk_xcvr) kunye ne-JESD204C Intel FPGA IP core PLL iwotshi yereferensi (refclk_core). I-100 MHz ukusuka kwi-Si5345-D-EVB iqhagamshelwe kwi-HMC7044 ijenereyitha yewotshi ecwangcisiweyo ekhoyo kwi-AD9081 EVM njengegalelo lewotshi.
(EXT_HMCREF).
I-HCM7044 ivelisa uphawu lwe-SYSREF lwexesha le-11.71875 MHz nge-FMC Connector.
I-JESD204C Intel FPGA IP ifakwe kwimodi ye-Duplex kodwa kuphela indlela yokufumana isetyenziswa.
Indlela yokuSebenza
Eli candelo lilandelayo lichaza iinjongo zovavanyo, inkqubo, kunye neendlela zokupasa. Uvavanyo lubandakanya ezi ndawo zilandelayo:
- Umamkeli wekhonkco ledatha
- Umamkeli wezothutho umaleko
Umamkeli weDatha yeLink
Lo mmandla wovavanyo ugubungela iimeko zovavanyo zolungelelwaniso lweheader sync (SHA) kunye nolungelelwaniso olwandisiweyo lweebhloko ezininzi (EMBA).
Kwikhonkco uqalise, emva kokusetha kwakhona umamkeli, iJESD204C Intel FPGA IP iqala ukukhangela umjelo wentloko wongqamaniso ogqithiswa sisixhobo. Ezi rejista zilandelayo ezivela kwi-data link layer zifundwa ngexesha lovavanyo, zibhalwe kwilog files, yaza yangqinisiswa ukuphumelela iikhrayitheriya kwiincwadi zeempendulo ze-TCL.
Ulwazi olunxulumeneyo
F-tile JESD204C Intel FPGA IP User Guide
NONE
Itheyibhile 1. Sync Iimeko zoVavanyo lokuLungelelaniswa kweNtloko
| Ityala lovavanyo | Injongo | Inkcazo | Ukupasa |
| SHA.1 | Jonga ukuba i-Sync Header Lock iyabangwa emva kokugqitywa kokusetwa ngokutsha. | Le miqondiso ilandelayo ifundwa kwiirejista:
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| SHA.2 | Jonga ubume beNqanaba yokuTshixa iNtloko emva kokuba ungqamaniso lokutshixa kweheader luphunyeziwe (okanye ngexesha loLungelelwaniso lweMulti-Block) kwaye uzinzile. | invalid_sync_header ifundelwe imo yokutshixa i-Sync Header kwirejista (0x60[8]). | invalid_sync_header imeko kufuneka ibe ngu-0. |
Ulungelelwaniso olwandisiweyo lweMultiblock (EMBA)
Itheyibhile 2. Iimeko zoVavanyo lwe-Multiblock Ulungelelwaniso olwandisiweyo
| Ityala lovavanyo | Injongo | Inkcazo | Ukupasa | |||||
| EMBA.1 | Jonga ukuba iSitshixo se-Multiblock Eyongeziweyo sibanjiswe kuphela emva kwe-Sync Header Lock. | Le miqondiso ilandelayo ifundwa kwiirejista: |
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| Ityala lovavanyo | Injongo | Inkcazo | Ukupasa | |||||
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| EMBA.2 | Jonga ukuba imo eyoNgezelelweyo ye-Multiblock Tshixo izinzile (emva kokutshixa okwandisiweyo kweebhloko ezininzi okanye de kukhululwe isithinteli esilastiki) kunye nokungabikho kwe-multiblocker engasebenzanga. | invalid_eomb_eoemb ifundwe kwirejista ye-rx_err_status (0x60[10:9]). | invalid_eomb_eoemb kufuneka ibengu "00". | |||||
| EMBA.3 | Jonga ulungelelwaniso lwendlela. | La maxabiso alandelayo afundwa kwiirejista:
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Umamkeli wezoThutho (TL)
Ukujonga ingqibelelo yedatha yedatha yomthwalo wokuhlawula ngokufumana (RX) JESD204C Intel FPGA IP kunye nomaleko wezothutho, i-ADC iqwalaselwe ukuba r.amp/Ipateni yovavanyo lwePRBS. I-ADC iphinde isetelwe ukuba isebenze kunye noqwalaselo olufanayo njengoko lubekwe kwiJESD204C Intel FPGA IP. I-ramp/ Umhloli wePRBS kwilaphu leFPGA lijonga i-ramp/ PRBS ingqibelelo yedatha yomzuzu omnye. I-RX JESD204C Intel FPGA IP irejista rx_err iphendulwa ngokuqhubekayo ngexabiso elingu-zero ngomzuzu omnye.
Lo mzobo ungezantsi ubonisa ukuseta ingqikelelo yovavanyo lokukhangela imfezeko yedatha.
Umzobo 3. UHlolo lweMfezeko yeDatha usebenzisa i-Ramp/PRBS15 Umhloli
Itheyibhile 3. Iimeko zoVavanyo lweNqanaba lezoThutho
| Ityala lovavanyo | Injongo | Inkcazo | Ukupasa |
| TL.1 | Khangela umaleko wothutho wemephu yeshaneli yedatha usebenzisa i-ramp ipateni yovavanyo. | Imowudi_yedatha imiselwe ku-Ramp_imowudi.
Le miqondiso ilandelayo ifundwa kwiirejista:
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| TL.2 | Jonga imephu yomgangatho wezothutho weshaneli yedatha usebenzisa i-PRBS15 iphethini yovavanyo. | Imowudi_yedatha imiselwe kwimowudi ye-prbs.
La maxabiso alandelayo afundwa kwiirejista:
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JESD204C Intel FPGA IP kunye noqwalaselo lwe-ADC
I-JESD204C Intel FPGA IP parameters (L, M, kunye F) kolu kukhutshwa kwee-hardware zixhaswa ngokwemveli sisixhobo se-AD9081. Ireyithi yedatha ye-transceiver, samplingkwotshi, kunye nezinye iiparamitha zeJESD204C zithobela iimeko zokusebenza ze-AD908D1.
Uvavanyo lokuphuma kwehardware lisebenzisa iJESD204C Intel FPGA IP ngolu qwalaselo lweparamitha lulandelayo.
Ulungiselelo lwehlabathi kulo lonke ulungelelwaniso:
- E = 1
- CF = 0
- CS = 0
- Udidi oluphantsi = 1
- FCLK_MULP = 1
- WIDTH_MULP = 8
- SH_CONFIG = CRC-12
- Ikloko yoLawulo yeFPGA (MHz) = 100
Iziphumo zovavanyo
Le theyibhile ilandelayo iqulethe iziphumo ezinokwenzeka kunye nenkcazo yazo.
ITheyibhile 4. Inkcazo yeZiphumo
| Isiphumo | Ingcaciso |
| PASS | Isixhobo esiphantsi kovavanyo (DUT) sajongwa ukubonisa ukuziphatha okuhambelanayo. |
| PASS ngezimvo | I-DUT iye yaqatshelwa ukubonisa indlela yokuziphatha ehambelanayo. Nangona kunjalo, ingcaciso eyongezelelweyo yale meko ibandakanyiwe (umzample: ngenxa yokulinganiselwa kwexesha, kuphela inxalenye yovavanyo eyenziwa). |
| Isiphumo | Ingcaciso |
| FAIL | I-DUT iye yaqatshelwa ukubonisa indlela yokuziphatha engahambelaniyo. |
| Isilumkiso | I-DUT iye yaqatshelwa ukubonisa indlela yokuziphatha engakhuthazwayo. |
| Jonga kwizimvo | Kokuqatshelweyo, ukupasa okusebenzayo okanye ukungaphumeleli akukwazanga ukumiselwa. Ingcaciso eyongezelelweyo yale meko ifakiwe. |
Le theyibhile ilandelayo ibonisa iziphumo zeemeko zovavanyo SHA.1, SHA.2, EMBA.1, EMBA.2, EMBA.3, TL.1, kunye ne-TL.2 kunye namaxabiso ahlukeneyo e-L, M, F, izinga ledatha, sampIkloko yeling, ikloko yekhonkco, kunye ne-SYSREF frequencies.
Itheyibhile 5. Iziphumo zaMatyala oVavanyo SHA.1, SHA.2, EMBA.1, EMBA.2, EMBA.3, TL.1, kunye neTL.2
| Hayi. | L | M | F | S | HD | E | N | NP | ADC
SampIkloko yokulala (MHz) |
Ikloko yesiXhobo seFPGA (MHz) | FPGA
Iwotshi yesakhelo (MHz) |
FPGA
Ikloko yonxulumaniso (MHz) |
Umlinganiselo weNdlela (Gbps) | Isiphumo |
| 1 | 8 | 4 | 1 | 1 | 0 | 1 | 16 | 16 | 3000.00 | 375.00 | 375.00 | 375.00 | 24.75 | Dlula |
Izimvo zeziphumo zovavanyo
Kwimeko nganye yovavanyo, i-RX JESD204C Intel FPGA IP iseka ngempumelelo ulungelelwaniso lwentloko ehambelanayo, ulungelelwaniso olwandisiweyo lwe-multiblock, kwaye kude kube nesigaba sedatha yomsebenzisi.
Akukho mcimbi wengqibelelo wedatha ujongwa nguRamp kunye ne-PRBS umkhangeli wolungelelwaniso lweJESD olugubungela zonke iindledlana zomzimba, kwakhona akukho jikijolo lokuphindaphinda kwakhona (CRC) kunye nempazamo yokulinganisa yomyalelo iyabonwa.
Ngexesha elithile lemijikelo yamandla, impazamo yedesika yendlela inokuvela kunye nolungelelwaniso lweparameter. Ukunqanda le mpazamo, i-LEMC yokulinganisa ixabiso kufuneka icwangciswe okanye unokwenza oku ngokuzenzakalelayo ngenkqubo yokutshayela ukulinganisa. Ukufumana ulwazi oluthe kratya malunga nemilinganiselo yezomthetho ye-LEMC offset, bhekisa kwi-RBD Tuning Mechanism kwi-F-tile JESD204C IP User Guide.
Ulwazi olunxulumeneyo
I-RBD Tuning Mechanism
Isishwankathelo
Le ngxelo ibonisa ukuqinisekiswa kwe-JESD204C Intel FPGA IP kunye ne-PHY i-interface yombane kunye ne-AD9081 / 9082 (R2 Silicon) isixhobo ukuya kwi-24.75 Gbps ye-ADC. Ukucwangciswa okupheleleyo kunye nokusekwa kwe-hardware kuboniswa ukunika ukuzithemba ekusebenzisaneni kunye nokusebenza kwezi zixhobo zombini.
Imbali yoHlaziyo loXwebhu lwe-AN 927: JESD204C Intel FPGA IP kunye ne-ADI AD9081 MxFE * Ingxelo ye-ADC yokusebenzisana kwi-Intel Agilex F-Tile Devices
| Inguqulelo yoXwebhu | Iinguqu |
| 2022.04.25 | Ukukhutshwa kokuqala. |
I-AN 876: JESD204C Intel® FPGA IP kunye ne-ADI AD9081 MxFE* Ingxelo ye-ADC yokusebenzisana kwi-Intel® Agilex® F-Tile Devices
Amaxwebhu / Izibonelelo
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intel JESD204C Intel FPGA IP kunye ne-ADI AD9081 MxFE iNgxelo yokusebenzisana kwe-ADC [pdf] Isikhokelo somsebenzisi I-JESD204C Intel FPGA IP kunye ne-ADI AD9081 MxFE iNgxelo yokusebenzisana kwe-ADC, iJESD204C, i-Intel FPGA IP kunye ne-ADI AD9081 MxFE iNgxelo yokusebenzisana kwe-ADC |