Abubuwan da ke ciki boye
1 JESD204C Intel FPGA IP da ADI AD9081 MxFE ADC Rahoton Haɗin kai
2 Bayanin samfur
3 Umarnin Amfani da samfur
4 JESD204C Intel® FPGA IP da ADI AD9081 MxFE* ADC Interoperability Report for Intel® Agilex™ F-tile Devices
4.1 Bayanin Tsarin
5 Takardu / Albarkatu
5.1 Magana

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JESD204C Intel FPGA IP da ADI AD9081 MxFE ADC Rahoton Haɗin kai

JESD204C-Intel-FPGA-IP-da-ADI-AD9081-MxF- ADC-Interoperability-Rahoton-KYAUTA-HOTUNA

Bayanin samfur

Samfurin da ake magana a kai a cikin littafin mai amfani shine JESD204C Intel FPGA IP. Kayan kayan masarufi ne wanda ake amfani dashi tare da Intel Agilex I-Series F-Tile Demo Board da ADI AD9081-FMCA-EBZ EVM. IP ɗin yana nan take a yanayin Duplex amma hanyar mai karɓa kawai ake amfani da shi. Yana samar da agogon haɗin kai 375 MHz da agogon firam na 375 MHz. Saitin kayan aikin don gwajin haɗin gwiwar ADC yana nunawa a cikin Hoto 1. IP yana buƙatar SYSREF ta samar da janareta na agogo wanda ke samar da agogon na'urar JESD204C Intel FPGA IP.

Umarnin Amfani da samfur

Saitin Hardware
Don saita kayan aikin don amfani da JESD204C Intel FPGA IP, bi waɗannan matakan:

  1. Haɗa ADI AD9081-FMCA-EBZ EVM zuwa mai haɗin FMC+ na Intel Agilex I-Series F-Tile Demo Board.
  2. Tabbatar cewa siginar SYSREF ta samar da janareta na agogo wanda ke samar da agogon na'urar JESD204C Intel FPGA IP.

Bayanin Tsarin
Zane-zane na matakin-tsari yana nuna yadda ake haɗa nau'o'i daban-daban a cikin wannan ƙira. Ya haɗa da Intel Agilex-I F-tile Demo Board, Intel Agilex F-tile Device, Top-Level RTL, Platform Designer System, Pattern Generator, Pattern Checker, F-Tile JESD204C Duplex IP Core, da agogo da musaya daban-daban.

Hanyar Sadarwa
Layer Data Link Layer
Wannan yanki na gwajin ya ƙunshi shari'o'in gwaji don daidaitawa na kai (SHA) da kuma tsawaita daidaitawa da yawa (EMBA). JESD204C Intel FPGA IP yana karanta rajista daga layin haɗin bayanan yayin gwajin, yana rubuta su cikin log. files, da kuma tabbatar da su don wuce ma'auni ta hanyar rubutun TCL.

JESD204C Intel® FPGA IP da ADI AD9081 MxFE* ADC Interoperability Report for Intel® Agilex™ F-tile Devices

JESD204C Intel® FPGA IP sigar fasaha ce mai sauri-zuwa-maki (IP).
An gwada JESD204C Intel FPGA IP na kayan aiki tare da na'urorin da aka zaɓa na JESD204C masu dacewa da analog-zuwa-dijital (ADC).
Wannan rahoto yana nuna haɗin gwiwar JESD204C Intel FPGA IP tare da AD9081 Mixed Signal Front End (MxFE *) kimantawa module (EVM) daga Analog Devices Inc. (ADI). Sassan da ke gaba suna bayyana hanyoyin duba kayan aikin da sakamakon gwaji.

Bayanai masu alaƙa
F-tile JESD204C Intel FPGA IP Jagorar mai amfani

Bukatun Hardware da Software
Gwajin hulɗar aiki yana buƙatar kayan aikin hardware da software masu zuwa: Hardware

  • Intel Agilex™ I-Series F-tile Demo Board (AGIB027R29A1E2VR0) tare da adaftar wutar lantarki 12V
  • Na'urorin Analog (ADI) AD9081 MxFE* EVM (AD9081-FMCA-EBZ, Rev C)
  • Skywork Si5345-D Board Evaluation (Si5345-D-EVB)
  • SMA namiji zuwa SMP namiji
  • SMP namiji zuwa kebul na SMP

Software

  • Intel Quartus Prime Pro Edition software 21.4
  • AD9081_API sigar 1.1.0 ko sabo (Aikace-aikacen Linux, ana buƙata don daidaitawar AD9081 EVM)

Bayanai masu alaƙa

  • AD9081/AD9082 Jagorar Mai Amfani da Ci gaban Tsarin
  • Jagoran Mai Amfani Skyworks Si5345-D

Saitin Hardware
JESD204C Intel FPGA IP yana nan take a yanayin Duplex amma hanyar mai karɓa kawai ake amfani dashi. Don FCLK_MULP = 1, WIDTH_MULP = 8, S = 1, ainihin PLL yana haifar da agogon haɗin 375 MHz da agogon firam 375 MHz.
Ana amfani da Intel Agilex I-Series F-Tile Demo Board tare da ADI AD9081-FMCA-EBZ EVM da aka haɗa da mai haɗin FMC + na hukumar haɓaka. Saitin kayan aikin don gwajin haɗin gwiwar ADC yana nunawa a cikin adadi na Saitin Hardware - • AD9081-FMCA-EBZ EVM yana samun iko daga Intel Agilex I-Series F-Tile Demo Board ta hanyar haɗin FMC+.

  • F-tile transceiver da JESD204C Intel FPGA IP core clocks reference clocks ana kawo su ta Si5345-D-EVB ta hanyar SMA zuwa kebul na SMP. Saita MUX_DIP_SW0 zuwa sama akan Agilex-I F-Tile Demo Board don tabbatar da U22 yana ɗaukar CLKIN1 wanda aka haɗa da kebul na SMP.
  • Si5345-D-EVB yana ba da agogon tunani zuwa janareta na agogon HMC7044 wanda ke cikin AD9081 EVM ta hanyar SMP zuwa kebul na SMP.
  • Agogon gudanarwa don JESD204C Intel FPGA IP core ana ba da shi ta Silicon Labs Si5332 janareta na agogon shirye-shirye wanda ke cikin Intel Agilex I-Series F-tile Demo Board.
  • HMC7044 mai samar da agogon shirye-shirye yana ba da agogon nuni na na'urar AD9081. Madaidaicin kulle-kulle (PLL) da ke cikin na'urar AD9081 yana haifar da ADC s da ake so.ampagogon ling daga agogon nuni na na'urar.
  • Don Subclass 1, janareta na agogon HMC7044 yana haifar da siginar SYSREF don na'urar AD9081 kuma don JESD204C Intel FPGA IP ta hanyar haɗin FMC+.

A'ate: Intel yana ba da shawarar SYSREF don samar da injin janareta na agogo wanda ke samar da agogon na'urar JESD204C Intel FPGA IP.

JESD204C-Intel-FPGA-IP-da-ADI-AD9081-MxF- ADC-Interoperability-Rahoton-01

Bayanin Tsarin

Hoton matakin-tsari mai zuwa yana nuna yadda ake haɗa nau'o'i daban-daban a cikin wannan ƙira.

Hoto na 2. Tsarin Tsarin JESD204C-Intel-FPGA-IP-da-ADI-AD9081-MxF- ADC-Interoperability-Rahoton-02

Bayanan kula:

  1. M shine adadin masu juyawa.
  2. S shine adadin sampLes per Converter kowane firam.
  3. WIDTH_MULP shine ninka nisan bayanai tsakanin layin aikace-aikacen da layin sufuri.
  4. N shine adadin juzu'in jujjuya kowane mai juyawa.
  5. CS shine adadin sarrafa ragowa kowane juyi samples.

A cikin wannan saitin, don example L = 8, M = 4, da F = 1, ƙimar bayanai na hanyoyin wucewa shine 24.75 Gbps.
Si5332 OUT1 yana haifar da agogon 100 MHz zuwa mgmt_clk. Si5345-D-EVB yana haifar da mitocin agogo biyu, 375 MHz da 100 MHz. Ana ba da 375 MHz zuwa mai haɗawa da yawa a cikin Intel Agilex I-Series F-tile Demo Board ta tashar tashar J19 SMA. Agogon fitarwa na Multixer da aka saka yana fitar da agogon F-tile transceiver (refclk_xcvr) da JESD204C Intel FPGA IP core PLL reference agogon (refclk_core). 100 MHz daga Si5345-D-EVB an haɗa shi zuwa HMC7044 janareta na agogo wanda ke cikin AD9081 EVM azaman shigar da agogo.
(EXT_HMCREF).

HCM7044 yana haifar da siginar SYSREF na lokaci-lokaci na 11.71875 MHz ta hanyar Mai Haɗin FMC.
JESD204C Intel FPGA IP yana nan take a yanayin Duplex amma hanyar mai karɓa kawai ake amfani dashi.

Hanyar Sadarwa
Sashe na gaba yana bayyana makasudin gwajin, tsari, da ka'idojin wucewa. Gwajin ya kunshi bangarori masu zuwa:

  • Layer mahada bayanan mai karɓa
  • Layer sufurin mai karɓa

Layer Data Link Layer
Wannan yanki na gwajin ya ƙunshi shari'o'in gwaji don daidaitawa na kai (SHA) da kuma tsawaita daidaitawa da yawa (EMBA).
A kan fara haɗin haɗin gwiwa, bayan sake saitin mai karɓa, JESD204C Intel FPGA IP yana fara neman rafi mai daidaitawa wanda na'urar ke watsawa. Ana karanta rajistan masu zuwa daga Layer link Layer yayin gwajin, an rubuta su cikin log files, kuma an tabbatar da ma'aunin wucewa ta hanyar rubutun TCL.

Bayanai masu alaƙa
F-tile JESD204C Intel FPGA IP Jagorar mai amfani

Daidaita Jagoran Daidaitawa (SHA)
Tebura 1. Daidaita Kan Jigon Gwajin Gwajin

Shari'ar Gwaji Manufar Bayani Sharuɗɗan wucewa
SHA.1 Bincika idan Sync Header Lock an tabbatar da shi bayan kammala tsarin sake saiti. Ana karanta sigina masu zuwa daga rajista:
  • Ana karanta CDR_Lock daga rajistar rx_status3 (0x8C).
  • An karanta SH_Locked daga rajistar rx_status4 (0x90).
  • jrx_sh_err_status ana karantawa daga rx_err_status (0x60).
  • CDR_Lock da SH_LOCK yakamata a tabbatar dasu zuwa tsayin daka daidai da adadin layuka.
  • jrx_sh_err_status ya kamata
  •  Filayen bit a cikin jrx_sh_err_status yana bincika sh_unlock_err, rx_gb_overflow_err, rx_gb_underflow_err, invalid_sync_header, src_rx_alarm, syspll_lock_err, da cdr_locked_err.
SHA.2 Bincika Matsayin Kulle Header Sync bayan an sami makullin kai na daidaitawa (ko lokacin Tsawaita Tsallake Tsallake Tsallake-tsalle) da kwanciyar hankali. invalid_sync_header ana karantawa don matsayin Sync Header kulle daga rajista (0x60[8]). Invalid_sync_header ya kamata ya zama 0.

Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙaddamarwa (EMBA)

Tebur 2. Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwaƙwalwa na Ƙaƙwalwa na Ƙaƙwalwa na Ƙaƙwalwa ) Mai Girma

Shari'ar Gwaji Manufar Bayani Sharuɗɗan wucewa  
EMBA.1 Bincika idan Extended Multiblock Lock an tabbatar da shi kawai bayan tabbatar da Kulle Header Sync. Ana karanta sigina masu zuwa ta hanyar rajista:
  • Ƙimar EMB_Locked_1 yakamata ta kasance daidai da 1 daidai da kowane layi. EMB_Lock_err yakamata ya zama 0.
  
 
  Shari'ar Gwaji Manufar Bayani Sharuɗɗan wucewa
     
  • Ana karanta EMB_Locked_1 daga rajistar rx_status5 (0x94).
  • Ana karanta EMB_Lock_err daga rx_err_status (0x60[19]).
  
  EMBA.2 Bincika idan Matsayin Kulle Multiblock Extended ya tsaya (bayan an tsawaita makullin katanga ko har sai an fito da buffer na roba) ba tare da ingantattun katangar multiblock ba. invalid_eomb_eoemb ana karantawa daga rx_err_status (0x60[10:9]). invalid_eomb_eoemb yakamata ya zama "00".
  EMBA.3 Duba daidaita layin. Ana karanta dabi'u masu zuwa daga rajista:
  • Ana karanta elastic_buf_over_flow daga rx_err_status (0x60[20]).
  • Ana karanta elastic_buf_full daga rajistar rx_status6 (0x98).
  • elastic_buf_over_flow yakamata ya zama 0.
  • Ƙimar elastic_buf_full yakamata ta zama daidai da 1 daidai da kowane layi.

Layer Transport Layer (TL)
Don bincika amincin bayanan rafin bayanan biyan kuɗi ta hanyar mai karɓar (RX) JESD204C Intel FPGA IP da layin sufuri, an saita ADC zuwa r.amp/ PRBS tsarin gwaji. Hakanan an saita ADC don aiki tare da tsari iri ɗaya kamar yadda aka saita a cikin JESD204C Intel FPGA IP. A ramp/PRBS Checker a cikin masana'anta na FPGA yana duba ramp/ PRBS amincin bayanai na minti daya. Rijistar RX JESD204C Intel FPGA IP rx_err ana ci gaba da zaɓe don ƙimar sifili na minti ɗaya.
Hoton da ke ƙasa yana nuna saitin gwajin ra'ayi don bincika amincin bayanai.

Hoto 3. Duba Mutuncin Bayanai Ta Amfani da Ramp/PRBS15 Mai duba

JESD204C-Intel-FPGA-IP-da-ADI-AD9081-MxF- ADC-Interoperability-Rahoton-03

Tebur 3. Abubuwan Gwajin Layer na sufuri

Shari'ar Gwaji Manufar Bayani Sharuɗɗan wucewa
TL.1 Duba taswirar layin sufuri na tashar bayanai ta amfani da ramp samfurin gwaji. Data_mode an saita zuwa Ramp_mode.

Ana karanta sigina masu zuwa ta hanyar rajista:

  • crc_err ana karantawa daga rx_err_status (0x60[14]).
  •  jrx_patchk_data_error ana karantawa daga rajistar tst_err0.
  • crc_err ya kamata ya zama ƙasa don wucewa.
  • jrx_patchk_data_error ya kamata yayi ƙasa.
TL.2 Bincika taswirar layin sufuri na tashar bayanai ta amfani da tsarin gwajin PRBS15. Data_mode an saita zuwa prbs_mode.

Ana karanta dabi'u masu zuwa daga rajista:

  • crc_err ana karantawa daga rx_err_status (0x60[14]).
  • jrx_patchk_data_error ana karantawa daga rajistar tst_err0.
  • crc_err ya kamata ya zama ƙasa don wucewa.
  • jrx_patchk_data_error ya kamata yayi ƙasa.

JESD204C Intel FPGA IP da Tsarin ADC
Ma'aunin JESD204C Intel FPGA IP (L, M, da F) a cikin wannan wurin duba kayan masarufi ana samun goyan bayan na'urar AD9081 ta asali. Matsakaicin adadin bayanan transceiver, sampagogon ling, da sauran sigogin JESD204C sun dace da yanayin aiki na AD908D1.
Gwajin duba kayan masarufi yana aiwatar da JESD204C Intel FPGA IP tare da saitin siga mai zuwa.

Saitin duniya don duk tsari:

  • E = 1
  • CF = 0
  • CS = 0
  • Subclass = 1
  • FCLK_MULP = 1
  • WIDTH_MULP = 8
  • SH_CONFIG = CRC-12
  • Agogon Gudanar da FPGA (MHz) = 100

Sakamakon Gwaji
Tebu mai zuwa ya ƙunshi sakamako mai yuwuwa da ma'anar su.

Table 4. Ma'anar sakamako

Sakamako Ma'anarsa
WUCE An lura da Na'urar Ƙarƙashin Gwaji (DUT) don nuna halaye masu dacewa.
PASS tare da sharhi An lura da DUT don nuna halaye masu dacewa. Koyaya, an haɗa ƙarin bayanin halin da ake ciki (misaliample: saboda ƙayyadaddun lokaci, an yi wani ɓangare na gwajin kawai).
Sakamako Ma'anarsa
GASKIYA An lura da DUT don nuna halin rashin daidaituwa.
Gargadi An lura da DUT don nuna halin da ba a ba da shawarar ba.
Koma zuwa sharhi Daga abubuwan da aka lura, an kasa tantance ingantaccen izinin wucewa ko gazawa. An haɗa ƙarin bayani game da halin da ake ciki.

Tebur mai zuwa yana nuna sakamakon gwajin gwaji SHA.1, SHA.2, EMBA.1, EMBA.2, EMBA.3, TL.1, da TL.2 tare da ma'auni na L, M, F, ƙimar bayanai, sampagogon ling, agogon haɗin gwiwa, da mitocin SYSREF.

Tebur 5. Sakamako na Abubuwan Gwaji SHA.1, SHA.2, EMBA.1, EMBA.2, EMBA.3, TL.1, da TL.2

A'a. L M F S HD E N NP ADC

Sampagogo (MHz)

 Agogon Na'urar FPGA (MHz) Farashin FPGA

Agogon Tsari (MHz)

 Farashin FPGA

Agogon haɗi (MHz)

 Adadin Layin (Gbps) Sakamako
1 8 4 1 1 0 1 16 16 3000.00 375.00 375.00 375.00 24.75 Wuce

Bayanin Sakamakon Gwaji
A cikin kowane shari'ar gwaji, RX JESD204C Intel FPGA IP ya sami nasarar kafa daidaitawar taken daidaitawa, tsawaita daidaitawar multiblock, kuma har sai lokacin bayanan mai amfani.
Babu batun amincin bayanan da Ramp da PRBS Checker don jeri na JESD wanda ke rufe duk hanyoyin jiki, haka nan ba a duba sake sakewa na cyclic (CRC) da kuskuren daidaiton umarni.
Yayin wasu zagayowar wutar lantarki, kuskuren deskew na layi na iya bayyana tare da daidaitawar siga. Don guje wa wannan kuskure, yakamata a tsara ƙimar ƙimar LEMC ko kuna iya sarrafa wannan ta hanyar share fage. Don ƙarin bayani kan ƙimar shari'a na biya diyya na LEMC, koma zuwa RBD Tuning Mechanism a F-tile JESD204C Jagorar Mai amfanin IP.

Bayanai masu alaƙa
RBD Tuning Mechanism

Takaitawa
Wannan rahoton yana nuna ingancin JESD204C Intel FPGA IP da PHY lantarki dubawa tare da na'urar AD9081/9082 (R2 Silicon) har zuwa 24.75 Gbps don ADC. Ana nuna cikakken saitin saitin kayan aiki da kayan aiki don samar da kwarin gwiwa game da aiki tare da aikin na'urorin biyu.

Tarihin Bita na Takardu don AN 927: JESD204C Intel FPGA IP da ADI AD9081 MxFE* Rahoton Haɗin gwiwar ADC don Intel Agilex F-Tile Devices

Sigar Takardu Canje-canje
2022.04.25 Sakin farko.

AN 876: JESD204C Intel® FPGA IP da ADI AD9081 MxFE* ADC Interoperability Report for Intel® Agilex® F-Tile Devices

Takardu / Albarkatu

intel JESD204C Intel FPGA IP da ADI AD9081 MxFE ADC Rahoton Haɗin kai [pdf] Jagorar mai amfani
JESD204C Intel FPGA IP da ADI AD9081 MxFE ADC Interoperability Report, JESD204C, Intel FPGA IP da ADI AD9081 MxFE ADC Rahoton Interoperability

Magana

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