JESD204C Intel FPGA IP le ADI AD9081 MxFE ADC Interoperability Report Guide

Litaba pata

1 JESD204C Intel FPGA IP le ADI AD9081 MxFE ADC Interoperability Report

2 Tlhahisoleseding ya Sehlahiswa

3 Litaelo tsa Tšebeliso ea Sehlahisoa

4 JESD204C Intel® FPGA IP le ADI AD9081 MxFE* ADC Interoperability Report for Intel® Agilex™ F-tile Devices

4.1 Tlhaloso ea Tsamaiso

5 Litokomane / Lisebelisoa

5.1 Litšupiso

JESD204C Intel FPGA IP le ADI AD9081 MxFE ADC Interoperability Report

Tlhahisoleseding ya Sehlahiswa

Sehlahisoa seo ho buuoang ka sona bukeng ea mosebelisi ke JESD204C Intel FPGA IP. Ke karolo ea hardware e sebelisoang hammoho le Intel Agilex I-Series F-Tile Demo Board le ADI AD9081-FMCA-EBZ EVM. IP e kentsoe ka mokhoa oa Duplex empa ho sebelisoa feela tsela ea moamoheli. E hlahisa oache ea khokahano ea 375 MHz le oache ea foreimi ea 375 MHz. Ho hlophisoa ha hardware bakeng sa teko ea ho sebelisana ha ADC ho bontšoa ho Setšoantšo sa 1. IP e hloka hore SYSREF e fanoe ke jenereithara ea oache e hlahisang oache ea sesebelisoa sa JESD204C Intel FPGA IP.

Litaelo tsa Tšebeliso ea Sehlahisoa

Ho hlophisoa ha Hardware
Ho theha lisebelisoa tsa ho sebelisa JESD204C Intel FPGA IP, latela mehato ena:

Hokela ADI AD9081-FMCA-EBZ EVM ho sehokelo sa FMC+ sa Intel Agilex I-Series F-Tile Demo Board.
Netefatsa hore lets'oao la SYSREF le fanoa ke jenereithara ea oache e fanang ka oache ea sesebelisoa sa JESD204C Intel FPGA IP.

Tlhaloso ea Tsamaiso
Setšoantšo sa boemo ba tsamaiso se bontša kamoo li-module tse fapaneng li hokahaneng kateng moralong ona. E kenyelletsa Intel Agilex-I F-tile Demo Board, Intel Agilex F-tile Device, Top-Level RTL, Platform Designer System, Pattern Generator, Pattern Checker, F-Tile JESD204C Duplex IP Core, le lioache tse fapa-fapaneng le li-interfaces.

Tšebelisano-'moho Mokhoa
Lera la Khokahanyo ea data ea Receiver
Sebaka sena sa teko se akaretsa linyeoe tsa teko bakeng sa sync header alignment (SHA) le multiblock alignment (EMBA) e atolositsoeng. JESD204C Intel FPGA IP e bala lirekoto ho tsoa ho sehokelo sa data nakong ea tlhahlobo, e li ngola ho log files, mme e li netefatse bakeng sa ho feta mekhoa ea ho fetisa mangolo a TCL.

JESD204C Intel® FPGA IP le ADI AD9081 MxFE* ADC Interoperability Report for Intel® Agilex™ F-tile Devices

JESD204C Intel® FPGA IP ke sesebelisoa sa serial interface sa serial intellectual property (IP) sa lebelo le holimo.
JESD204C Intel FPGA IP e 'nile ea lekoa ka hardware ka lisebelisoa tse' maloa tse khethiloeng tsa JESD204C tse lumellanang le analog-to-digital converter (ADC).
Tlaleho ena e totobatsa tšebelisano-'moho ea JESD204C Intel FPGA IP le mojule oa tlhahlobo ea AD9081 Mixed Signal Front End (MxFE *) (EVM) ho tsoa ho Analog Devices Inc. (ADI). Likarolo tse latelang li hlalosa mokhoa oa ho tsoa ha hardware le liphetho tsa liteko.

Lintlha Tse Amanang
F-tile JESD204C Intel FPGA IP User Guide

Litlhoko tsa Hardware le Software
Teko ea ho sebelisana e hloka lisebelisoa tse latelang tsa Hardware le software: Hardware

Intel Agilex™ I-Series F-tile Demo Board (AGIB027R29A1E2VR0) e nang le adaptara ea matla ea 12V

Lisebelisoa tsa Analog (ADI) AD9081 MxFE* EVM (AD9081-FMCA-EBZ, Rev C)
Skywork Si5345-D Evaluation Board (Si5345-D-EVB)

SMA e tona ho ea ho SMP e motona
SMP e motona ho ea ho thapo ea SMP

Software

Intel Quartus® Prime Pro Edition software version 21.4

AD9081_API mofuta 1.1.0 kapa e ncha (ts'ebeliso ea Linux, e hlokahalang bakeng sa phetisetso ea AD9081 EVM)

Lintlha Tse Amanang

AD9081/AD9082 Tataiso ea Ts'ebetso ea Ts'ebetso ea Sistimi
Skyworks Si5345-D Evaluation Board Tataiso ea Mosebelisi

Ho hlophisoa ha Hardware
JESD204C Intel FPGA IP e kentsoe ka mokhoa oa Duplex empa ho sebelisoa tsela ea moamoheli feela. Bakeng sa FCLK_MULP =1, WIDTH_MULP = 8, S = 1, PLL ea mantlha e hlahisa oache ea khokahanyo ea 375 MHz le oache ea foreimi ea 375 MHz.
Intel Agilex I-Series F-Tile Demo Board e sebelisoa le ADI AD9081-FMCA-EBZ EVM e hokahaneng le sehokelo sa FMC+ sa boto ea ntlafatso. Ho hlophisoa ha hardware bakeng sa teko ea ho sebelisana ha ADC ho bontšoa setšoantšong sa Setupo sa Hardware.- • AD9081-FMCA-EBZ EVM e fumana matla ho Intel Agilex I-Series F-Tile Demo Board ka sehokelo sa FMC +.

F-tile transceiver le JESD204C Intel FPGA IP core PLL lioache li fanoa ke Si5345-D-EVB ka SMA ho ea SMP cable. Beha MUX_DIP_SW0 holimo ho Agilex-I F-Tile Demo Board ho netefatsa hore U22 e nka CLKIN1 e hoketsoeng thapong ea SMP.

Si5345-D-EVB e fana ka oache ea litšupiso ho jenereithara ea lioache e hlophisehileng ea HMC7044 e teng ho AD9081 EVM ka thapo ea SMP ho ea ho SMP.
Oache ea tsamaiso ea JESD204C Intel FPGA IP core e fanoe ke Silicon Labs Si5332 jenereithara e ka khonehang ea oache e teng ho Intel Agilex I-Series F-tile Demo Board.

HMC7044 jenereithara ea lioache e lokiselitsoeng e fana ka oache ea litšupiso ea sesebelisoa sa AD9081. Phase-locked loop (PLL) e teng ka har'a sesebelisoa sa AD9081 e hlahisa li-ADC tse lakatsehang.ampoache ea ling ho tloha ho sesupo sa sesebediswa.
Bakeng sa Subclass 1, jenereithara ea oache ea HMC7044 e hlahisa lets'oao la SYSREF bakeng sa sesebelisoa sa AD9081 le bakeng sa JESD204C Intel FPGA IP ka sehokelo sa FMC +.

Chete: Intel e khothaletsa SYSREF hore e fanoe ke jenereithara ea oache e fanang ka oache ea sesebelisoa sa JESD204C Intel FPGA IP.

Tlhaloso ea Tsamaiso

Setšoantšo se latelang sa boemo ba tsamaiso se bontša kamoo li-module tse fapaneng li hokahaneng kateng moralong ona.

Setšoantšo sa 2. Setšoantšo sa Sistimi

Lintlha:

M ke palo ea li-converter.
S ke palo ea a fetisoang samptlase ka ho ya ka converter ka foreime.
WIDTH_MULP ke sekhahla sa bophara ba data lipakeng tsa sekhahla sa ts'ebeliso le sekhahla sa lipalangoang.
N ke palo ea likotoana tsa ho sokoloha ka converter.
CS ke palo ea li-bits tsa taolo ho phetolo ea samples.

Setupong sena, mohlalaample L = 8, M = 4, le F = 1, tekanyo ea data ea litsela tsa transceiver ke 24.75 Gbps.
Si5332 OUT1 e hlahisa oache ea 100 MHz ho mgmt_clk. Si5345-D-EVB e hlahisa maqhubu a mabeli a oache, 375 MHz le 100 MHz. 375 MHz e fanoa ho multiplexer e kentsoeng ho Intel Agilex I-Series F-tile Demo Board ka boema-kepe ba J19 SMA. Oache ea tlhahiso ea multiplexer e kentsoeng e khanna oache ea refclk_xcvr ea F-tile (refclk_xcvr) le JESD204C Intel FPGA IP core PLL clock (refclk_core). 100 MHz ho tloha ho Si5345-D-EVB e hokahane le jenereithara ea HMC7044 e ka fetolehang ea oache e teng ho AD9081 EVM joalo ka kenyeletso ea oache.
(EXT_HMCREF).

HCM7044 e hlahisa lets'oao la nako le nako la SYSREF la 11.71875 MHz ka Sehokelo sa FMC.
JESD204C Intel FPGA IP e kentsoe ka mokhoa oa Duplex empa ho sebelisoa tsela ea moamoheli feela.

Tšebelisano-'moho Mokhoa
Karolo e latelang e hlalosa lipheo tsa tlhahlobo, mokhoa oa tšebetso le mekhoa ea ho feta. Teko e akaretsa libaka tse latelang:

Lera la khokahano ea data ea moamoheli
Lera la lipalangoang tsa moamoheli

Lera la Khokahanyo ea data ea Receiver
Sebaka sena sa teko se akaretsa linyeoe tsa teko bakeng sa sync header alignment (SHA) le multiblock alignment (EMBA) e atolositsoeng.
Ho qala sehokelo, kamora hore moamoheli a hlophise bocha, JESD204C Intel FPGA IP e qala ho batla molatsoana oa hlooho ea sync o fetisoang ke sesebelisoa. Lingoliloeng tse latelang tse tsoang ho data link layer li baloa nakong ea tlhahlobo, li ngotsoe ho log files, le ho netefatsoa bakeng sa ho fetisa mekhoa ea ho fetisa mangolo a TCL.

Lintlha Tse Amanang
F-tile JESD204C Intel FPGA IP User Guide

Khokahano ea Hlooho (SHA)
Lethathamo la 1. Sync Maemo a Teko a ho Lokisana ha Hlooho

Nyeoe ea Teko	Sepheo	Tlhaloso	Ho Fetisa Litekanyetso
SHA.1	Sheba hore na Sync Header Lock e tiisitsoe ka mor'a hore ho phethoe tatellano ea reset.	Matshwao a latelang a balwa ho tswa ho direjistara: CDR_Lock e baloa ho tsoa bukeng ea rx_status3 (0x8C). SH_Locked e baloa ho tsoa bukeng ea rx_status4 (0x90). jrx_sh_err_status e baloa ho tsoa bukeng ea rx_err_status (0x60).	CDR_Lock le SH_LOCK li tlameha ho tiisetsoa ka holimo ho tsamaisanang le palo ea litselana. jrx_sh_err_status e lokela ho ba Li-bit fields ho jrx_sh_err_status li hlahloba sh_unlock_err, rx_gb_overflow_err, rx_gb_underflow_err, invalid_sync_header, src_rx_alarm, syspll_lock_err, le cdr_locked_err.
SHA.2	Sheba boemo ba Sync Header Lock ka mor'a hore senotlolo sa hlooho sa sync se fihletsoe (kapa nakong ea Mokhahlelo o Atolositsoeng oa Multi-Block Alignment) mme o tsitsitse.	invalid_sync_header e baloa bakeng sa boemo ba senotlolo sa Sync Header ho tsoa ho rejisetara (0x60[8]).	invalid_sync_header boemo bo lokela ho ba 0.

Tekanyetso e Atolositsoeng ea Multiblock (EMBA)

Letlapa la 2. Maemo a Atolositsoeng a Multiblock Alignment Test

Nyeoe ea Teko		Sepheo		Tlhaloso		Ho Fetisa Litekanyetso
EMBA.1		Lekola hore na Lock e Atolositsoeng ea Multiblock e tiisitsoe feela ka mor'a polelo ea Sync Header Lock.		Matshwao a latelang a balwa ka direjista:		Theko ea EMB_Locked_1 e lokela ho lekana le 1 e tsamaellanang le tsela ka 'ngoe. EMB_Lock_err e lokela ho ba 0.

	Nyeoe ea Teko		Sepheo		Tlhaloso		Ho Fetisa Litekanyetso
					EMB_Locked_1 e baloa ho tsoa bukeng ea rx_status5 (0x94). EMB_Lock_err e baloa ho tsoa bukeng ea rx_err_status (0x60[19]).
	EMBA.2		Lekola hore na boemo bo Atolositsoeng ba Multiblock Lock bo tsitsitse (kamora ho notlelloa ha li-multiblock tse atolositsoeng kapa ho fihlela buffer e lokollotsoeng) ho se na li-multiblock tse fosahetseng.		invalid_eomb_eoemb e baloa ho tsoa bukeng ea rx_err_status (0x60[10:9]).		invalid_eomb_eoemb e lokela ho ba "00".
	EMBA.3		Sheba tsela ea ho tsamaisana.		Lintlha tse latelang li baloa ho tsoa lirejiseteng: elastic_buf_over_flow e baloa ho tsoa bukeng ea rx_err_status (0x60[20]). elastic_buf_full e baloa ho tsoa bukeng ea rx_status6 (0x98).		elastic_buf_over_flow e lokela ho ba 0. The elastic_buf_full value e lokela ho lekana le 1 e tsamaellanang le lane ka 'ngoe.

Leya la Lipalangoang la Moamoheli (TL)
Ho lekola botšepehi ba data ea phallo ea data ea payload ka moamoheli (RX) JESD204C Intel FPGA IP le lera la lipalangoang, ADC e lokiselitsoe ho r.amp/ PRBS mohlala oa teko. ADC e boetse e hlophiselitsoe ho sebetsa ka tlhophiso e ts'oanang le e behiloeng ho JESD204C Intel FPGA IP. The ramp/ PRBS e hlahloba lesela la FPGA e hlahloba ramp/PRBS botšepehi ba data motsotso o le mong. Registara ea IP ea RX JESD204C Intel FPGA rx_err e hlahlojoa khafetsa bakeng sa boleng ba zero motsotso o le mong.
Setšoantšo se ka tlase se bonts'a tlhahlobo ea tlhahlobo ea mohopolo bakeng sa ho lekola botšepehi ba data.

Setšoantšo sa 3. Tlhahlobo ea Botšepehi ba Data Ho Sebelisa Ramp/PRBS15 Checker

Lethathamo la 3. Linyeoe tsa Teko tsa Lera la Lipalangoang

Nyeoe ea Teko

Sepheo

Tlhaloso

Ho Fetisa Litekanyetso

TL.1

Sheba 'mapa oa lera la lipalangoang tsa mocha oa data u sebelisa ramp mohlala oa teko.

Data_mode e hlophisitsoe ho Ramp_mokhoa.

Matshwao a latelang a balwa ka direjista:

crc_err e baloa ho tsoa ho rx_err_status (0x60[14]).
jrx_patchk_data_error e baloa ho tsoa bukeng ea tst_err0.

crc_err e lokela ho ba tlase ho feta.
jrx_patchk_data_error e lokela ho ba tlase.

TL.2

Sheba 'mapa oa lera la lipalangoang tsa mocha oa data ho sebelisa mokhoa oa teko oa PRBS15.

Data_mode e setetsoe ho prbs_mode.

Lintlha tse latelang li baloa ho tsoa lirejiseteng:

crc_err e baloa ho tsoa ho rx_err_status (0x60[14]).
jrx_patchk_data_error e baloa ho tsoa bukeng ea tst_err0.

crc_err e lokela ho ba tlase ho feta.
jrx_patchk_data_error e lokela ho ba tlase.

JESD204C Intel FPGA IP le ADC Configurations
Litekanyetso tsa JESD204C Intel FPGA IP (L, M, le F) sebakeng sena sa ho lefshoa ha hardware li tšehetsoa ka tlhaho ke sesebelisoa sa AD9081. Sekhahla sa data ea transceiver, sampling oache, le likarolo tse ling tsa JESD204C li lumellana le maemo a ts'ebetso a AD908D1.
Teko ea ho hlahloba lisebelisoa tsa thepa e sebelisa JESD204C Intel FPGA IP ka tlhophiso e latelang ea paramente.

Litlhophiso tsa lefats'e bakeng sa litlhophiso tsohle:

E = 1

CF = 0
CS = 0
Sehlopha se senyenyane = 1

FCLK_MULP = 1
WIDTH_MULP = 8
SH_CONFIG = CRC-12

Oache ea Tsamaiso ea FPGA (MHz) = 100

Liphetho tsa liteko
Tafole e latelang e na le liphetho tse ka bang teng le tlhaloso ea tsona.

Lethathamo la 4. Tlhaloso ea Liphetho

Sephetho	Tlhaloso
PHASA	The Device Under Test (DUT) e ile ea shejoa ho bonts'a boitšoaro bo lumellanang.
PASS ka maikutlo	DUT e ile ea shejoa ho bontša boitšoaro bo lumellanang. Leha ho le joalo, tlhaloso e eketsehileng ea boemo e kenyelelitsoe (mohlalaample: ka lebaka la mefokolo ea nako, ke karolo e itseng feela ea tlhahlobo e ileng ea etsoa).

Sephetho	Tlhaloso
HLOMELA	DUT e ile ea hlokomeloa ho bontša boitšoaro bo sa lumellaneng.
Tlhokomediso	DUT e ile ea shejoa ho bontša boitšoaro bo sa khothaletsoang.
Sheba maikutlo	Ho latela se hlokometsoeng, ho pasa ho nepahetseng kapa ho hloleha ho ne ho ke ke ha tsejoa. Tlhaloso e eketsehileng ea boemo e kenyelelitsoe.

Tafole e latelang e bonts'a liphetho tsa linyeoe tsa liteko SHA.1, SHA.2, EMBA.1, EMBA.2, EMBA.3, TL.1, le TL.2 ka litekanyetso tse fapaneng tsa L, M, F, sekhahla sa data, sampoache ea ling, oache ea khokahano, le maqhubu a SYSREF.

Lethathamo la 5. Sephetho sa Maemo a Teko SHA.1, SHA.2, EMBA.1, EMBA.2, EMBA.3, TL.1, and TL.2

Che.	L	M	F	S	HD	E	N	NP	ADC SampOache e telele (MHz)	Oache ea Sesebelisoa sa FPGA (MHz)	FPGA Oache ea Foreme (MHz)	FPGA Khokahano oache (MHz)	Rate ea Lane (Gbps)	Sephetho
1	8	4	1	1	0	1	16	16	3000.00	375.00	375.00	375.00	24.75	Feta

Maikutlo a Sephetho sa Teko
Ketsahalong e 'ngoe le e' ngoe ea teko, RX JESD204C Intel FPGA IP e atlehile ho theha khokahano ea hlooho ea sync, alignment e atolositsoeng ea li-multiblock, le ho fihlela karolo ea data ea mosebelisi.
Ha ho na taba ea botšepehi ba data e hlokometsoeng ke Ramp le PRBS checker bakeng sa tlhophiso ea JESD e koahelang litsela tsohle tsa 'mele, hape ha ho na tlhahlobo ea cyclic redundancy check (CRC) le phoso ea parity ea taelo e hlokometsoeng.
Nakong ea lipotoloho tse itseng tsa matla, phoso ea lane deskew e ka hlaha ka litlhophiso tsa paramethara. Ho qoba phoso ena, litekanyetso tsa offset tsa LEMC li lokela ho hlophisoa kapa u ka etsa sena ka mokhoa oa ho fiela. Bakeng sa tlhaiso-leseling e batsi mabapi le boleng ba molao ba LEMC offset, sheba ho RBD Tuning Mechanism ho F-tile JESD204C IP User Guide.

Lintlha Tse Amanang
Mokhoa oa ho lokisa oa RBD

Kakaretso
Tlaleho ena e bonts'a netefatso ea JESD204C Intel FPGA IP le PHY segokanyimmediamentsi sa sebolokigolo sa AD9081/9082 (R2 Silicon) ho fihla ho 24.75 Gbps bakeng sa ADC. Tlhophiso e felletseng le setupo sa Hardware li bonts'oa ho fana ka kholiseho ts'ebetsong le ts'ebetsong ea lisebelisoa tse peli.

Nalane ea Tokomane ea Tokomane bakeng sa AN 927: JESD204C Intel FPGA IP le ADI AD9081 MxFE* ADC Interoperability Report bakeng sa Intel Agilex F-Tile Devices

Tokomane Version	Liphetoho
2022.04.25	Tokollo ea pele.

AN 876: JESD204C Intel® FPGA IP le ADI AD9081 MxFE* ADC Interoperability Report for Intel® Agilex® F-Tile Devices

Litokomane / Lisebelisoa

Intel JESD204C Intel FPGA IP le ADI AD9081 MxFE ADC Interoperability Report [pdf] Bukana ea Mosebelisi
JESD204C Intel FPGA IP le ADI AD9081 MxFE ADC Interoperability Report, JESD204C, Intel FPGA IP le ADI AD9081 MxFE ADC Interoperability Report

Litšupiso

Bukana ea Mosebelisi