JESD204C Intel FPGA IP thiab ADI AD9081 MxFE ADC Interoperability Report User Guide

Cov ntsiab lus zais

1 JESD204C Intel FPGA IP thiab ADI AD9081 MxFE ADC Interoperability Report

2 Cov ntaub ntawv khoom

3 Cov lus qhia siv khoom

4 JESD204C Intel® FPGA IP thiab ADI AD9081 MxFE* ADC Interoperability Report rau Intel® Agilex™ F-tile Devices

4.1 System Description

5 Cov ntaub ntawv / Cov ntaub ntawv

5.1 Cov ntaub ntawv

JESD204C Intel FPGA IP thiab ADI AD9081 MxFE ADC Interoperability Report

Cov ntaub ntawv khoom

Cov khoom xa mus rau hauv phau ntawv siv yog JESD204C Intel FPGA IP. Nws yog cov khoom siv kho vajtse uas tau siv ua ke nrog Intel Agilex I-Series F-Tile Demo Board thiab ADI AD9081-FMCA-EBZ EVM. IP yog instantiated nyob rau hauv Duplex hom tab sis tsuas yog txoj kev txais tau siv. Nws tsim 375 MHz txuas moos thiab 375 MHz ncej moos. Kev teeb tsa kho vajtse rau ADC kev sib cuam tshuam kev sim tau pom nyob rau hauv daim duab 1. Tus IP yuav tsum tau SYSREF muab los ntawm lub tshuab hluav taws xob moos uas muab JESD204C Intel FPGA IP ntaus ntawv moos.

Cov lus qhia siv khoom

Kev teeb tsa kho vajtse
Txhawm rau teeb tsa cov khoom siv rau kev siv JESD204C Intel FPGA IP, ua raws li cov kauj ruam no:

Txuas ADI AD9081-FMCA-EBZ EVM rau FMC + txuas ntawm Intel Agilex I-Series F-Tile Demo Board.
Xyuas kom meej tias SYSREF teeb liab yog muab los ntawm lub tshuab hluav taws xob moos uas muab JESD204C Intel FPGA IP ntaus ntawv moos.

System Description
Daim duab-theem qhia tau hais tias qhov sib txawv modules txuas nrog hauv qhov tsim no li cas. Nws suav nrog Intel Agilex-I F-tile Demo Board, Intel Agilex F-tile Device, Sab saum toj-Qib RTL, Platform Designer System, Pattern Generator, Pattern Checker, F-Tile JESD204C Duplex IP Core, thiab ntau lub moos thiab interfaces.

Txoj Kev Sib Koom Tes
Receiver Data Link Layer
Qhov chaw sim no suav nrog cov xwm txheej sim rau kev sib koom ua ke ntawm lub taub hau (SHA) thiab txuas ntxiv ntau qhov sib dhos (EMBA). JESD204C Intel FPGA IP nyeem cov ntawv sau npe los ntawm cov ntaub ntawv txuas txheej thaum lub sijhawm xeem, sau rau hauv cov ntawv sau files, thiab txheeb xyuas lawv kom dhau cov txheej txheem los ntawm TCL cov ntawv sau.

JESD204C Intel® FPGA IP thiab ADI AD9081 MxFE* ADC Interoperability Report rau Intel® Agilex™ F-tile Devices

JESD204C Intel® FPGA IP yog qhov ceev ceev point-to-point serial interface kev txawj ntse (IP).
JESD204C Intel FPGA IP tau raug kuaj kho vajtse nrog ob peb xaiv JESD204C raws li analog-to-digital converter (ADC) li.
Daim ntawv tshaj tawm no qhia txog kev sib cuam tshuam ntawm JESD204C Intel FPGA IP nrog AD9081 Mixed Signal Front End (MxFE*) kev soj ntsuam module (EVM) los ntawm Analog Devices Inc. (ADI). Cov ntu hauv qab no piav qhia txog cov txheej txheem kuaj xyuas kho vajtse thiab cov txiaj ntsig kev xeem.

Cov ntaub ntawv ntsig txog
F-tile JESD204C Intel FPGA tus neeg siv phau ntawv qhia

Hardware thiab Software Requirements
Kev ntsuas kev sib koom tes yuav tsum muaj cov cuab yeej kho vajtse thiab software hauv qab no: Hardware

Intel Agilex™ I-Series F-tile Demo Board (AGIB027R29A1E2VR0) nrog 12V fais fab adapter

Analog Devices (ADI) AD9081 MxFE* EVM (AD9081-FMCA-EBZ, Rev C)
Skywork Si5345-D Evaluation Board (Si5345-D-EVB)

SMA txiv neej rau SMP txiv neej
SMP txiv neej rau SMP cable

Software

Intel Quartus® Prime Pro Edition software version 21.4

AD9081_API version 1.1.0 lossis tshiab dua (Linux application, xav tau rau AD9081 EVM configuration)

Cov ntaub ntawv ntsig txog

AD9081/AD9082 Kev Txhim Kho Cov Neeg Siv Phau Ntawv Qhia
Skyworks Si5345-D Evaluation Board User Guide

Kev teeb tsa kho vajtse
JESD204C Intel FPGA IP yog instantiated hauv Duplex hom tab sis tsuas yog siv txoj kev txais. Rau FCLK_MULP = 1, WIDTH_MULP = 8, S = 1, cov tub ntxhais PLL tsim 375 MHz txuas moos thiab 375 MHz ncej moos.
Intel Agilex I-Series F-Tile Demo Board yog siv nrog ADI AD9081-FMCA-EBZ EVM txuas nrog FMC + connector ntawm pawg thawj coj loj hlob. Kev teeb tsa kho vajtse rau ADC kev sib cuam tshuam kev sim tau pom nyob rau hauv Hardware Setup daim duab.- • AD9081-FMCA-EBZ EVM muab lub zog los ntawm Intel Agilex I-Series F-Tile Demo Board los ntawm FMC + connector.

F-tile transceiver thiab JESD204C Intel FPGA IP core PLL siv moos yog muab los ntawm Si5345-D-EVB los ntawm SMA rau SMP cable. Teem MUX_DIP_SW0 kom siab rau Agilex-I F-Tile Demo Board kom ntseeg tau tias U22 noj CLKIN1 uas txuas nrog SMP cable.

Si5345-D-EVB muab lub moos siv rau HMC7044 programmable moos generator tam sim no hauv AD9081 EVM los ntawm SMP rau SMP cable.
Lub moos tswj rau JESD204C Intel FPGA IP core yog muab los ntawm Silicon Labs Si5332 programmable moos generator tam sim no nyob rau hauv Intel Agilex I-Series F-tile Demo Board.

HMC7044 programmable moos generator muab AD9081 ntaus ntawv siv moos. Theem-locked voj (PLL) tam sim no nyob rau hauv AD9081 ntaus ntawv generates qhov xav tau ADC sampling moos los ntawm cov cuab yeej siv moos.
Rau Subclass 1, HMC7044 moos generator tsim SYSREF teeb liab rau AD9081 ntaus ntawv thiab rau JESD204C Intel FPGA IP los ntawm FMC + connector.

Tsis muajte: Intel xav kom SYSREF muab los ntawm lub tshuab hluav taws xob moos uas tau txais JESD204C Intel FPGA IP ntaus ntawv moos.

System Description

Cov kab ke hauv qab no qhia tau hais tias qhov sib txawv modules txuas nrog hauv qhov tsim no li cas.

Daim duab 2. System Diagram

Sau ntawv:

M yog tus naj npawb ntawm converters.
S yog tus naj npawb ntawm kis samples per converter ib thav duab.
WIDTH_MULP yog cov ntaub ntawv dav dav ntawm daim ntawv thov txheej thiab thauj txheej.
N yog tus naj npawb ntawm cov khoom hloov pauv rau ib lub converter.
CS yog tus naj npawb ntawm cov khoom tswj ib qho kev hloov pauv samples.

Hauv kev teeb tsa no, rau example L = 8, M = 4, thiab F = 1, cov ntaub ntawv tus nqi ntawm transceiver kab yog 24.75 Gbps.
Si5332 OUT1 tsim 100 MHz moos rau mgmt_clk. Si5345-D-EVB tsim ob lub moos zaus, 375 MHz thiab 100 MHz. Lub 375 MHz yog muab rau lub embedded multiplexer hauv Intel Agilex I-Series F-tile Demo Board los ntawm J19 SMA chaw nres nkoj. Lub moos tso zis ntawm cov khoom sib xyaw ua ke tsav lub F-tile transceiver siv moos (refclk_xcvr) thiab JESD204C Intel FPGA IP core PLL siv moos (refclk_core). 100 MHz los ntawm Si5345-D-EVB txuas nrog HMC7044 programmable moos generator tam sim no nyob rau hauv AD9081 EVM raws li lub moos input
(EXT_HMCREF).

HCM7044 tsim ib lub sijhawm SYSREF teeb liab ntawm 11.71875 MHz los ntawm FMC Connector.
JESD204C Intel FPGA IP yog instantiated hauv Duplex hom tab sis tsuas yog siv txoj kev txais.

Txoj Kev Sib Koom Tes
Nqe lus hauv qab no piav qhia txog lub hom phiaj ntawm kev xeem, txheej txheem, thiab cov txheej txheem dhau los. Qhov kev xeem no suav nrog thaj chaw hauv qab no:

Receiver data link txheej
Receiver thauj txheej

Receiver Data Link Layer
Qhov chaw sim no suav nrog cov xwm txheej sim rau kev sib koom ua ke ntawm lub taub hau (SHA) thiab txuas ntxiv ntau qhov sib dhos (EMBA).
Ntawm qhov txuas pib, tom qab lub receiver pib dua, JESD204C Intel FPGA IP pib nrhiav cov sync header kwj uas kis tau los ntawm lub cuab yeej. Cov ntawv sau npe hauv qab no los ntawm cov ntaub ntawv txuas txheej tau nyeem thaum lub sijhawm xeem, sau rau hauv lub cav files, thiab txheeb xyuas cov txheej txheem dhau los ntawm TCL cov ntawv sau.

Cov ntaub ntawv ntsig txog
F-tile JESD204C Intel FPGA tus neeg siv phau ntawv qhia

Sync Header Alignment (SHA)
Table 1. Sync Header Alignment Test Cases

Kuaj Case	Lub hom phiaj	Kev piav qhia	Txoj Cai Hla
SHA.1	Xyuas yog tias Sync Header Lock tau lees paub tom qab ua tiav ntawm qhov rov pib ua tiav.	Cov cim hauv qab no tau nyeem los ntawm cov ntawv sau npe: CDR_Lock yog nyeem los ntawm rx_status3 (0x8C) sau npe. SH_Locked yog nyeem los ntawm rx_status4 (0x90) sau npe. jrx_sh_err_status yog nyeem los ntawm rx_err_status (0x60) sau npe.	CDR_Lock thiab SH_LOCK yuav tsum tau lees paub rau siab sib xws rau cov kab ntau lawm. jrx_sh_err_status yuav tsum yog Cov teb me ntsis hauv jrx_sh_err_status kuaj rau sh_unlock_err, rx_gb_overflow_err, rx_gb_underflow_err, invalid_sync_header, src_rx_alarm, syspll_lock_err, thiab cdr_locked_err.
SHA.2	Kos Sync Header Lock raws li txoj cai tom qab sync header xauv tau tiav (los yog thaum lub sij hawm Extended Multi-Block Alignment theem) thiab ruaj khov.	invalid_sync_header yog nyeem rau Sync Header xauv xwm txheej los ntawm kev sau npe (0x60[8]).	invalid_sync_header xwm txheej yuav tsum yog 0.

Extended Multiblock Alignment (EMBA)

Table 2. Extended Multiblock Alignment Test Cases

Kuaj Case		Lub hom phiaj		Kev piav qhia		Txoj Cai Hla
EMBA.1		Xyuas seb qhov Extended Multiblock Lock tau lees paub tsuas yog tom qab qhov kev lees paub ntawm Sync Header Lock.		Cov teeb liab hauv qab no tau nyeem los ntawm cov ntawv sau npe:		Tus nqi EMB_Locked_1 yuav tsum sib npaug rau 1 sib raug rau txhua txoj kab. EMB_Lock_err yuav tsum yog 0.

	Kuaj Case		Lub hom phiaj		Kev piav qhia		Txoj Cai Hla
					EMB_Locked_1 yog nyeem los ntawm rx_status5 (0x94) sau npe. EMB_Lock_err yog nyeem los ntawm rx_err_status (0x60[19]) sau npe.
	EMBA.2		Xyuas seb qhov Extended Multiblock Lock li cas yog ruaj khov (tom qab txuas ntxiv multiblock xauv los yog kom txog thaum lub elastic buffer tso tawm) nrog rau tsis muaj qhov tsis siv tau ntau.		invalid_eomb_eoemb yog nyeem los ntawm rx_err_status (0x60[10:9]) sau npe.		invalid_eomb_eoemb yuav tsum yog "00".
	EMBA.3		Txheeb xyuas txoj kab sib dhos.		Cov txiaj ntsig hauv qab no tau nyeem los ntawm cov ntawv sau npe: elastic_buf_over_flow yog nyeem los ntawm rx_err_status (0x60[20]) sau npe. elastic_buf_full yog nyeem los ntawm rx_status6 (0x98) rau npe.		elastic_buf_over_flow yuav tsum yog 0. Tus nqi elastic_buf_full yuav tsum sib npaug rau 1 sib raug rau txhua txoj kab.

Txais Thauj Txheej (TL)
Txhawm rau txheeb xyuas cov ntaub ntawv kev ncaj ncees ntawm cov ntaub ntawv them nyiaj ntws los ntawm tus txais (RX) JESD204C Intel FPGA IP thiab thauj txheej, ADC tau teeb tsa rau ramp/ PRBS xeem qauv. ADC kuj tau teeb tsa ua haujlwm nrog tib lub teeb tsa raws li tau teev tseg hauv JESD204C Intel FPGA IP. Cov ramp/ PRBS checker nyob rau hauv FPGA ntaub check ramp/PRBS cov ntaub ntawv ncaj ncees rau ib feeb. RX JESD204C Intel FPGA IP sau npe rx_err tau soj ntsuam tsis tu ncua rau pes tsawg tus nqi rau ib feeb.
Daim duab hauv qab no qhia txog kev teeb tsa lub tswv yim rau kev kuaj xyuas cov ntaub ntawv.

Daim duab 3. Kev Tshawb Xyuas Cov Ntaub Ntawv Siv Ramp/PRBS15 Checker

Table 3. Thawv Txheej Txheej Txheej Txheem

Kuaj Case

Lub hom phiaj

Kev piav qhia

Txoj Cai Hla

TL.1

Txheeb xyuas cov txheej txheem thauj khoom ntawm cov ntaub ntawv channel siv ramp kuaj qauv.

Data_mode yog teem rau Ramp_mode.

Cov teeb liab hauv qab no tau nyeem los ntawm cov ntawv sau npe:

crc_err yog nyeem los ntawm rx_err_status (0x60[14]).
jrx_patchk_data_error yog nyeem los ntawm tst_err0 sau npe.

crc_err yuav tsum qis kom dhau.
jrx_patchk_data_error yuav tsum tsawg.

TL.2

Txheeb xyuas cov txheej txheem thauj khoom ntawm cov ntaub ntawv channel siv PRBS15 tus qauv xeem.

Data_mode yog teem rau prbs_mode.

Cov txiaj ntsig hauv qab no tau nyeem los ntawm cov ntawv sau npe:

crc_err yog nyeem los ntawm rx_err_status (0x60[14]).
jrx_patchk_data_error yog nyeem los ntawm tst_err0 sau npe.

crc_err yuav tsum qis kom dhau.
jrx_patchk_data_error yuav tsum tsawg.

JESD204C Intel FPGA IP thiab ADC Configurations
JESD204C Intel FPGA IP parameters (L, M, thiab F) hauv qhov kev kuaj xyuas kho vajtse no yog ib txwm txhawb nqa los ntawm AD9081 ntaus ntawv. Tus nqi transceiver, sampling moos, thiab lwm yam JESD204C tsis ua raws li AD908D1 kev ua haujlwm.
Kev kuaj xyuas kho vajtse siv JESD204C Intel FPGA IP nrog rau cov kev teeb tsa hauv qab no.

Kev teeb tsa thoob ntiaj teb rau txhua qhov kev teeb tsa:

E = 1

CF = 0
CS = 0
Subclass = 1

FCLK_MULP = 1
WIDTH_MULP = 8
SH_CONFIG = CRC-12

FPGA tswj moos (MHz) = 100

Cov qhabnias xeem
Cov lus hauv qab no muaj cov txiaj ntsig tau thiab lawv txhais.

Table 4. Cov ntsiab lus txhais

Kev tshwm sim	Txhais
PASS	Lub Device Under Test (DUT) tau soj ntsuam kom pom tus cwj pwm tsis zoo.
PASS nrog cov lus pom	DUT tau soj ntsuam kom pom tus cwj pwm tsis raug. Txawm li cas los xij, muaj kev piav qhia ntxiv txog qhov xwm txheej no (example: vim lub sijhawm txwv, tsuas yog ib feem ntawm qhov kev sim tau ua).

Kev tshwm sim	Txhais
FAIL	DUT tau raug pom los ua pov thawj tus cwj pwm tsis sib haum.
Ceeb toom	DUT tau soj ntsuam kom pom tus cwj pwm uas tsis pom zoo.
Xa mus rau cov lus pom	Los ntawm cov kev soj ntsuam, ib tug siv tau pass los yog tsis tau txiav txim. Muaj ib qho kev piav qhia ntxiv ntawm qhov xwm txheej.

Cov lus hauv qab no qhia txog cov txiaj ntsig ntawm qhov kev xeem SHA.1, SHA.2, EMBA.1, EMBA.2, EMBA.3, TL.1, thiab TL.2 nrog rau qhov tseem ceeb ntawm L, M, F, cov ntaub ntawv tus nqi, sampling moos, txuas moos, thiab SYSREF zaus.

Table 5. Qhov tshwm sim rau Cov Kev Xeem SHA.1, SHA.2, EMBA.1, EMBA.2, EMBA.3, TL.1, thiab TL.2

Tsis muaj.	L	M	F	S	HD	E	N	NP	ADC SampNtau zaus (MHz)	FPGA Ntaus Clock (MHz)	FPGA Ncej moos (MHz)	FPGA Link moos (MHz)	Txoj kab uas hla (Gbps)	Kev tshwm sim
1	8	4	1	1	0	1	16	16	3000.00	375.00	375.00	375.00	24.75	Hla

Test Result Comments
Nyob rau hauv txhua rooj plaub, RX JESD204C Intel FPGA IP ua tiav txoj kev sib koom ua ke ntawm cov header alignment, txuas ntxiv ntau qhov kev sib tw, thiab txog thaum cov neeg siv cov ntaub ntawv theem.
Tsis muaj cov ntaub ntawv qhov teeb meem kev ncaj ncees raug soj ntsuam los ntawm Ramp thiab PRBS checker rau JESD configurations npog tag nrho lub cev txoj kab, kuj tsis muaj cyclic redundancy check (CRC) thiab hais kom ua parity yuam kev.
Thaum qee lub voj voog fais fab, txoj kab deskew yuam kev yuav tshwm sim nrog cov kev teeb tsa tsis raug. Txhawm rau zam qhov kev ua yuam kev no, LEMC offset qhov tseem ceeb yuav tsum tau programmed lossis koj tuaj yeem ua qhov no nrog cov txheej txheem calibration cheb. Yog xav paub ntxiv txog cov txiaj ntsig raug cai ntawm LEMC offset, xa mus rau RBD Tuning Mechanism hauv F-tile JESD204C IP Tus Neeg Siv Qhia.

Cov ntaub ntawv ntsig txog
RBD Tuning Mechanism

Cov ntsiab lus
Daim ntawv tshaj tawm no qhia txog kev siv tau ntawm JESD204C Intel FPGA IP thiab PHY hluav taws xob cuam tshuam nrog AD9081/9082 (R2 Silicon) ntaus ntawv mus txog 24.75 Gbps rau ADC. Kev teeb tsa tiav thiab kev teeb tsa kho vajtse tau pom tias muaj kev ntseeg siab hauv kev sib cuam tshuam thiab kev ua haujlwm ntawm ob lub cuab yeej.

Cov Ntaub Ntawv Hloov Kho Keeb Kwm rau AN 927: JESD204C Intel FPGA IP thiab ADI AD9081 MxFE * ADC Interoperability Report rau Intel Agilex F-Tile Devices

Cov ntaub ntawv Version	Hloov
2022.04.25	Kev tso tawm thawj zaug.

AN 876: JESD204C Intel® FPGA IP thiab ADI AD9081 MxFE* ADC Interoperability Report rau Intel® Agilex® F-Tile Devices

Cov ntaub ntawv / Cov ntaub ntawv

Intel JESD204C Intel FPGA IP thiab ADI AD9081 MxFE ADC Interoperability Report [ua pdf] Cov neeg siv phau ntawv qhia
JESD204C Intel FPGA IP thiab ADI AD9081 MxFE ADC Interoperability Report, JESD204C, Intel FPGA IP thiab ADI AD9081 MxFE ADC Interoperability Report

Cov ntaub ntawv

Cov neeg siv phau ntawv