JESD204C Intel FPGA IP a me ADI AD9081 MxFE ADC Interoperability Hōʻike alakaʻi alakaʻi.

ʻIkepili huna

1 JESD204C Intel FPGA IP a me ADI AD9081 MxFE ADC Interoperability Report

2 ʻIke Huahana

3 Nā ʻōlelo hoʻohana huahana

4 JESD204C Intel® FPGA IP a me ADI AD9081 MxFE* ADC Interoperability Report no Intel® Agilex™ F-tile Device

4.1 Hōʻike Pūnaewele

5 Palapala / Punawai

5.1 Nā kuhikuhi

JESD204C Intel FPGA IP a me ADI AD9081 MxFE ADC Interoperability Report

ʻIke Huahana

ʻO ka huahana i ʻōlelo ʻia ma ka manual mea hoʻohana ʻo JESD204C Intel FPGA IP. He ʻāpana ʻenehana ia i hoʻohana pū ʻia me ka Intel Agilex I-Series F-Tile Demo Board a me ka ADI AD9081-FMCA-EBZ EVM. Hoʻomaka koke ʻia ka IP ma ke ʻano Duplex akā hoʻohana wale ʻia ke ala hoʻokipa. Hoʻopuka ia i kahi uaki loulou 375 MHz a me kahi uaki kiʻi 375 MHz. Hōʻike ʻia ka hoʻonohonoho ʻenehana no ka hoʻāʻo interoperability ADC ma ke Kiʻi 1. Pono ka IP e hāʻawi ʻia ʻo SYSREF e ka mea hana uaki e loaʻa ai ka uaki hāmeʻa JESD204C Intel FPGA IP.

Nā ʻōlelo hoʻohana huahana

Hoʻonohonoho lako lako
No ka hoʻonohonoho ʻana i ka hāmeʻa no ka hoʻohana ʻana i ka JESD204C Intel FPGA IP, e hahai i kēia mau ʻanuʻu:

Hoʻohui i ka ADI AD9081-FMCA-EBZ EVM i ka mea hoʻohui FMC+ o ka Intel Agilex I-Series F-Tile Demo Board.
E hōʻoia i ka hāʻawi ʻia ʻana o ka hōʻailona SYSREF e ka mea hana uaki e hoʻopuka ana i ka uaki hāmeʻa JESD204C Intel FPGA IP.

Hōʻike Pūnaewele
Hōʻike ke kiʻikuhi pae ʻōnaehana i ka pili ʻana o nā modula like ʻole i kēia hoʻolālā. Loaʻa iā ia ka Intel Agilex-I F-tile Demo Board, Intel Agilex F-tile Device, Top-Level RTL, Platform Designer System, Pattern Generator, Pattern Checker, F-Tile JESD204C Duplex IP Core, a me nā wati a me nā pilina.

ʻO ke ʻano hana like ʻole
Layer Link Ikepili Loaʻa
Hoʻopili kēia wahi hoʻāʻo i nā hihia hoʻāʻo no ka sync header alignment (SHA) a me ka lōʻihi multiblock alignment (EMBA). Heluhelu ka JESD204C Intel FPGA IP i nā papa inoa mai ka papa loulou data i ka wā o ka hoʻāʻo, kākau iā lākou i ka log files, a hōʻoia iā lākou no ka hāʻawi ʻana i nā koina ma o nā palapala TCL.

JESD204C Intel® FPGA IP a me ADI AD9081 MxFE* ADC Interoperability Report no Intel® Agilex™ F-tile Device

ʻO ka JESD204C Intel® FPGA IP kahi kiʻekiʻe kiʻekiʻe kiʻekiʻe kiʻekiʻe-to-point serial interface intellectual property (IP).
Ua hoʻāʻo ʻia ka JESD204C Intel FPGA IP me nā mea hoʻololi analog-to-digital converter (ADC) i koho ʻia.
Hōʻike kēia hōʻike i ka interoperability o ka JESD204C Intel FPGA IP me ka AD9081 Mixed Signal Front End (MxFE*) evaluation module (EVM) mai Analog Devices Inc. (ADI). Hōʻike nā ʻāpana aʻe i ke ʻano o ka nānā ʻana i ka mīkini a me nā hopena hōʻike.

ʻIke pili
F-tile JESD204C Intel FPGA IP alakaʻi hoʻohana

Pono nā lako lako a me nā lako polokalamu
Pono ka ho'āʻo interoperability i kēia mau lako lako a me nā lako polokalamu: Hardware

Intel Agilex™ I-Series F-tile Demo Board (AGIB027R29A1E2VR0) me 12V mana hoʻololi.

Mea Hana Analog (ADI) AD9081 MxFE* EVM (AD9081-FMCA-EBZ, Rev C)
Papa Loiloi Skywork Si5345-D (Si5345-D-EVB)

SMA kāne a SMP kāne
SMP kāne a SMP kelepona

lako polokalamu

ʻO ka polokalamu polokalamu polokalamu Intel Quartus® Prime Pro Edition 21.4

Manaʻo AD9081_API 1.1.0 a i ʻole ka mea hou (no Linux, koi ʻia no ka hoʻonohonoho AD9081 EVM)

ʻIke pili

AD9081/AD9082 Hoʻolālā Pūnaehana Mea Hoʻohana
Skyworks Si5345-D Papa Hoʻonaʻauao Papa Hoʻohana

Hoʻonohonoho lako lako
Hoʻomaka koke ʻia ka JESD204C Intel FPGA IP ma ke ʻano Duplex akā hoʻohana wale ʻia ke ala hoʻokipa. No FCLK_MULP =1, WIDTH_MULP = 8, S = 1, hoʻopuka ka PLL kumu i ka uaki loulou 375 MHz a me ka uaki kiʻi 375 MHz.
Hoʻohana ʻia kahi Intel Agilex I-Series F-Tile Demo Board me ka ADI AD9081-FMCA-EBZ EVM e pili ana i ka mea hoʻohui FMC + o ka papa hoʻomohala. Hōʻike ʻia ka hoʻonohonoho ʻenehana no ka hoʻāʻo interoperability ADC ma ka helu Hardware Setup.- • Loaʻa i ka AD9081-FMCA-EBZ EVM ka mana mai Intel Agilex I-Series F-Tile Demo Board ma o ka mea hoʻohui FMC +.

Hāʻawi ʻia ka F-tile transceiver a me JESD204C Intel FPGA IP core PLL reference clock e Si5345-D-EVB ma o SMA a SMP cable. E hoʻonoho iā MUX_DIP_SW0 i ke kiʻekiʻe ma Agilex-I F-Tile Demo Board e hōʻoia i ka lawe ʻana o U22 iā CLKIN1 i hoʻopili ʻia i ke kaula SMP.

Hāʻawi ka Si5345-D-EVB i kahi uaki kuhikuhi i ka HMC7044 programmable clock generator i loaʻa i ka AD9081 EVM ma o SMP a SMP cable.
Hāʻawi ʻia ka uaki hoʻokele no JESD204C Intel FPGA IP core e Silicon Labs Si5332 programmable clock generator i loaʻa i ka Intel Agilex I-Series F-tile Demo Board.

Hāʻawi ka HMC7044 programmable clock generator i ka AD9081 device reference clock. ʻO ka loop-locked loop (PLL) i loaʻa i ka mea AD9081 e hoʻopuka i nā ADC i makemake ʻia.ampuaki ling mai ka uaki kuhikuhi.
No Subclass 1, hana ka HMC7044 clock generator i ka hōʻailona SYSREF no ka mea AD9081 a no ka JESD204C Intel FPGA IP ma o ka mea hoʻohui FMC+.

ʻAʻolete: Manaʻo ʻo Intel i ka SYSREF e hāʻawi ʻia e ka mea hana uaki e loaʻa ai ka uaki hāmeʻa JESD204C Intel FPGA IP.

Hōʻike Pūnaewele

Hōʻike ke kiʻikuhi pae ʻōnaehana i ka pili ʻana o nā modula like ʻole i kēia hoʻolālā.

Kiʻi 2. Kiʻi Pūnaehana

Nā memo:

ʻO M ka helu o nā mea hoʻololi.
ʻO S ka helu o nā s i hoʻouna ʻiaamples no ka mea hoʻololi no ke kiʻi.
ʻO WIDTH_MULP ka mea hoʻonui ākea ʻikepili ma waena o ka papa noi a me ka papa lawe.
ʻO N ka helu o nā ʻāpana hoʻololi i kēlā me kēia mea hoʻololi.
ʻO CS ka helu o nā ʻāpana mana no kēlā me kēia hoʻololi ʻanaamples.

Ma kēia hoʻonohonoho, no example L = 8, M = 4, a me F = 1, ʻo ka helu ʻikepili o nā ala transceiver he 24.75 Gbps.
Hoʻopuka ka Si5332 OUT1 i ka uaki 100 MHz i mgmt_clk. Hoʻopuka ʻo Si5345-D-EVB i ʻelua mau alapine uaki, 375 MHz a me 100 MHz. Hāʻawi ʻia ka 375 MHz i ka multiplexer i hoʻopili ʻia i ka Intel Agilex I-Series F-tile Demo Board ma o ke awa J19 SMA. ʻO ka uaki hoʻopuka o ka multiplexer i hoʻokomo ʻia e alakaʻi i ka uaki kuhikuhi F-tile transceiver (refclk_xcvr) a me JESD204C Intel FPGA IP core PLL reference clock (refclk_core). Hoʻopili ʻia ʻo 100 MHz mai Si5345-D-EVB i ka HMC7044 programmable clock generator i loaʻa i ka AD9081 EVM ma ke ʻano he hoʻokomo uaki.
(EXT_HMCREF).

Hoʻopuka ka HCM7044 i kahi hōʻailona SYSREF manawa o 11.71875 MHz ma o ka FMC Connector.
Hoʻomaka koke ʻia ka JESD204C Intel FPGA IP ma ke ʻano Duplex akā hoʻohana wale ʻia ke ala hoʻokipa.

ʻO ke ʻano hana like ʻole
Hōʻike ka ʻāpana aʻe i nā pahuhopu hoʻāʻo, kaʻina hana, a me nā pae hoʻoholo. Hoʻopili ʻia ka hoʻāʻo i nā ʻāpana penei:

Papa loulou ʻikepili mea hoʻokipa
Papa lawe lawe

Layer Link Ikepili Loaʻa
Hoʻopili kēia wahi hoʻāʻo i nā hihia hoʻāʻo no ka sync header alignment (SHA) a me ka lōʻihi multiblock alignment (EMBA).
I ka hoʻomaka ʻana o ka loulou, ma hope o ka hoʻihoʻi ʻana o ka mea hoʻokipa, hoʻomaka ka JESD204C Intel FPGA IP e ʻimi i ke kahawai poʻomanaʻo sync i hoʻouna ʻia e ka hāmeʻa. Heluhelu ʻia nā papa inoa ma lalo mai ka papa loulou data i ka wā o ka hoʻāʻo, kākau ʻia i loko o ka log files, a hōʻoia ʻia no ka hele ʻana i nā pae hoʻohālike ma o nā palapala TCL.

ʻIke pili
F-tile JESD204C Intel FPGA IP alakaʻi hoʻohana

Hoʻopololei i ke poʻo (SHA)
Papa 1. Sync Header Alignment Test Cases

Ka Hoao Hoao	Pahuhopu	wehewehe	Koina Holo
SHA.1	E nānā inā hoʻokō ʻia ka Sync Header Lock ma hope o ka pau ʻana o ke kaʻina hoʻonohonoho.	Heluhelu ʻia nā hōʻailona mai nā papa inoa. Heluhelu ʻia ʻo CDR_Lock mai ka papa inoa rx_status3 (0x8C). Heluhelu ʻia ʻo SH_Locked mai ka papa inoa rx_status4 (0x90). Heluhelu ʻia ka jrx_sh_err_status mai ka papa inoa rx_err_status (0x60).	Pono e hōʻoia ʻia ʻo CDR_Lock a me SH_LOCK i ke kiʻekiʻe e like me ka helu o nā alahele. jrx_sh_err_status pono Ke nānā nei nā māla bit ma jrx_sh_err_status no sh_unlock_err, rx_gb_overflow_err, rx_gb_underflow_err, invalid_sync_header, src_rx_alarm, syspll_lock_err, a me cdr_locked_err.
SHA.2	E nānā i ke kūlana Sync Header Lock ma hope o ka loaʻa ʻana o ka laka poʻomanaʻo sync (a i ʻole i ka wā o ka Extended Multi-Block Alignment phase) a paʻa.	Heluhelu ʻia ka invalid_sync_header no ke kūlana laka Sync Header mai ka papa inoa (0x60[8]).	ʻO ke kūlana invalid_sync_header he 0.

Hoʻopaʻa ʻia ʻo Multiblock Alignment (EMBA)

Papa 2. Nā hihia ho'āʻo hoʻohālikelike Multiblock

Ka Hoao Hoao		Pahuhopu		wehewehe		Koina Holo
EMBA.1		E nānā inā hoʻopaʻa ʻia ka Lock Multiblock Extended ma hope o ka ʻōlelo ʻana o Sync Header Lock.		Heluhelu ʻia nā hōʻailona ma nā papa inoa.		Pono ka waiwai EMB_Locked_1 me 1 e pili ana i kēlā me kēia alahele. Pono ʻo EMB_Lock_err he 0.

	Ka Hoao Hoao		Pahuhopu		wehewehe		Koina Holo
					Heluhelu ʻia ʻo EMB_Locked_1 mai ka papa inoa rx_status5 (0x94). Heluhelu ʻia ʻo EMB_Lock_err mai ka papa inoa rx_err_status (0x60[19]).
	EMBA.2		E nānā inā paʻa ke kūlana Laka Multiblock (ma hope o ka laka multiblock lōʻihi a i ʻole a hiki i ka hoʻokuʻu ʻia ʻana o ka pahu elastic) me ka multiblock ʻole.		Heluhelu ʻia ka invalid_eomb_eoemb mai ka papa inoa rx_err_status (0x60[10:9]).		invalid_eomb_eoemb he “00”.
	EMBA.3		E nānā i ka hoʻonohonoho ʻana o ke ala.		Heluhelu ʻia kēia mau waiwai mai nā papa inoa. Heluhelu ʻia ka elastic_buf_over_flow mai ka papa inoa rx_err_status (0x60[20]). Heluhelu ʻia ka elastic_buf_full mai ka papa inoa rx_status6 (0x98).		ʻO ka elastic_buf_over_flow he 0. Pono ka waiwai elastic_buf_full me 1 e pili ana i kēlā me kēia ala.

Layer Kaʻa Mea Loaʻa (TL)
No ka nānā ʻana i ka pono o ka ʻikepili o ke kahawai ʻikepili uku ma o ka mea hoʻokipa (RX) JESD204C Intel FPGA IP a me ka pae lawe, ua hoʻonohonoho ʻia ka ADC i ramp/ ʻano hoʻāʻo PRBS. Hoʻonohonoho pū ʻia ka ADC e hana me ka hoʻonohonoho like e like me ka JESD204C Intel FPGA IP. ʻO ka ramp/ ʻO ka mea nānā PRBS ma ka lole FPGA e nānā i ka ramp/PRBS ka pono ʻikepili no hoʻokahi minuke. ʻO ka RX JESD204C Intel FPGA IP kākau inoa rx_err e koho mau ʻia no ka waiwai ʻole no hoʻokahi minuke.
Hōʻike ka kiʻi ma lalo nei i ka hoʻonohonoho hoʻāʻo manaʻo no ka nānā pono ʻana i ka ʻikepili.

Kiʻi 3. Hōʻoia i ka pono o ka ʻikepili me Ramp/PRBS15 Nānā

Papa 3. Nā hihia ho'āʻo Layer Transport

Ka Hoao Hoao

Pahuhopu

wehewehe

Koina Holo

TL.1

E nānā i ka palapala palapala ʻāina o ka ʻikepili me ka ramp ʻano hoʻāʻo.

Ua hoʻonohonoho ʻia ka Data_mode iā Ramp_ke ano.

Heluhelu ʻia nā hōʻailona ma nā papa inoa.

Heluhelu ʻia ka crc_err mai ka rx_err_status (0x60[14]).
Heluhelu ʻia ka jrx_patchk_data_error mai ka papa inoa tst_err0.

Pono e haʻahaʻa ka crc_err e hala.
He haʻahaʻa ka jrx_patchk_data_error.

TL.2

E nānā i ka palapala palapala ʻāina o ka ʻikepili me ka hoʻohana ʻana i ke kumu hoʻāʻo PRBS15.

Ua hoʻonohonoho ʻia ka ʻikepili_mode i ka prbs_mode.

Heluhelu ʻia kēia mau waiwai mai nā papa inoa.

Heluhelu ʻia ka crc_err mai ka rx_err_status (0x60[14]).
Heluhelu ʻia ka jrx_patchk_data_error mai ka papa inoa tst_err0.

Pono e haʻahaʻa ka crc_err e hala.
He haʻahaʻa ka jrx_patchk_data_error.

JESD204C Intel FPGA IP a me ADC Configurations
Kākoʻo maoli ʻia nā ʻāpana JESD204C Intel FPGA IP (L, M, a me F) i kēia nānā ʻana i nā lako e ka mea AD9081. ʻO ka helu ʻikepili transceiver, sampling, a me nā ʻāpana JESD204C ʻē aʻe e pili ana i nā kūlana hana AD908D1.
Hoʻohana ʻia ka hoʻāʻo ʻana i ka ʻikepili i ka JESD204C Intel FPGA IP me kēia hoʻonohonoho hoʻonohonoho.

Hoʻonohonoho honua no nā hoʻonohonoho āpau:

E = 1

CF = 0
CS = 0
Papa haʻahaʻa = 1

FCLK_MULP = 1
WIDTH_MULP = 8
SH_CONFIG = CRC-12

FPGA Hoʻokele Uaki (MHz) = 100

Nā hopena hoʻāʻo
Aia ma ka papa ma lalo nei nā hopena kūpono a me kā lākou wehewehe ʻana.

Papa 4. Wehewehe Hua

Ka hopena	Wehewehe
HALA	Ua nānā ʻia ka Device Under Test (DUT) e hōʻike i ke ʻano conformant.
PASS me nā manaʻo	Ua ʻike ʻia ka DUT e hōʻike i ke ʻano conformant. Eia naʻe, ua hoʻokomo ʻia kahi wehewehe hou o ke kūlana (example: ma muli o nā palena manawa, ua hana ʻia kahi hapa o ka hoʻāʻo).

Ka hopena	Wehewehe
HAOLE	Ua ʻike ʻia ka DUT e hōʻike i ke ʻano like ʻole.
ʻŌlelo aʻo	Ua ʻike ʻia ka DUT e hōʻike i ke ʻano i ʻōlelo ʻole ʻia.
E nānā i nā manaʻo	Mai ka nānā ʻana, ʻaʻole hiki ke hoʻoholo ʻia kahi pā kūpono a hāʻule paha. Hoʻokomo ʻia kahi wehewehe hou o ke kūlana.

Hōʻike ka papa ma lalo nei i nā hopena no nā hihia hoʻāʻo SHA.1, SHA.2, EMBA.1, EMBA.2, EMBA.3, TL.1, a me TL.2 me nā waiwai o L, M, F, helu helu, sampuaki ling, uaki loulou, a me nā alapine SYSREF.

Papa 5. Ka hopena no nā hihia hoʻāʻo SHA.1, SHA.2, EMBA.1, EMBA.2, EMBA.3, TL.1, a me TL.2

ʻAʻole.	L	M	F	S	HD	E	N	NP	ADC Sampling Clock (MHz)	Uaki Mea Hana FPGA (MHz)	FPGA Uaki Kiʻi (MHz)	FPGA Uaki loulou (MHz)	Laki Alanui (Gbps)	Ka hopena
1	8	4	1	1	0	1	16	16	3000.00	375.00	375.00	375.00	24.75	Holo

Nā Manaʻo hopena hoʻāʻo
I kēlā me kēia hihia hoʻāʻo, hoʻokumu ʻia ka RX JESD204C Intel FPGA IP i ka alignment header sync, hoʻonui ʻia multiblock alignment, a hiki i ka pae ʻikepili mea hoʻohana.
ʻAʻole ʻike ʻia kahi pilikia pili pono ʻikepili e ka Ramp a me ka mea nānā PRBS no nā hoʻonohonoho JESD e uhi ana i nā ala kino a pau, ʻaʻole hoʻi i ʻike ʻia ka cyclic redundancy check (CRC) a me ke kauoha parity error.
I kekahi mau pōʻaiapuni mana, hiki ke ʻike ʻia ka hewa o ka lane deskew me nā hoʻonohonoho hoʻonohonoho. No ka pale ʻana i kēia kuhi hewa, pono e hoʻolālā ʻia nā koina offset LEMC a i ʻole hiki iā ʻoe ke hoʻokaʻawale i kēia me ke kaʻina hana calibration sweep. No ka ʻike hou aku e pili ana i nā waiwai kānāwai o LEMC offset, e nānā i ka RBD Tuning Mechanism ma F-tile JESD204C IP User Guide.

ʻIke pili
RBD Hoʻoponopono Mechanism

Hōʻuluʻulu manaʻo
Hōʻike kēia hōʻike i ka hōʻoia o ka JESD204C Intel FPGA IP a me PHY uila uila me ka AD9081/9082 (R2 Silicon) a hiki i 24.75 Gbps no ADC. Hōʻike ʻia ka hoʻonohonoho piha ʻana a me ka hoʻonohonoho ʻana i nā lako e hāʻawi i ka hilinaʻi i ka interoperability a me ka hana o nā mea ʻelua.

Moʻolelo Hoʻoponopono Hou no AN 927: JESD204C Intel FPGA IP a me ADI AD9081 MxFE* ADC Interoperability Report no Intel Agilex F-Tile Device

Palapala Palapala	Nā hoʻololi
2022.04.25	Hoʻokuʻu mua.

AN 876: JESD204C Intel® FPGA IP a me ADI AD9081 MxFE* ADC Interoperability Report no Intel® Agilex® F-Tile Device

Palapala / Punawai

intel JESD204C Intel FPGA IP a me ADI AD9081 MxFE ADC Interoperability Report [pdf] Ke alakaʻi hoʻohana
JESD204C Intel FPGA IP a me ADI AD9081 MxFE ADC Interoperability Report, JESD204C, Intel FPGA IP a me ADI AD9081 MxFE ADC Interoperability Report

Nā kuhikuhi

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