Intel UG-01155 IOPLL FPGA IP Core
Yakagadziridzwa Intel® Quartus® Prime Design Suite: 18.1
IOPLL Intel® FPGA IP Core User Guide
Iyo IOPLL Intel® FPGA IP musimboti inokutendera kuti ugadzirise marongero eIntel Arria® 10 uye Intel Cyclone® 10 GX I/O PLL.
IOPLL IP musimboti inotsigira zvinotevera maficha:
- Inotsigira matanhatu akasiyana ewachi mhinduro modhi: yakananga, yekunze mhinduro, yakajairwa, sosi inopindirana, zero kunonoka buffer, uye LVDS maitiro.
- Inogadzira masaini anosvika mapfumbamwe ekuburitsa masaini eIntel Arria 10 uye Intel CycloneM 10 GX zvishandiso.
- Chinja pakati pemareferensi wachi mbiri.
- Inotsigira iri padyo nePLL (adjpllin) yekuisa yekubatanidza neyekumusoro PLL muPLL cascading mode.
- Inogadzira Memory Initialization File (.mif) uye inobvumira PLL dynamicVreconfiguration.
- Inotsigira PLL dynamic phase shift.
Related Information
- Nhanganyaya kuIntel FPGA IP Cores
Inopa rumwe ruzivo nezve Intel FPGA IP cores uye parameter mupepeti. - Maitiro Okushandisa ari papeji 9
- Mawachi eKubuda ari papeji 10
- Reference Clock Switchover pane peji 10
- PLL-ku-PLL Inoputika pane peji 11
- IOPLL Intel FPGA IP Core Mushandisi Yekushandisa Archives pane peji 12
Inopa rondedzero yevashandisi madhairekitori ekare eIOPLL Intel FPGA IP musimboti.
Device Family Support
Iyo IOPLL IP musimboti inotsigira chete Intel Arria 10 uye Intel Cyclone 10 GX mudziyo mhuri.
IOPLL IP Core Parameters
Iyo IOPLL IP core parameter editor inoonekwa muchikamu chePLL cheIP Catalog.
| Parameter | Kukosha Kwemutemo | Tsanangudzo |
| Mudziyo Mhuri | Intel Arria 10, Intel
Cyclone 10 GX |
Inotsanangura mhuri yemudziyo. |
| Chikamu | — | Inotsanangura mudziyo wakanangwa. |
| Speed Giredhi | — | Inotsanangura kasidhi yegiredhi yechinhu chakanangana. |
| PLL Mode | Integer-N PLL | Inotsanangura maitiro anoshandiswa kuIOPLL IP core. Kusarudzwa kwepamutemo chete ndiko Integer-N PLL. Kana iwe uchida chikamu chePLL, unofanirwa kushandisa iyo fPLL Intel Arria 10/Cyclone 10 FPGA IP musimboti. |
| Reference Clock Frequency | — | Inodoma frequency yekuisa yewachi yekupinza, refclk, muMHz. Iko kukosha kwekutanga ndiko 100.0 MHz. Izvo zvishoma uye zvakanyanya kukosha zvinoenderana nemudziyo wakasarudzwa. |
| Gonesa Yakakiyiwa Inobuda Port | Batidza kana Kudzima | Batidza kuti chiteshi chakakiiwa chigonese. |
| Gonesa zvimiro zvewachi inobuda | Batidza kana Kudzima | Batidza kuti uise emuviri PLL counter paramita pane kutsanangura yaunoda inobuda wachi frequency. |
| Operation Mode | zvakananga, mhinduro yekunze, normal, source synchronous, zero kunonoka buffer, kana lvds | Inotsanangura kushanda kwePLL. The default operation iri zvakananga
mode. • Kana ukasarudza iyo zvakananga mode, iyo PLL inoderedza kureba kwenzira yemhinduro kuti ibudise jitter duku kudarika pane PLL yakabuda.Iri mukati-wachi uye yekunze-wachi zvabuda zvePLL zvinoshandurwa nechikamu maererano nePLL clock input. Mune iyi modhi, iyo PLL haitsipire chero mawachi network. • Kana ukasarudza iyo normal modhi, iyo PLL inotsiva kunonoka kwemukati wachi network inoshandiswa nekubuda kwewachi. Kana iyo PLL ichishandiswawo kutyaira yekunze wachi yekubuda pini, inopindirana chikamu chekuchinja kwechiratidzo pane inobuda pini inoitika. • Kana ukasarudza iyo source synchronous modhi, kunonoka kwewachi kubva papini kuenda kuI/O rejisita yekupinza inofanana nekunonoka kwedata kubva papini kuenda kuI / O regisheni yekuisa. • Kana ukasarudza iyo mhinduro yekunze modhi, unofanira kubatanidza fbclk yekupinza port kune pini yekupinza. Iyo bhodhi-level yekubatanidza inofanirwa kubatanidza ese pini yekupinza uye yekunze wachi yekubuda port, fboutclk. Fbclk port inofambirana newachi yekupinda. • Kana ukasarudza iyo zero kunonoka buffer modhi, iyo PLL inofanirwa kudyisa yekunze wachi yekubuda pini uye kutsiva kunonoka kwakaunzwa nepini iyoyo. Chiratidzo chinocherechedzwa papini chinowiriraniswa kune wachi yekupinza. Iyo PLL wachi inobuda inobatanidza kune altbidir chiteshi uye inotyaira zdbfbclk sechiteshi chekubuda. Kana iyo PLL zvakare ichityaira yemukati wachi network, inoenderana chikamu chekuchinja kweiyo network inoitika. • Kana ukasarudza iyo lvds modhi, iyo yakafanana data uye wachi yekumisikidza hukama hwepini pane yemukati SERDES yekutora rejista inochengetwa. Iyo modhi inotsiva kunonoka kweLVDS wachi network, uye pakati pepini yedata uye pini yekuisa wachi kune SEDES yekutora rejista nzira. |
| Nhamba Yemawachi | 1–9 | Inotsanangura huwandu hwemawachi ekubuda anodiwa kune yega yega mudziyo muPLL dhizaini. Izvo zvakakumbirwa zvigadziriso zvekubuda kwe frequency, phase shift, uye duty cycle inoratidzwa zvichienderana nenhamba yewachi dzakasarudzwa. |
| Taurai VCO Frequency | Batidza kana Kudzima | Inokutendera kuti udzivise iyo VCO frequency kune yakataurwa kukosha. Izvi zvinobatsira kana uchigadzira PLL yeLVDS yekunze modhi, kana kana yakasarudzika chikamu chekuchinja nhanho saizi inodiwa. |
| akaenderera… | ||
| Parameter | Kukosha Kwemutemo | Tsanangudzo |
| VCO Frequency (1) | — | • Rini Gonesa zvimiro zvewachi inobuda inobatidzwa- inoratidza iyo VCO frequency zvichienderana nehunhu hwe Reference Clock Frequency, Multiply Factor (M-Counter),uye Divide Factor (N-Counter).
• Rini Gonesa zvimiro zvewachi inobuda yakadzimwa- inokutendera kuti utaure kukosha kwakakumbirwa kweiyo VCO frequency. Iko kukosha kwekutanga ndiko 600.0 MHz. |
| Ipa wachi yepasi rose zita | Batidza kana Kudzima | Inokutendera kuti utumidze zita rewachi yekubuda. |
| Zita reClock | — | Zita remushandisi wachi yeSynopsis Design Constraints (SDC). |
| Desired Frequency | — | Inotsanangura mafambisirwo ewachi yeinobuda pawachi inobuda, outclk[], muMHz. Iko kukosha kwekutanga ndiko 100.0 MHz. Izvo zvishoma uye zvakanyanya kukosha zvinoenderana nemudziyo wakashandiswa. Iyo PLL inongoverenga manhamba munzvimbo nhanhatu dzekutanga. |
| Actual Frequency | — | Inokutendera kuti usarudze iyo chaiyo yekubuda wachi frequency kubva pane runyorwa rweanogoneka mafrequency. The default value ndiyo iri padyo inogoneka frequency kune inodiwa frequency. |
| Phase Shift zvikamu | ps or madhigirii | Inotsanangudza chikamu chekuchinja chikamu cheiyo inoenderana inobuda wachi port,
outclk[], mu picoseconds (ps) kana madhigirii. |
| Inodiwa Phase Shift | — | Inotsanangura kukosha kwakumbirwa kwechikamu chekuchinja. Iko kukosha kwekutanga ndiko
0 p. |
| Actual Phase Shift | — | Inokutendera kuti usarudze iyo chaiyo chikamu chekuchinja kubva pane rondedzero inogoneka yechikamu chekuchinja kukosha. Iko kukosha kwekutanga ndiyo iri padhuze inogoneka yekuchinja kune inodiwa chikamu shanduko. |
| Inodiwa Duty Cycle | 0.0–100.0 | Inotsanangura kukosha kwakumbirwa kweduty cycle. Iko kukosha kwekutanga ndiko
50.0%. |
| Actual Duty Cycle | — | Inokutendera kuti usarudze iyo chaiyo yebasa kutenderera kubva pane rondedzero inogoneka yebasa cycle values. Iko kukosha kwekutanga ndiyo yepedyo inogoneka yebasa kutenderera kune inodiwa duty cycle. |
| Multiply Factor (M-Counter)
(2) |
4–511 | Inotsanangura huwandu hweM-counter.
Iyo yepamutemo mhando yeM counter ndeye 4-511. Nekudaro, zvirambidzo pane hushoma pamutemo PFD frequency uye yakanyanya pamutemo VCO frequency inorambidza inoshanda M counter renji kusvika 4-160. |
| Divide Factor (N-Counter) (2) | 1–511 | Inodoma divide factor yeN-counter.
Mutsara wepamutemo weN counter ndeye 1-511. Nekudaro, zvirambidzo pahushoma hwemutemo PFD frequency inodzikamisa hunoshanda huwandu hweN counter kusvika 1-80. |
| Divide Factor (C-Counter) (2) | 1–511 | Inotsanangura chikamu chekuparadzanisa chewachi yekubuda (C-counter). |
- Iyi parameter inongowanikwa chete kana Kugonesa kwemuviri kuburitsa ma parameter kwakadzimwa.
- Iyi parameter inongowanikwa chete kana Kugonesa muviri kuburitsa ma paramita akabatidzwa.
IOPLL IP Core Parameters - Settings Tab
Tafura 2. IOPLL IP Core Parameters - Settings Tab
| Parameter | Kukosha Kwemutemo | Tsanangudzo |
| PLL Bandwidth Preset | Low, Pakati, kana High | Inotsanangura iyo PLL bandwidth preset kuseta. Sarudzo yakasarudzika ndeye
Low. |
| PLL Auto Reset | Batidza kana Kudzima | Otomatiki gadzirisa iyo PLL pakurasikirwa kwekiyi. |
| Gadzira yechipiri yekuisa clk 'refclk1' | Batidza kana Kudzima | Batidza kuti upe wachi yekudzosera yakanamatira kuPLL yako iyo inogona kushandura neyako yekutanga referensi wachi. |
| Yechipiri Reference Clock Frequency | — | Inosarudza frequency yechiratidzo chechipiri chewachi. Iko kukosha kwekutanga ndiko 100.0 MHz. Iko kushoma uye kukosha kwakanyanya kunoenderana nechishandiso chinoshandiswa. |
| Gadzira chiratidzo che'active_clk' kuratidza wachi yekupinda iri kushandiswa | Batidza kana Kudzima | Batidza kuti ugadzire activeclk kubuda. Iyo activeclk yakabuda inoratidza wachi yekuisa iyo iri kushandiswa nePLL. Chiratidzo chekubuda chakaderera chinoratidza refclk uye chiratidzo chekubuda chakakwira chinoratidza refclk1. |
| Gadzira chiratidzo che'clkbad' chewachi yega yega yekupinza | Batidza kana Kudzima | Batidza kuti ugadzire zviviri clkbad zvinobuda, imwe yewachi yega yega yekupinza. Chiratidzo chekubuda chakaderera chinoratidza wachi iri kushanda uye chiratidzo chekubuda chakakwira chinoratidza wachi haisi kushanda. |
| Switchover Mode | Automatic Switchover, Manual Switchover, kana Otomatiki Switchover ine Manual Override | Inotsanangura switchover modhi yedhizaini yekushandisa. Iyo IP inotsigira matatu switchover modes:
• Kana ukasarudza iyo Automatic Switchover modhi, iyo PLL yedunhu inotarisisa iyo yakasarudzwa referensi wachi. Kana wachi imwe chete ikamira, dunhu rinobva rachinja richienda kuachi yekuchengetedza mumawachi mashoma uye rinogadzirisa masiginecha, clkbad uye activeclk. • Kana ukasarudza iyo Manual Switchover modhi, kana chiratidzo chekudzora, chinodzima, chinoshanduka kubva ku logic yakakwira kusvika kune logic yakaderera, uye inogara yakaderera kweanosvika matatu mawachi kutenderera, wachi yekuisa inochinja kune imwe wachi. Iyo extswitch inogona kugadzirwa kubva kuFPGA musimboti logic kana pini yekupinza. • Kana ukasarudza Otomatiki Switchover ine Manual Override modhi, kana iyo extswitch chiratidzo yakadzikira, inodarika iyo otomatiki switch basa. Chero bedzi extswitch ichiramba yakaderera, imwe switchover chiito yakavharwa. Kusarudza iyi modhi, ako maviri masosi ewachi anofanira kunge achimhanya uye kuwanda kwewachi mbiri hakugone kusiyana neinopfuura makumi maviri%. Kana mawachi ese ari maviri asiri pama frequency akafanana, asi mutsauko wenguva uri mukati me20%, wachi yekuona kurasikirwa kwewachi inogona kuona wachi yakarasika. Iyo PLL inowanzodonha kunze kwekiyi mushure meiyo PLL wachi yekuisa switchover uye inoda nguva yekukiya zvakare. |
| Switchover Kunonoka | 0–7 | Inowedzera huwandu hwakati hwekutenderera kunonoka kune switchover process. Iko kukosha kweiyo 0. |
| Kuwanikwa kuPLL LVDS_CLK/ LOADEN yekubuda chiteshi | Yakaremara, Bvisa LVDS_CLK/ LOADEN 0, kana
Bvisa LVDS_CLK/ RODZERA 0 & 1 |
Sarudza Gonesa LVDS_CLK/LOADEN 0 or Gonesa LVDS_CLK/ LOADEN 0 & 1 kugonesa iyo PLL lvds_clk kana kurodha inobuda chiteshi. Inogonesa iyi parameter kana PLL ichidyisa LVDS SERDES block nekunze PLL.
Paunenge uchishandisa I/O PLL outclk ports ine LVDS ports, outclk[0..3] inoshandiswa lvds_clk[0,1] uye loaden [0,1] ports, outclk4 inogona kushandiswa kune coreclk ports. |
| Gonesa kupinda kune iyo PLL DPA yekubuda port | Batidza kana Kudzima | Batidza kuti ugone kugonesa iyo PLL DPA yekuburitsa port. |
| akaenderera… | ||
| Parameter | Kukosha Kwemutemo | Tsanangudzo |
| Gonesa kupinda kuPLL yekunze wachi inobuda pachiteshi | Batidza kana Kudzima | Batidza kugonesa iyo PLL yekunze wachi yekuburitsa port. |
| Inotsanangura kuti ndeipi outclk ichashandiswa se extclk_out[0] sosi | C0 – C8 | Inotsanangura iyo outclk port ichashandiswa se extclk_out[0] sosi. |
| Inotsanangura kuti ndeipi outclk ichashandiswa se extclk_out[1] sosi | C0 – C8 | Inotsanangura iyo outclk port ichashandiswa se extclk_out[1] sosi. |
Cascading Tab
Tafura 3. IOPLL IP Core Parameters - Cascading Tab3
| Parameter | Kukosha Kwemutemo | Tsanangudzo |
| Gadzira chiratidzo che 'cascade out' kuti ubatanidze nePLL yakadzika | Batidza kana Kudzima | Batidza kuti ugadzire iyo cascade_out port, inoratidza kuti iyi PLL ndiyo sosi uye inobatana nenzvimbo (yakadzika) PLL. |
| Inotsanangura kuti ndeipi outclk ichashandiswa secascading source | 0–8 | Inotsanangura iyo cascading source. |
| Gadzira chiratidzo che adjpllin kana cclk kuti ubatanidze nePLL iri kumusoro | Batidza kana Kudzima | Batidza kuti ugadzire chiteshi chekuisa, izvo zvinoratidza kuti iyi PLL inzvimbo uye inobatana neyekunobva (kumusoro) PLL. |
Dynamic Reconfiguration Tab
Tafura 4. IOPLL IP Core Parameters - Dynamic Reconfiguration Tab
| Parameter | Kukosha Kwemutemo | Tsanangudzo |
| Gonesa dynamic reconfiguration yePLL | Batidza kana Kudzima | Batidza iyo inogonesa kugadziridzwa kwesimba kweiyi PLL (pamwe chete nePLL Reconfig Intel FPGA IP musimboti). |
| Bvumira mukana kune dynamic phase shift ports | Batidza kana Kudzima | Batidza iyo inogonesa iyo dynamic phase shift interface nePLL. |
| MIF Generation Sarudzo (3) | Gadzira Mutsva MIF File, Wedzera Configuration kune Iripo MIF File,uye Gadzira MIF File panguva IP Generation | Zvimwe gadzira itsva .mif file ine zvigadziriso zvazvino zveI/O PLL, kana wedzera gadziriro iyi kune iripo .mif file. Unogona kushandisa iyi .mif file panguva yekuchinjazve kugadzirisa zvakare I / O PLL kune yayo yazvino marongero. |
| Nzira yeNew MIF file (4) | — | Pinda nzvimbo uye file zita idzva .mif file kugadzirwa. |
| Nzira yeMIF Iripo file (5) | — | Pinda nzvimbo uye file zita riripo .mif file unoda kuwedzera. |
| akaenderera… | ||
- Iyi parameter inowanikwa chete kana Bvumira dynamic reconfiguration yePLL yakabatidzwa.
- Iyi parameter inowanikwa chete kana Gadzira Nyowani MIF File inosarudzwa seMIF Generation
Option.Parameter Kukosha Kwemutemo Tsanangudzo Gonesa Dynamic Phase Shift yeMIF Kutenderera (3) Batidza kana Kudzima Batidza kuchengetedza dynamic phase shift zvivakwa zvePLL reconfiguration. DPS Counter Sarudzo (6) C0–C8, Zvese C, or M
Inosarudza counter kuti iite dynamic phase shift. M ndiyo kaunda yemhinduro uye C ndiyo inoverengera post-scale counters. Nhamba yeDynamic Phase Shifts (6) 1–7 Inosarudza nhamba yekuwedzera kwechikamu. Saizi yeimwe chikamu chekuchinja kuwedzera yakaenzana ne1/8 yenguva yeVCO. Iko kukosha kwekutanga ndiko 1. Dynamic Phase Shift Direction (6) Positive or Negative
Inosarudza iyo inoshanduka chikamu chekuchinja nzira yekuchengeta muPLL MIF. - Iyi parameter inowanikwa chete kana Wedzera Configuration kune Iripo MIF File inosarudzwa seMIF Generation Option
IOPLL IP Core Parameters - Yepamberi Parameters Tab
Tafura 5. IOPLL IP Core Parameters - Advanced Parameters Tab
| Parameter | Kukosha Kwemutemo | Tsanangudzo |
| Advanced Parameters | — | Inoratidza tafura yemuviri PLL marongero ayo anozoitwa zvichibva pane zvaunoisa. |
Tsanangudzo Yekushanda
- I/O PLL i frequency-control system inogadzira wachi yekubuda nekuzviwiriranisa kune wachi yekupinza. Iyo PLL inofananidza mutsauko wechikamu pakati pechiratidzo chekuisa uye chiratidzo chekubuda chevoltage-controlled oscillator (VCO) uye obva aita nhanho yekuwiriranisa kuchengetedza inogara chikamu chekona (kukiya) pane frequency yekupinza kana chiratidzo chechiratidzo. Iyo yekuwiriranisa kana isina kunaka mhinduro loop yeiyo system inomanikidza iyo PLL kuti ivharwe-chikamu-kukiyiwa.
- Unogona kumisikidza PLLs sema frequency anowedzera, divider, demodulators, tracking jenareta, kana wachi yekudzoreredza maseketi. Iwe unogona kushandisa maPLL kugadzira ma frequency akagadzikana, kudzoreredza masaini kubva kune ine ruzha nzira yekutaurirana, kana kugovera masaini masaini mukati mekugadzira kwako.
Zvivakwa zvekuvaka zvePLL
Iwo makuru mabhuraki eI/O PLL ndiwo dhizaini frequency detector (PFD), pombi yekuchaja, loop filter, VCO, uye zviverengero, senge mhinduro counter (M), pre-scale counter (N), uye post- zvikero zvechikero (C). Iyo PLL dhizaini inoenderana nechishandiso chaunoshandisa mukugadzira kwako.
Iyi parameter inowanikwa chete kana Gonesa Dynamic Phase Shift yeMIF Kutenderera yakabatidzwa.
Yakajairika I/O PLL Architecture
- Aya mazwi anotevera anowanzoshandiswa kutsanangura maitiro ePLL:
PLL yekuvhara nguva-inozivikanwawo sePLL yekutora nguva. PLL kukiya nguva inguva yekuti PLL iwane yainotarirwa frequency uye hukama hwechikamu mushure mesimba-kumusoro, mushure meyakarongwa yekubuda frequency shanduko, kana mushure mekugadzirisazve PLL. Ongorora: Simulation software haienzanise yechokwadi PLL yekuvhara nguva. Simulation inoratidza nguva yekukiya zvisingaite. Kune chaiyo yekukiya nguva yakatarwa, tarisa kune dhatabheti remudziyo. - PLL resolution-iyo shoma frequency increment kukosha kwePLL VCO. Huwandu hwemabhiti muM uye N zviverengero zvinotarisa kukosha kwePLL resolution.
- PLL sample rate-iyo FREF sampling frequency inodiwa kuita chikamu uye frequency kururamisa muPLL. Iye PLL sampmuyero uri fREF/N.
PLL Kiya
Iyo PLL kukiya inotsamira pane maviri ekuisa masaini muchikamu frequency detector. Iyo yekuvhara chiratidzo ndeye asynchronous kubuda kwePLLs. Huwandu hwematenderedzwa anodiwa kugedhe chiratidzo chekiyi zvinoenderana newachi yekupinda yePLL inovhara gated-lock circuitry. Govanisa iyo yakanyanya kukiyiwa nguva yePLL nenguva yePLL yekuisa wachi kuti uverenge huwandu hwemawashi anodiwa kugedhe chiratidzo chekiyi.
Operation Modes
Iyo IOPLL IP musimboti inotsigira matanhatu akasiyana ewachi mhinduro modhi. Imwe neimwe modhi inobvumira wachi kuwanda uye kupatsanura, chikamu chekuchinja, uye basa-kutenderera hurongwa.
Output Clocks
- Iyo IOPLL IP musimboti inogona kugadzira anosvika mapfumbamwe wachi yekuburitsa masaini. Iyo inogadzirwa wachi inobuda masiginecha inovhara pakati kana mabhuroko ekunze kunze kwepakati.
- Iwe unogona kushandisa iyo reset chiratidzo kuseta zvakare kukosha kwewachi ku0 uye kudzima iyo PLL yekubuda wachi.
- Wachi yega yega inobuda ine seti yezvirongwa zvakakumbirwa kwaunokwanisa kutsanangura kukosha kwaunoda kune inobuda frequency, phase shift, uye basa kutenderera. Iwo anodiwa marongero ndiwo marongero aunoda kuita mukugadzira kwako.
- Iwo chaiwo maitiro eiyo frequency, chikamu chekuchinja, uye basa kutenderera ndiwo ari padhuze marongero (yakanakisa fungidziro yeinodiwa marongero) anogona kuitwa muPLL dunhu.
Reference Clock Switchover
Iyo referensi wachi switchover chimiro inobvumira iyo PLL kuti ichinje pakati pemareferenzi ekuisa wachi. Shandisa ichi chimiro chewachi redundancy, kana yeaviri wachi domain application senge mune system. Iyo system inogona kubatidza wachi isingashande kana iyo yekutanga wachi ikamira kushanda.
Uchishandisa referensi wachi switchover chimiro, unogona kutsanangura frequency yewachi yechipiri yekuisa, uye sarudza modhi uye kunonoka kweiyo switchover.
Iyo yekuona kurasikirwa kwewachi uye referensi wachi switchover block ine anotevera mabasa:
- Inotarisisa mamiriro ewachi. Kana iyo wachi yereferensi ikatadza, wachi inochinja ichienda kune yekuisa yekuchengetedza wachi. Iyo wachi inogadziridza chimiro che clkbad uye activeclk masiginecha kunyevera chiitiko.
- Shandura wachi yereferensi nekudzoka pakati pemafrequency maviri akasiyana. Shandisa iyo extswitch siginecha kuti udzore nemaoko chinja chiito. Mushure mekunge switchover yaitika, iyo PLL inogona kurasikirwa nekiyi kwechinguva uye ichipfuura nepakati pekugadzirisa.
PLL-ku-PLL Cascading
Kana iwe uchikanda maPLL mukugadzira kwako, iyo sosi (kumusoro) PLL inofanirwa kunge ine yakaderera bandwidth kuseta, nepo kwainoenda (kuzasi) PLL kunofanirwa kunge kune yakakwirira bandwidth kuseta. Panguva yekudonha, kuburitswa kwesource PLL kunoshanda seyereferensi wachi (yekuisa) yenzvimbo yekuenda PLL. Iyo bandwidth zvigadziriso zveCascaded PLLs inofanira kunge yakasiyana. Kana iyo bandwidth marongero eiyo cascaded PLLs akafanana, maPLL akadhindwa anogona ampLify phase noise pane dzimwe frequencies.The adjpllin input clock source inoshandiswa pa inter-cascading between fracturable fractional PLLs.
Ports
Tafura 6. IOPLL IP Core Ports
| Parameter | Type | Condition | Tsanangudzo |
| refclk | Input | Zvinodiwa | Iyo referensi wachi sosi inotyaira iyo I/O PLL. |
| rst | Input | Zvinodiwa | Iyo asynchronous reset port kune yakabuda wachi. Dhiraivha ichi chinokwidibira kuti uise patsva mawachi ese anobuda kune kukosha kwe0. Unofanira kubatanidza chiteshi ichi kuchiratidzo chekudzora mushandisi. |
| fbclk | Input | Optional | Iyo yekunze yekuisa mhinduro port yeI/O PLL.
Iyo IOPLL IP musimboti inogadzira chiteshi ichi kana I/O PLL iri kushanda mune yekunze mhinduro modhi kana zero-kunonoka buffer modhi. Kuti upedze iyo loop yemhinduro, bhodhi-level yekubatanidza inofanirwa kubatanidza fbclk port uye yekunze wachi yekubuda port yeI/O PLL. |
| fboutclk | Output | Optional | Chiteshi chinodyisa fbclk chiteshi kuburikidza neyekutevedzera sedunhu.
Iyo fboutclk port inowanikwa chete kana iyo I/O PLL iri kunze kwemhinduro modhi. |
| zdbfbclk | Bidirectional | Optional | Iyo bidirectional port inobatanidza kune inic sedunhu. Chiteshi ichi chinofanirwa kubatana nepini yebidirectional inoiswa pane yakanaka mhinduro yakatsaurirwa pini yekubuda yeI/O PLL.
Iyo zdbfbclk port inowanikwa chete kana I/O PLL iri mu zero- kunonoka buffer mode. Kuti udzivise kutarisisa kwechiratidzo paunenge uchishandisa zero-kunonoka buffer modhi, usaise zviteshi zvebhodhi pane bidirectional I/O pini. |
| rakakiyiwa | Output | Optional | Iyo IOPLL IP musimboti inotyaira ichi chiteshi chakakwira kana PLL ikawana kukiya. Chiteshi chinoramba chakakwirira chero bedzi IOPLL yakavharwa. Iyo I/O PLL inotaura chiteshi chakakiyiwa apo zvikamu uye mafambiro ewachi yereferenzi uye wachi yemhinduro ndiyo |
| akaenderera… | |||
| Parameter | Type | Condition | Tsanangudzo |
| zvakafanana kana mukati chekiyi redunhu kushivirira. Kana musiyano uripo pakati pemasaini maviri ewachi inodarika kushivirira kwekiyi yekiyi, iyo I/O PLL inorasikirwa nekukiya. | |||
| refclk1 | Input | Optional | Chechipiri referensi wachi sosi inotyaira iyo I/O PLL yewachi switchover chimiro. |
| extswitch | Input | Optional | Rongedza iyo extswitch siginecha yakaderera (1'b0) kweinenge 3 clock cycles kuti iwe pachako uchinje wachi. |
| activeclk | Output | Optional | Chiratidzo chekuburitsa kuratidza kuti ndechipi chinongedzo wachi chinoshandiswa neI/O PLL. |
| clkbad | Output | Optional | Chiratidzo chekubuda chinoratidza chimiro chereferensi wachi sosi yakanaka kana yakaipa. |
| cascade_out | Output | Optional | Chiratidzo chekubuda chinodyisa muzasi I/O PLL. |
| adjpllin | Input | Optional | Chiratidzo chekupinza chinodyisa kubva kumusoro kwerukova I/O PLL. |
| outclk_[] | Output | Optional | Wachi yekuburitsa kubva kuI/O PLL. |
IOPLL Intel FPGA IP Core Mushandisi Yekushandisa Archives
Kana IP core vhezheni isina kunyorwa, gwara remushandisi rekare IP core version rinoshanda
| IP Core Version | User Guide |
| 17.0 | Altera I/O Phase-Locked Loop (Altera IOPLL) IP Core User Guide |
| 16.1 | Altera I/O Phase-Locked Loop (Altera IOPLL) IP Core User Guide |
| 16.0 | Altera I/O Phase-Locked Loop (Altera IOPLL) IP Core User Guide |
| 15.0 | Altera I/O Phase-Locked Loop (Altera IOPLL) IP Core User Guide |
Gwaro Revision Nhoroondo yeIOPLL Intel FPGA IP Core Mushandisi Guide
| Document Version | Intel Quartus® Prime Version | Kuchinja |
| 2019.06.24 | 18.1 | Yakagadziridza tsananguro yewachi yakatsaurwa yekupinda mu Yakajairika I/O PLL Architecture diagram. |
| 2019.01.03 | 18.1 | • Updated the Kusvika kuPLL LVDS_CLK/LOADEN yekubuda chiteshi
parameter mu IOPLL IP Core Parameters - Settings Tab table. • Yakagadziridza tsananguro yechiteshi chezdbfbclk mu IOPLL IP Core Ports table. |
| 2018.09.28 | 18.1 | • Yakagadzirisa tsananguro yeextswitch mu IOPLL IP Core Ports
table. • Kupazve mazita anotevera IP cores sekuenderana neIntel rebranding: - Yakachinja Altera IOPLL IP musimboti kuita IOPLL Intel FPGA IP musimboti. - Yakachinjwa Altera PLL Reconfig IP musimboti kuPLL Reconfig Intel FPGA IP musimboti. - Yakachinjwa Arria 10 FPLL IP musimboti kuita fPLL Intel Arria 10/Cyclone 10 FPGA IP musimboti. |
| Date | Version | Kuchinja |
| Chikumi 2017 | 2017.06.16 | • Yakawedzerwa tsigiro yeIntel Cyclone 10 GX zvishandiso.
• Yakadzorerwa zvakare seIntel. |
| Zvita 2016 | 2016.12.05 | Yakagadziridza tsananguro yechiteshi chekutanga cheiyo IP core. |
| Chikumi 2016 | 2016.06.23 | • Yakagadziridzwa IP Core Parameters - Settings Tab tafura.
- Yakagadziridza tsananguro yeManual Switchover uye otomatiki Switchover ine Manual Override paramita. Wachi switchover control siginecha inoshanda yakaderera. - Yakagadziridza tsananguro yeSwitchover Delay parameter. • Yakatsanangurwa M uye C zviverengero zveDPS Counter Selection parameter mu IP Core Parameters - Dynamic Reconfiguration Tab tafura. • Kuchinja zita rechiteshi chewachi kubva kuclkswitch kuenda kuextswitch muDhiyagiramu yeI/O PLL Architecture diagram. |
| Chivabvu 2016 | 2016.05.02 | Yakagadziridzwa IP Core Parameters - Dynamic Reconfiguration Tab tafura. |
| Chivabvu 2015 | 2015.05.04 | Yakagadziridza tsananguro yeGonesa kupinda kuPLL LVDS_CLK/LOADEN inobuda pachiteshi paramende muIP Core Parameters - Settings Tab tafura. Yakawedzera chinongedzo kuSignal Interface Pakati peAltera IOPLL neAltera LVDS SERDES IP Cores tafura muI/O uye High Speed I/O muArria 10 Devices chitsauko. |
| Nyamavhuvhu 2014 | 2014.08.18 | Kusunungurwa kwekutanga. |
Zvinyorwa / Zvishandiso
 |
Intel UG-01155 IOPLL FPGA IP Core [pdf] Bhuku reMushandisi UG-01155 IOPLL FPGA IP Core, UG-01155, IOPLL FPGA IP Core, FPGA IP Core |
