intel UG-01155 IOPLL FPGA IP Core

Ihlaziywe i-Intel® Quartus® Prime Design Suite: 18.1

IOPLL Intel® FPGA IP Core User Guide

I-IOPLL Intel® FPGA IP core ikuvumela ukuba uqwalasele izicwangciso ze-Intel Arria® 10 kunye ne-Intel Cyclone® 10 GX I/O PLL.

Undoqo we-IOPLL IP uxhasa ezi mpawu zilandelayo:

• Ixhasa iindlela ezintandathu ezahlukeneyo zeempendulo zewotshi: ngokuthe ngqo, impendulo yangaphandle, eqhelekileyo, imvelaphi ye-synchronous, i-zero yokulibazisa i-buffer, kunye nemo ye-LVDS.
• Ivelisa ukuya kuthi ga kwiimpawu zewotshi ezilithoba zeIntel Arria 10 kunye neIntel CycloneM 10 GX izixhobo.
• Ukutshintsha phakathi kweewotshi ezimbini zereferensi yokufaka.
• Ixhasa i-PLL ekufutshane (adjpllin) igalelo lokudibanisa ne-PLL enyukayo kwimowudi yokuphosa ye-PLL.
• Ivelisa ukuqaliswa kweNkumbulo File (.mif) kwaye ivumela i-PLL dynamicVreconfiguration.
• Ixhasa inguqu yesigaba esiguqukayo se-PLL.

Ulwazi olunxulumeneyo

• Intshayelelo kwi-Intel FPGA IP Cores
  Ibonelela ngolwazi olungakumbi malunga ne-Intel FPGA IP cores kunye nomhleli weparameter.
• Iindlela zokuSebenza kwiphepha lesi-9
• Iiwotshi zemveliso kwiphepha le-10
• UTshintsho lwewotshi yeSingqinisiso kwiphepha le-10
• I-PLL-to-PLL iCascading kwiphepha le-11
• IOPLL Intel FPGA IP Core isiKhokelo soMsebenzisi ooVimba kwiphepha le-12

Ibonelela ngoluhlu lwezikhokelo zabasebenzisi kwiinguqulelo zangaphambili ze-IOPLL Intel FPGA IP engundoqo.

Isixhobo seNkxaso yoSapho

Undoqo we-IOPLL IP uxhasa kuphela i-Intel Arria 10 kunye ne-Intel Cyclone 10 kwiintsapho zesixhobo se-GX.

Iiparamitha ze-IOPLL IP Core

Umhleli weparameter ye-IOPLL IP engundoqo uvela kudidi lwe-PLL ye-IP Catalogue.

Ipharamitha	Ixabiso elisemthethweni	Inkcazo
Isixhobo Usapho	Intel Arria 10, Intel I-Cyclone 10 GX	Ixela usapho lwesixhobo.
Icandelo	—	Ixela isixhobo ekujoliswe kuso.
Isantya seBanga	—	Ixela inqanaba lesantya kwisixhobo ekujoliswe kuso.
Imo ye-PLL	Inani elipheleleyo-N I-PLL	Ixela indlela esetyenziswa kwi-IOPLL IP core. Ukhetho olusemthethweni kuphela Inani elipheleleyo-N PLL. Ukuba ufuna i-PLL yeqhezu, kufuneka usebenzise i-fPLL Intel Arria 10/Cyclone 10 FPGA IP core.
Reference Clock Frequency	—	Ikhankanya ungeniso lwekloko yewotshi, irefclk, kwiMHz. Ixabiso elimiselweyo ngu 100.0 MHz. Ubuncinci kunye nexabiso eliphezulu lixhomekeke kwisixhobo esikhethiweyo.
Yenza iZibuko zeZiphumo ezitshixiweyo	Vula okanye Cima	Layita ukuze uvule izibuko elitshixiweyo.
Yenza iiparamitha zewotshi yemveliso isebenze	Vula okanye Cima	Layita ukuze ufake iiparamitha zekhawunta ye-PLL endaweni yokuchaza ubuninzi bewotshi efunekayo.
Imo yokusebenza	ngqo, ingxelo yangaphandle, eqhelekileyo, umthombo ungqamaniso, Isikhuseli sokulibazisa esingu-zero, okanye lvds	Ixela ukusebenza kwe-PLL. Umsebenzi omiselweyo ngu ngqo indlela. • Ukuba ukhetha i ngqo imowudi, i-PLL inciphisa ubude bendlela yempendulo ukuvelisa i-jitter encinci kunokwenzeka kwi-PLL output.I-clock yangaphakathi kunye neziphumo zewotshi zangaphandle ze-PLL ziguqulwa ngesigaba ngokubhekiselele kwigalelo lewotshi ye-PLL. Kule modi, i-PLL ayibuyiseli naluphi na uthungelwano lwewotshi. • Ukuba ukhetha i eqhelekileyo Imowudi, i-PLL ibuyekeza ulibaziseko lwewotshi yangaphakathi yothungelwano olusetyenziswa yimveliso yewotshi. Ukuba i-PLL isetyenziselwa ukuqhuba i-pin yokuphuma kwewotshi yangaphandle, ukutshintshwa kwesigaba esihambelanayo somqondiso kwi-pin yemveliso kwenzeka. • Ukuba ukhetha i umthombo ungqamaniso imowudi, ukulibaziseka kwewotshi ukusuka kwi-pin ukuya kwirejista yegalelo ye-I/O ihambelana nokulibaziseka kwedatha ukusuka kwi-pin ukuya kwirejista yegalelo le-I/O. • Ukuba ukhetha i ingxelo yangaphandle Indlela, kufuneka uqhagamshele i-port ye-fbclk kwi-pin yongeniso. Uxhulumaniso lwenqanaba lebhodi kufuneka lidibanise zombini i-pin yokufaka kunye ne-port yangaphandle ye-clock output, fboutclk. Izibuko le-fbclk lilungelelaniswe newotshi yokufaka. • Ukuba ukhetha i Isikhuseli sokulibazisa esingu-zero Imowudi, i-PLL kufuneka yondle iphini yokuphuma kwewotshi yangaphandle kwaye ibuyekeze ulibaziseko olwenziwa yile pin. Umqondiso oqatshelwe kwiphini ungqamaniswa newotshi yokufaka. Imveliso yewotshi ye-PLL iqhagamshela kwizibuko le-altbidir kwaye iqhuba i-zdbfbclk njengendawo yokuphuma. Ukuba i-PLL iphinda iqhube inethiwekhi yewotshi yangaphakathi, ukutshintshwa kwesigaba esihambelanayo saloo nethiwekhi kwenzeka. • Ukuba ukhetha i lvds imowudi, idatha efanayo kunye nobudlelwane bexesha lewotshi kwizikhonkwane kwirejista yokubamba ye-SERDES yangaphakathi iyagcinwa. Imowudi ibuyekeza ulibaziseko kwinethiwekhi yewotshi ye-LVDS, naphakathi kwephini yedatha kunye nephini lokungena kwewotshi kwiindlela zerejista zokubamba zeSERDES.
Inani leeWotshi	1–9	Ixela inani leewotshi zemveliso ezifunekayo kwisixhobo ngasinye kuyilo lwePLL. Izicwangciso eziceliweyo zomaza ophumayo, ukutshintshwa kwesigaba, kunye nomjikelo womsebenzi ziboniswa ngokwenani leewotshi ezikhethiweyo.
Chaza i-VCO Frequency	Vula okanye Cima	Ikuvumela ukuba uthintele i-VCO rhoqo kwixabiso elikhankanyiweyo. Oku kuluncedo xa usenza i-PLL ye-LVDS imowudi yangaphandle, okanye ukuba ubungakanani benqanaba lokutshintsha kwenqanaba elithile liyafunwa.
iqhubekile...

Ipharamitha	Ixabiso elisemthethweni	Inkcazo
VCO Frequency (1)	—	• Nini Yenza iiparamitha zewotshi yemveliso isebenze ilayitiwe- ibonisa rhoqo VCO ngokusekelwe kumaxabiso Reference Clock Frequency, Izinto eziphindaphindayo (M-Counter), kwaye Yahlula iFactor (N-Counter). • Nini Yenza iiparamitha zewotshi yemveliso isebenze icinyiwe- ikuvumela ukuba uchaze ixabiso eliceliweyo le-VCO rhoqo. Ixabiso elimiselweyo ngu 600.0 MHz.
Nika igama lewotshi yehlabathi	Vula okanye Cima	Ikuvumela ukuba uthiye ngokutsha igama lewotshi yemveliso.
Igama Lekloko	—	Igama lomsebenzisi wewotshi yeSynopsis Design Constrants (SDC).
Ukuphindaphinda okufunwayo	—	Ikhankanya ikloko yekloko yemveliso ehambelanayo yezibuko zewotshi, outclk[], kwiMHz. Ixabiso elimiselweyo ngu 100.0 MHz. Ubuncinci kunye namaxabiso aphezulu axhomekeke kwisixhobo esisetyenzisiweyo. I-PLL ifunda kuphela amanani kwiindawo ezintandathu zokuqala zedesimali.
Okwenyani Ukuphindaphinda	—	Ikuvumela ukuba ukhethe esona siphumo sewotshi ephumayo kuluhlu lwamaza afumanekayo. Ixabiso elimiselweyo lelona xesha likufutshane elifikelelekayo kwifrikhwensi oyifunayo.
Iiyunithi zeSigaba Shift	ps or izidanga	Ixela iyunithi yokutshintsha kwenqanaba lezibuko lewotshi ehambelanayo, outclk[], kwi picoseconds (ps) okanye izidanga.
I-Shift yeSigaba esinqwenelwayo	—	Ixela ixabiso eliceliweyo lotshintsho lwesigaba. Ixabiso elimiselweyo ngu 0 ii-ps.
Olona tshintsho lweSigaba	—	Ikuvumela ukuba ukhethe eyona shift yesigaba ukusuka kuluhlu lwamaxabiso eshift yesigaba esiphunyelelwayo. Ixabiso elimiselweyo lolona tshintsho lusondeleyo lwesigaba olunokufezekiswa kwishifti yesigaba esifunwayo.
Umjikelo woMsebenzi ofunekayo	0.0–100.0	Ichaza ixabiso eliceliweyo lomjikelo womsebenzi. Ixabiso elimiselweyo ngu 50.0%.
Owena uMjikelo woMsebenzi	—	Ikuvumela ukuba ukhethe owona mjikelo womsebenzi kuluhlu lwamaxabiso afikelelekayo omjikelo. Ixabiso elimiselweyo ngowona mjikelo womsebenzi ukufutshane ofikelelekayo kumjikelo womsebenzi ofunekayo.
Izinto eziphindaphindayo (M-Counter) (2)	4–511	Ixela into yophindaphindo lweM-counter. Uluhlu olusemthethweni lwekhawunta ye-M yi-4-511. Nangona kunjalo, izithintelo kubuncinci befrikhwensi ye-PFD esemthethweni kunye nobuninzi be-VCO esemthethweni ithintela uluhlu olusebenzayo lwekhawuntara ye-M ukuya kwi-4-160.
Yahlula iFactor (N-Counter) (2)	1–511	Ixela ulwahlulo lwefektha ye-N-counter. Uluhlu olusemthethweni lwekhawunta ye-N yi-1-511. Nangona kunjalo, izithintelo kubuncinci befrikhwensi yePFD esemthethweni ithintela uluhlu olusebenzayo lwekhawunta ye-N ukuya kwi-1-80.
Ukwahlula iFactor (C-Counter) (2)	1–511	Ixela ulwahlulo lwewotshi yemveliso (C-counter).

1. Le parameter ifumaneka kuphela xa i-parameters yewotshi yemveliso yemveliso ivaliwe.
2. Le parameter ifumaneka kuphela xa i-parameters yewotshi yemveliso ebonakalayo ivuliwe.

I-IOPLL IP Core Parameters-Izicwangciso zeTab

Itheyibhile 2. I-IOPLL IP Core Parameters - Izicwangciso zeTab

Ipharamitha	Ixabiso elisemthethweni	Inkcazo
Ukusetwa kwangaphambili kwe-PLL Bandwidth	Phantsi, Phakathi, okanye Phezulu	Ikhankanya i-PLL bandwidth yokusetha kwangaphambili. Ukhetho olungagqibekanga lu Phantsi.
Ukuseta kwakhona okuzenzekelayo kwe-PLL	Vula okanye Cima	ngokuzenzekelayo uziseta kwakhona i-PLL ekulahlekeni kwesitshixo.
Yenza igalelo lesibini clk 'refclk1'	Vula okanye Cima	Layita ukubonelela ngewotshi yogcino encanyathiselwe kwi-PLL yakho enokutshintsha ngewotshi yakho yokuqala yereferensi.
Ikloko yesiBini yoReferensi yokuphindaphinda	—	Ikhetha ukuphindaphinda kophawu lwewotshi yesibini. Ixabiso elimiselweyo ngu 100.0 MHz. Ubuncinci kunye nexabiso eliphezulu lixhomekeke kwisixhobo esisetyenzisiweyo.
Yenza isignali ethi 'active_clk' ukubonisa ikloko yongeniso esebenzayo	Vula okanye Cima	Layita ukwenza imveliso ye-activeclk. Imveliso ye-activeclk ibonisa ikloko yokufaka esetyenziswa yi-PLL. Isignali yemveliso ephantsi ibonisa i-refclk kunye nophawu lwemveliso ephezulu ibonisa i-refclk1.
Yenza uphawu lwe 'clkbad' kwiwotshi nganye yegalelo	Vula okanye Cima	Layita ukwenza iziphumo ezimbini zeclkbad, enye kwiwotshi nganye yokufaka. Isignali yemveliso ephantsi ibonisa ukuba iwotshi iyasebenza kwaye umqondiso wemveliso uphezulu ubonisa ukuba iwotshi ayisebenzi.
Imowudi yoTshintsho	Ukutshintsha okuzenzekelayo, Ukutshintshwa kweManuwali, okanye Ukutshintshela ngokuzenzekela ngokuBhala ngokuBhalwa ngaphezulu	Ixela imowudi yokutshintsha kwisicelo soyilo. I-IP ixhasa iindlela ezintathu zokutshintsha: • Ukuba ukhetha i Ukutshintsha okuzenzekelayo Imowudi, i-PLL yesiphaluka ibeka iliso kwiwotshi ekhethiweyo yereferensi. Ukuba iwotshi enye iyema, isekethe itshintshela ngokuzenzekelayo kwiwotshi yogcino kwimijikelo yeewotshi ezimbalwa kwaye ihlaziya iimpawu zesimo, clkbad kunye ne activeclk. • Ukuba ukhetha i Ukutshintshwa kweManuwali Imowudi, xa isignali yolawulo, i-extwitch, itshintsha ukusuka kwi-logic ephezulu ukuya kwi-logic ephantsi, kwaye ihlala iphantsi ubuncinane imijikelo yeewotshi ezintathu, igalelo lewotshi litshintshela kwenye. I-extwitch ingenziwa kwi-FPGA core logic okanye i-pin yokufaka. • Ukuba ukhetha Ukutshintshela ngokuzenzekela ngokuBhala ngokuBhalwa ngaphezulu imowudi, xa isignali yokucima iphantsi, ibeka ngaphezulu umsebenzi wokutshintsha okuzenzekelayo. Logama nje i-extwitch ihleli isezantsi, intshukumo eyongezelelweyo yokutshintsha ivaliwe. Ukukhetha le mowudi, imithombo yewotshi yakho emibini kufuneka isebenze kwaye namaxesha eewotshi ezimbini awanakwahluka ngaphezulu kwe-20%. Ukuba zombini iiwotshi azikho kwifrikhwensi enye, kodwa umahluko wexesha lazo ungaphakathi kwe-20%, ibhloko yokufumanisa ilahleko yewotshi inokubona iwotshi elahlekileyo. I-PLL inokwenzeka ukuba iphume ngaphandle kwesitshixo emva kokutshintshwa kwewotshi ye-PLL kwaye idinga ixesha lokutshixa kwakhona.
Ukulibaziseka kweSwitchover	0–7	Yongeza inani elithile lokulibaziseka komjikelo kwinkqubo yokutshintsha. Ixabiso elimiselweyo ngu-0.
Ukufikelela kwi-PLL LVDS_CLK/ LOADEN izibuko lemveliso	Kukhubazekile, Vula i-LVDS_CLK/ LAWULA 0, okanye Vula i-LVDS_CLK/ LAPHA 0 & 1	Khetha Vula i-LVDS_CLK/LOADEN 0 or Vula i-LVDS_CLK/ LOADEN 0 & 1 ukwenza i-PLL lvds_clk okanye ukulayisha izibuko lemveliso. Yenza le parameter isebenze kwimeko apho i-PLL yondla ibhlokhi ye-LVDS SEDES nge-PLL yangaphandle. Xa usebenzisa i-I/O PLL outclk port kunye ne-LVDS ports, i-outclk [0..3] isetyenziselwa i-lvds_clk [0,1] kunye ne-loaden [0,1] izibuko, i-outclk4 ingasetyenziselwa i-coreclk port.
Yenza ufikelelo kwizibuko lemveliso ye-PLL DPA	Vula okanye Cima	Layita ukuze uvule izibuko lemveliso ye-PLL DPA.
iqhubekile...

Ipharamitha	Ixabiso elisemthethweni	Inkcazo
Yenza ufikelelo kwizibuko lewotshi yangaphandle yePLL	Vula okanye Cima	Layita ukwenza izibuko lemveliso yewotshi yangaphandle ye-PLL.
Ixela ukuba yeyiphi i-outclk eza kusetyenziswa njenge-extclk_out[0] umthombo	C0 – C8	Ikhankanya izibuko le outclk eliza kusetyenziswa njenge extclk_out[0] umthombo.
Ixela ukuba yeyiphi i-outclk eza kusetyenziswa njenge-extclk_out[1] umthombo	C0 – C8	Ikhankanya izibuko le outclk eliza kusetyenziswa njenge extclk_out[1] umthombo.

I-Cascading Tab

Itheyibhile 3. I-IOPLL IP Core Parameters - I-Cascading Tab3

Ipharamitha	Ixabiso elisemthethweni	Inkcazo
Yenza uphawu 'lokuphuma' ukuze udibanise ne-PLL esezantsi	Vula okanye Cima	Vula ukwenza i-cascade_out port, ebonisa ukuba le PLL ngumthombo kwaye idibanisa nendawo (ezantsi) PLL.
Ixela ukuba yeyiphi i-outclk eza kusetyenziswa njengomthombo we-cascading	0–8	Ikhankanya umthombo we-cascading.
Yenza isignali ye-adjpllin okanye ye-cclk ukudibanisa ne-PLL enyukayo	Vula okanye Cima	Vula ukwenza i-port yongeniso, ebonisa ukuba le PLL yindawo ekuyiwa kuyo kwaye idibanisa nomthombo (phezulu) PLL.

Uqwalaselo ngokutsha lweTab

Itheyibhile 4. I-IOPLL IP Core Parameters - Dynamic Reconfiguration Tab

Ipharamitha	Ixabiso elisemthethweni	Inkcazo
Yenza uqwalaselo ngokutsha oluguquguqukayo lwe PLL	Vula okanye Cima	Layita vumela uqwalaselo ngokutsha oluguquguqukayo lwale PLL (ngokudityaniswa ne PLL Reconfig Intel FPGA IP core).
Yenza ufikelelo kumazibuko okutshintsha kwesigaba esiguqukayo	Vula okanye Cima	Layita ujongano lotshintsho lwesigaba esiguqukayo kunye nePLL.
MIF Generation Option (3)	Veza I-MIF entsha File, Yongeza ubumbeko kwi-MIF ekhoyo File, kwaye Yenza i-MIF File ngexesha le-IP Generation	Okanye yenza entsha .mif file iqulathe uqwalaselo lwangoku lwe I/O PLL, okanye yongeza olu qwalaselo kwi .mif ekhoyo. file. Ungasebenzisa le .mif file ngexesha loqwalaselo ngokutsha oluguquguqukayo ukuqwalasela kwakhona i-I/O PLL kwizicwangciso zayo zangoku.
Indlela eya kwi-MIF entsha file (4)	—	Ngenisa indawo kwaye file igama le .mif entsha file ukudalwa.
Indlela eya kwi-MIF ekhoyo file (5)	—	Ngenisa indawo kwaye file igama le-.mif ekhoyo file ujonge ukongeza kwi.
iqhubekile...

1. Le parameter ifumaneka kuphela xa Vulela uqwalaselo oluguquguqukayo lwe PLL luvuliwe.
2. Le parameter ifumaneka kuphela xa uVelisa i-MIF eNtsha File ikhethwe njengeMIF Generation
   Ukhetho.

   Ipharamitha	Ixabiso elisemthethweni	Inkcazo
   Yenza iShift yeNqanaba eliDynamic ukulungiselela ukusasaza kwe-MIF (3)	Vula okanye Cima	Layita ukugcina iipropati zokutshintsha kwesigaba esiguqukayo kuqwalaselo ngokutsha lwe-PLL.
   UKhetho lwe-Counter ye-DPS (6)	C0–C8, Bonke C, or M	Ikhetha into yokubala ukuze ingene kwishifti yesigaba esitshintshayo. U-M yikhawuntara yempendulo kwaye u-C yikhawunta ye-post-scale.
   Inani leeShifts zeNqanaba eliNgqongileyo (6)	1–7	Ikhetha inani lokunyuswa kwesigaba sokutshintsha. Ubungakanani besigaba esisodwa sokunyuswa kwenguqu bulingana ne-1/8 yexesha le-VCO. Ixabiso elimiselweyo ngu 1.
   ISigaba esiGuquguqukayo soMkhomba-ndlela weShift (6)	Okuhle or Ibi	Imisela isalathiso sokutshintsha kwesigaba esitshintshayo ukuze sigcinwe kwi-PLL MIF.

3. Le parameter ifumaneka kuphela xa Yongeza uqwalaselo kwi-MIF ekhoyo File ikhethwe njengoKhetho lwesiZukulwana se-MIF

I-IOPLL IP Core Parameters - I-Tab yeeParamitha eziPhambili

Itheyibhile 5. I-IOPLL IP Core Parameters - Advanced Parameters Tab

Ipharamitha	Ixabiso elisemthethweni	Inkcazo
IiParameters eziPhezulu	—	Ibonisa itheyibhile yezicwangciso ze-PLL eza kuphunyezwa ngokusekelwe kwigalelo lakho.

Inkcazo esebenzayo

• I-I/O PLL yinkqubo yokulawula amaza omoya eyenza ikloko yemveliso ngokuzilungelelanisa newotshi yokufaka. I-PLL ithelekisa umahluko wesigaba phakathi kwesiginali yegalelo kunye nomqondiso wokuphuma kwevolthitagI-oscillator elawulwa yi-e-controlled (VCO) kwaye emva koko yenza ulungelelwaniso lwesigaba ukuze kugcinwe i-angle yesigaba esingaguqukiyo (isitshixo) kwi-frequency yegalelo okanye isignali yereferensi. Ungqamaniso okanye iluphu yengxelo engalunganga yesixokelelwano inyanzela i-PLL ukuba itshixiwe ngokwesigaba.
• Ungaqwalasela ii-PLL njengabaphindaphindi-ziphindaphindayo, abahluli, iidemodulators, iijenereyitha zokulandela umkhondo, okanye iisekethe zokubuyisela iwotshi. Unokusebenzisa ii-PLL ukuvelisa iifrikhwensi ezizinzileyo, ubuyise imiqondiso kwijelo lonxibelelwano elinengxolo, okanye usasaze imiqondiso yewotshi kulo lonke uyilo lwakho.

Iibhloko zokwakha zePLL

Iibhloko eziphambili ze-I/O PLL yi-phase frequency detector (PFD), impompo yentlawulo, isihluzi se-loop, i-VCO, kunye nezinto zokubala, ezifana ne-counter counter (M), i-pre-scale counter (N), kunye ne-post- izixhobo zokubala zesikali (C). Uyilo lwePLL luxhomekeke kwisixhobo osisebenzisayo kuyilo lwakho.

Le parameter ifumaneka kuphela xa kulayitiwe i-Fase Dynamic Phase Shift yokusasaza kwe-MIF.

Uyilo lwe-I/O PLL oluqhelekileyo

• La magama alandelayo aqhele ukusetyenziswa ukuchaza ukuziphatha kwe-PLL:
  Ixesha lokuvala i-PLL-ekwabizwa ngokuba lixesha lokufumana i-PLL. Ixesha lokutshixa i-PLL lixesha lokuba i-PLL ifumane i-frequency ekujoliswe kuyo kunye nobudlelwane besigaba emva kokunyuswa kwamandla, emva kokutshintsha okucwangcisiweyo okuphumayo, okanye emva kokusetha kwakhona kwe-PLL. Qaphela: Isoftware yokulinganisa ayibonisi ixesha lokwenyani lokutshixa i-PLL. Ukulinganisa kubonisa ixesha lokutshixa ngokukhawuleza ngokungekho ngqiqweni. Ngeenkcukacha ezichanekileyo zexesha lokutshixa, jonga kwidatha yedatha yesixhobo.
• Isisombululo se-PLL-elona xabiso lincinci lokunyuswa kwe-frequency ye-PLL VCO. Inani leebits kwiikhawunta ze-M kunye ne-N limisela ixabiso lesisombululo se-PLL.
• PLL sample rate-i FREF sampi-ling frequency efunekayo ukwenza isigaba kunye nokulungiswa rhoqo kwi-PLL. I-PLLampireyithi yi-fREF/N.

PLL Tshixo

Isitshixo se-PLL sixhomekeke kwiimpawu ezimbini zokungenisa kwi-disk frequency detector. Umqondiso wokutshixa yimveliso engahambelaniyo yee-PLLs. Inani lemijikelo efunekayo ukuze kungene umqondiso wokutshixa kuxhomekeke kwiwotshi ye-PLL evala i-gate-lock. Yahlula elona xesha liphezulu lokutshixa le-PLL ngexesha lewotshi yokufaka i-PLL ukubala inani lemijikelo yewotshi efunekayo kwisango lophawu lwesitshixo.

Iindlela zokuSebenza

Undoqo we-IOPLL IP uxhasa iindlela ezintandathu ezahlukeneyo zokuphendula iwotshi. Imowudi nganye ivumela ukuphindaphinda kwewotshi kunye nokwahlulahlula, ukutshintshwa kwesigaba, kunye neprogramu yomjikelo womsebenzi.

Iiwotshi zemveliso

• Undoqo we-IOPLL IP unokuvelisa ukuya kuthi ga kwiimpawu zewotshi ezilithoba. Iimpawu eziveliswayo zewotshi zivala undoqo okanye iibhloko zangaphandle ngaphandle kondoqo.
• Ungasebenzisa isignali yokusetha kwakhona ukuseta kwakhona ixabiso lewotshi yemveliso kwi-0 kwaye ukhubaze iiwotshi ze-PLL zemveliso.
• Ikloko nganye yemveliso ineseti yezicwangciso eziceliweyo apho ungakhankanya khona amaxabiso afunwayo okwenziwa rhoqo, ukutshintshwa kwesigaba, kunye nomjikelo womsebenzi. Useto olufunekayo luseto ofuna ukulusebenzisa kuyilo lwakho.
• Amaxabiso okwenene okuphindaphinda, ukutshintshwa kwesigaba, kunye nomjikelezo womsebenzi yizona zicwangciso ezikufutshane (ezona ziqikelelo ezifunwayo) ezinokuthi ziphunyezwe kwisekethe ye-PLL.

Ukutshintshwa kweClock yeReferensi

Indawo yokutshintsha iwotshi yereferensi ivumela i-PLL ukuba itshintshe phakathi kweewotshi ezimbini zokufaka ireferensi. Sebenzisa olu phawu ukungasebenzi kwewotshi, okanye usetyenziso lwethambeka yewotshi ezimbini njengakwinkqubo. Inkqubo inokuvula iwotshi engafunekiyo ukuba iwotshi yokuqala iyayeka ukusebenza.
Usebenzisa isiciko sokutshintsha iwotshi yereferensi, ungakhankanya ukuphindaphindeka kwewotshi yesibini yokufaka, kwaye ukhethe imo kunye nokulibaziseka kokutshintsha.

Ukufunyaniswa kwelahleko yewotshi kunye nebhlokhi yokutshintsha iwotshi inemisebenzi elandelayo:

• Ubeka iliso kwimo yewotshi yereferensi. Ukuba iwotshi yereferensi ayiphumelelanga, iwotshi iyazitshintshela kumthombo wongeniso wewotshi yogcino. Iwotshi ihlaziya ubume be-clkbad kunye neempawu ze-activeclk ukulumkisa isiganeko.
• Utshintsha iwotshi yereferensi emva naphambili phakathi kwezakhelo ezimbini ezahlukeneyo. Sebenzisa isignali yokucima ukulawula ngesandla isenzo sokutshintsha. Emva kokuba utshintshiselwano lwenzekile, i-PLL inokulahlekelwa itshixo okwethutyana kwaye idlule kwinkqubo yokubala.

I-PLL-to-PLL Cascading

Ukuba uphosa ii-PLL kuyilo lwakho, umthombo (phezulu) i-PLL kufuneka ibe ne-low-bandwidth setting, ngelixa indawo (ezantsi) i-PLL kufuneka ibe ne-high-bandwidth setting. Ngexesha le-Cascading, imveliso yomthombo we-PLL isebenza njengewotshi yereferensi (igalelo) yendawo ekuyiwa kuyo ye-PLL. Iisetingi ze-bandwidth ye-cascade PLLs kufuneka zahluke. Ukuba useto lwe-bandwidth ye-Cascaded PLLs ziyafana, i-Cascaded PLLs inakho ampI-lify phase ingxolo kumaza athile.Umthombo wewotshi ye-adjpllin isetyenziswa kwi-inter-cascade phakathi kwe-fracturable fractional PLLs.

Amazibuko

Itheyibhile 6. IOPLL IP Core Ports

Ipharamitha	Uhlobo	Imeko	Inkcazo
refclk	Igalelo	Kufuneka	Umthombo wewotshi yereferensi eqhuba i-I/O PLL.
kuqala	Igalelo	Kufuneka	Izibuko lokuseta kwakhona okungalungelelananga kwiiwotshi zemveliso. Qhuba eli zibuko liphezulu ukuseta kwakhona zonke iiwotshi zemveliso kwixabiso lika-0. Kufuneka uqhagamshele eli zibuko kuphawu lolawulo lomsebenzisi.
fbclk	Igalelo	Ukhetho	Ingxelo yongeniso yangaphandle yezibuko ye-I/O PLL. I-IOPLL IP core yenza eli zibuko xa i-I/O PLL isebenza kwimo yengxelo yangaphandle okanye imo yebuffer yokulibazisa. Ukugqiba i-loop yengxelo, uxhulumaniso lwenqanaba lebhodi kufuneka lidibanise i-port ye-fbclk kunye ne-port yangaphandle ye-clock ye-I / O PLL.
fboutclk	Isiphumo	Ukhetho	Izibuko elondla izibuko le-fbclk ngomjikelezo wokulingisa. I-port ye-fboutclk ifumaneka kuphela ukuba i-I/O PLL ikwimo yempendulo yangaphandle.
zdbfbclk	I-Bidirectional	Ukhetho	Izibuko elindlela-mbini elidityaniswe kumjikelezo wokulingisa. Eli zibuko kufuneka liqhagamshele kwisikhonkwane se-bidirectional esibekwe kwingxelo elungileyo ezinikeleyo iphini yemveliso ye-I/O PLL. Izibuko le-zdbfbclk lifumaneka kuphela ukuba i-I/O PLL ikwimowudi ye-buffer engu-zero. Ukunqanda ukubonakaliswa komqondiso xa usebenzisa imowudi yesikhuseli sokulibaziseka kwe-zero, musa ukubeka umkhondo webhodi kwiphini lokuphinda-phindwe kabini le-I/O.
itshixiwe	Isiphumo	Ukhetho	Undoqo we-IOPLL IP uqhuba eli zibuko phezulu xa i-PLL ifumana ukutshixa. Izibuko lihlala liphezulu nje ukuba i-IOPLL itshixiwe. I/O PLL iqinisekisa izibuko elitshixiweyo xa izigaba kunye namaxesha ewotshi yereferensi kunye newotshi yengxelo ziyi
iqhubekile...

Ipharamitha	Uhlobo	Imeko	Inkcazo
			efanayo okanye ngaphakathi lock unyamezelo lwesekethe. Xa umahluko phakathi kweempawu zewotshi ezimbini zidlula ukunyamezela kwesekethe yokutshixa, i-I/O PLL ilahlekelwa sisitshixo.
refclk1	Igalelo	Ukhetho	Umthombo wewotshi yereferensi yesibini eqhuba i-I/O PLL yesici sokutshintsha iwotshi.
ukucima	Igalelo	Ukhetho	Faka isignali yokucima isezantsi (1'b0) ubuncinane imijikelo yeewotshi ezi-3 ukuze utshintshe iwotshi ngesandla.
activeclk	Isiphumo	Ukhetho	Umqondiso wemveliso ukubonisa ukuba ngowuphi umthombo wewotshi yereferensi esetyenziswa yi-I/O PLL.
clkbad	Isiphumo	Ukhetho	Isignali yemveliso ebonisa ubume bomthombo wewotshi yereferensi ilungile okanye imbi.
cascade_out	Isiphumo	Ukhetho	Umqondiso wesiphumo esondla kwi-I/O PLL esezantsi.
adjpllin	Igalelo	Ukhetho	Umqondiso wegalelo otya ukusuka kumsinga we-I/O PLL.
outclk_[]	Isiphumo	Ukhetho	Ikloko yemveliso evela kwi-I/O PLL.

IOPLL Intel FPGA IP Core User Guide Archives

Ukuba i-IP core version ayidweliswanga, isikhokelo somsebenzisi senguqulo yangaphambili ye-IP siyasebenza

IP Core Version	Isikhokelo somsebenzisi
17.0	I-Altera I/O yeSigaba-Sitshixiwe iLoop (i-Altera IOPLL) iSikhokelo soMsebenzisi esiPhambili se-IP
16.1	I-Altera I/O yeSigaba-Sitshixiwe iLoop (i-Altera IOPLL) iSikhokelo soMsebenzisi esiPhambili se-IP
16.0	I-Altera I/O yeSigaba-Sitshixiwe iLoop (i-Altera IOPLL) iSikhokelo soMsebenzisi esiPhambili se-IP
15.0	I-Altera I/O yeSigaba-Sitshixiwe iLoop (i-Altera IOPLL) iSikhokelo soMsebenzisi esiPhambili se-IP

Imbali yoHlaziyo yoXwebhu ye-IOPLL Intel FPGA IP Core User Guide

Inguqulelo yoXwebhu	Intel Quartus® Prime Version	Iinguqu
2019.06.24	18.1	Ihlaziywe inkcazo yamagalelo ewotshi enikezelweyo kwi Uyilo lwe-I/O PLL oluqhelekileyo umzobo.
2019.01.03	18.1	• Hlaziya i Ukufikelela kwi-PLL LVDS_CLK/LOADEN kwizibuko lemveliso iparameter kwi I-IOPLL IP Core Parameters-Izicwangciso zeTab itafile. • Hlaziya inkcazo yezibuko le-zdbfbclk kwi IOPLL IP Core Ports itafile.
2018.09.28	18.1	• Ilungiswe inkcazo yokutshintsha kwi IOPLL IP Core Ports itafile. • Thiya ngokutsha ezi core ze-IP zilandelayo ngokokwenziwa ngokutsha kwe-Intel: -Utshintsho lwe-Altera IOPLL IP core kwi-IOPLL Intel FPGA IP core. -Itshintshiwe iAltera PLL Reconfig IP core kwiPLL Reconfig Intel FPGA IP core. -Utshintsho lwe-Arria 10 FPLL IP core kwi-fPLL Intel Arria 10 / Cyclone 10 FPGA IP core.

Umhla	Inguqulelo	Iinguqu
NgoJuni 2017	2017.06.16	• Inkxaso eyongeziweyo yezixhobo ze-Intel Cyclone 10 GX. • Ibhalwe ngokutsha njenge-Intel.
Disemba 2016	2016.12.05	Ihlaziywe inkcazo yezibuko lokuqala londoqo we-IP.
NgoJuni 2016	2016.06.23	• Uhlaziyo lwe-IP Core Parameters - Izicwangciso Tab table. -Ingcaciso ehlaziyiweyo ye-Manual Switchover kunye ne-Automatic Switchover nge-Manual Override parameters. Uphawu lolawulo lwewotshi lusebenza luphantsi. -Uhlaziyo lwenkcazo ye-Switchover Delay parameter. • Iikhawunta ezichaziweyo ze-M kunye ne-C ze-DPS Counter Selection parameter kwi-IP Core Parameters - Dynamic Reconfiguration Tab table. • Kutshintshwe igama lezibuko lokutshintsha iwotshi ukusuka kwi-clkswitch ukuya kwi-extwitch kwi-Eyiqhelekileyo ye-I/O PLL Architecture diagram.
Meyi 2016	2016.05.02	I-IP Core Parameters ehlaziyiweyo - Itheyibhile yeTab yokuLungiselela kwakhona iDynamic.
Meyi 2015	2015.05.04	Ukuhlaziya inkcazo ye-Vumela ukufikelela kwi-PLL LVDS_CLK / LOADEN i-parameter ye-port ye-port kwi-IP Core Parameters - Izicwangciso zeTab table. Yongeza ikhonkco kwi-Signal Interface phakathi kwe-Altera IOPLL kunye ne-Altera LVDS SERDES IP Cores itheyibhile kwi-I / O kunye ne-Speed ​​​​Speed ​​​​I / O kwi-Arria 10 Devices isahluko.
Agasti 2014	2014.08.18	Ukukhutshwa kokuqala.

Amaxwebhu / Izibonelelo

intel UG-01155 IOPLL FPGA IP Core [pdf] Isikhokelo somsebenzisi UG-01155 IOPLL FPGA IP Core, UG-01155, IOPLL FPGA IP Core, FPGA IP Core

Iimbekiselo

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