intel UG-01155 IOPLL FPGA IP Core Tus Neeg Siv Qhia

Txhawb PLL uas nyob ib sab (adjpllin) cov tswv yim los txuas nrog PLL nce toj hauv PLL cascading hom.
Generates Memory Initialization File (.mif) thiab tso cai rau PLL dynamicVreconfiguration.

Txhawb PLL dynamic theem hloov.

Cov ntaub ntawv ntsig txog

Taw qhia rau Intel FPGA IP Cores
Muab cov ntaub ntawv ntau ntxiv txog Intel FPGA IP cores thiab parameter editor.
Cov Qauv Ua Haujlwm ntawm nplooj 9

Tso Tawm Moos ntawm nplooj 10
Siv Clock Switchover ntawm nplooj 10

PLL-rau-PLL Cascading ntawm nplooj 11
IOPLL Intel FPGA IP Core User Guide Archives ntawm nplooj 12

Muab cov npe ntawm cov neeg siv cov lus qhia rau yav dhau los versions ntawm IOPLL Intel FPGA IP core.

Device Family Support

IOPLL IP core tsuas yog txhawb nqa Intel Arria 10 thiab Intel Cyclone 10 GX cov cuab yeej cuab tam tsev neeg.

IOPLL IP Core Parameters

IOPLL IP core parameter editor tshwm hauv PLL qeb ntawm IP Catalog.

Parameter	Tus nqi raug cai	Kev piav qhia
Device Family	Intel Arria 10, Intel Cyclone 10 GX	Qhia txog tsev neeg lub cuab yeej.
Cheebtsam	—	Qhia lub hom phiaj ntaus ntawv.
Qib Qib	—	Qhia cov qib ceev rau lub hom phiaj ntaus ntawv.
PLL hom	Integer-N PLL	Qhia meej hom siv rau IOPLL IP core. Kev xaiv raug cai nkaus xwb Integer-N PLL. Yog tias koj xav tau ib feem PLL, koj yuav tsum siv fPLL Intel Arria 10 / Cyclone 10 FPGA IP core.
Siv Clock Frequency	—	Qhia meej qhov input zaus rau lub moos input, refclk, hauv MHz. Tus nqi pib yog 100.0 MHz. Qhov tsawg kawg nkaus thiab siab tshaj tus nqi yog nyob ntawm cov khoom xaiv.
Enable Locked Output Port	Tig los yog Tig tawm	Qhib kom qhib qhov chaw nres nkoj xauv.
Pab kom lub cev tso zis lub moos parameters	Tig los yog Tig tawm	Tig rau nkag mus rau lub cev PLL cov txee tsis tau qhia meej txog qhov xav tau tso zis ntau zaus.
Hom kev ua haujlwm	ncaj qha, tawm tswv yim sab nraud, ib txwm, qhov chaw synchronous, xoom ncua tsis, los yog lvds ua	Qhia meej txog kev ua haujlwm ntawm PLL. Qhov kev ua haujlwm zoo li qub yog ncaj qha hom. • Yog tias koj xaiv qhov ncaj qha hom, PLL txo qhov ntev ntawm txoj kev tawm tswv yim los tsim qhov tsawg tshaj plaws ua tau jitter ntawm PLL cov zis tawm.Lub moos sab hauv thiab sab nraud ntawm lub moos tawm ntawm PLL yog theem hloov nrog kev hwm rau PLL moos input. Hauv hom no, PLL tsis them nyiaj rau txhua lub moos network. • Yog tias koj xaiv qhov ib txwm hom, PLL them nyiaj rau qhov ncua sij hawm ntawm lub moos sab hauv siv los ntawm lub moos tso zis. Yog tias PLL tseem siv los tsav lub moos sab nraud tso zis tus pin, qhov sib txuas theem hloov ntawm lub teeb liab ntawm tus pin tso zis tshwm sim. • Yog tias koj xaiv qhov qhov chaw synchronous hom, lub moos ncua sij hawm los ntawm tus pin rau I / O input register sib tw cov ntaub ntawv ncua ntawm tus pin rau I / O input register. • Yog tias koj xaiv qhov tawm tswv yim sab nraud hom, koj yuav tsum txuas lub fbclk input chaw nres nkoj rau ib tus pin input. Lub rooj tsavxwm-theem kev sib txuas yuav tsum txuas ob lub tswv yim tus pin thiab sab nraud moos tso zis chaw nres nkoj, fboutclk. Qhov chaw nres nkoj fbclk tau ua raws li lub sijhawm nkag. • Yog tias koj xaiv qhov xoom ncua tsis hom, PLL yuav tsum pub lub moos sab nraud tso tawm tus pin thiab them nyiaj rau qhov ncua sij hawm qhia los ntawm tus pin ntawd. Lub teeb liab pom ntawm tus pin yog synchronized rau lub moos input. PLL moos tso zis txuas mus rau altbidir chaw nres nkoj thiab tsav zdbfbclk ua qhov chaw nres nkoj tso zis. Yog tias PLL tseem tsav lub moos sab hauv lub network, qhov hloov pauv hloov pauv ntawm lub network tshwm sim. • Yog tias koj xaiv qhov lvds ua hom, tib cov ntaub ntawv thiab lub sijhawm sib raug zoo ntawm cov pins ntawm lub SERDES capture register yog khaws cia. Hom kev them nyiaj rau qhov qeeb hauv LVDS moos network, thiab nruab nrab ntawm cov ntaub ntawv tus pin thiab moos input tus pin mus rau SERDES ntes txoj hauv kev.
Lub moos	1–9	Qhia txog cov naj npawb ntawm cov moos tso zis uas xav tau rau txhua lub cuab yeej hauv PLL tsim. Cov kev thov rau qhov tso zis ntau zaus, hloov theem, thiab lub voj voog ua haujlwm tau qhia raws li tus naj npawb ntawm cov moos xaiv.
Qhia meej VCO zaus	Tig los yog Tig tawm	Tso cai rau koj txwv VCO zaus rau tus nqi teev. Qhov no yog qhov muaj txiaj ntsig zoo thaum tsim PLL rau LVDS sab nraud hom, lossis yog tias xav tau ib qho kev hloov pauv theem hloov theem loj.
*txuas ntxiv…*

Parameter	Tus nqi raug cai	Kev piav qhia
VCO zaus (1)	—	• Thaum twg Pab kom lub cev tso zis lub moos parameters yog qhib- qhia VCO zaus raws li qhov tseem ceeb rau Siv Clock Frequency, Multiply Factor (M-Counter), thiab Kev faib ua feem (N-Counter). • Thaum twg Pab kom lub cev tso zis lub moos parameters raug muab tua- tso cai rau koj qhia tus nqi thov rau VCO zaus. Tus nqi pib yog 600.0 MHz.
Muab lub npe moos thoob ntiaj teb	Tig los yog Tig tawm	Tso cai rau koj hloov lub npe tso zis moos lub npe.
Lub npe moos	—	Tus neeg siv moos lub npe rau Synopsis Design Constraints (SDC).
Xav tau zaus	—	Qhia meej cov zis moos zaus ntawm cov zis moos sib xws, outclk[], hauv MHz. Tus nqi pib yog 100.0 MHz. Qhov tsawg kawg nkaus thiab qhov siab tshaj plaws yog nyob ntawm cov cuab yeej siv. Lub PLL tsuas yog nyeem cov lej hauv thawj rau rau tus lej lej.
Qhov tseeb	—	Tso cai rau koj xaiv qhov tseeb tso zis zaus zaus los ntawm ib daim ntawv teev cov kev ua tau zoo. Lub neej ntawd tus nqi yog qhov ze tshaj plaws ua tau raws li qhov xav tau ntau zaus.
Phase Shift units	ps or qib	Qhia txog theem hloov chaw rau qhov sib thooj tso zis moos chaw nres nkoj, outclk[], hauv picoseconds (ps) lossis degrees.
Desired Phase Shift	—	Qhia tus nqi thov rau lub sijhawm hloov. Tus nqi pib yog 0ps wb.
Phase ua haujlwm tiag tiag	—	Tso cai rau koj xaiv lub sijhawm hloov pauv tiag tiag los ntawm cov npe ntawm qhov ua tiav theem hloov qhov tseem ceeb. Tus nqi pib yog qhov ze tshaj plaws ua tiav theem hloov mus rau qhov xav tau theem hloov.
Desired Duty Cycle	0.0–100.0	Qhia tus nqi thov rau lub voj voog ua haujlwm. Tus nqi pib yog 50.0%.
Lub luag haujlwm tiag tiag	—	Tso cai rau koj xaiv lub voj voog lub luag haujlwm tiag tiag los ntawm cov npe ntawm cov txiaj ntsig ntawm lub voj voog ua tiav. Lub neej ntawd tus nqi yog qhov ze tshaj plaws ua tiav lub luag haujlwm mus rau lub voj voog uas xav tau.
Multiply Factor (M-Counter) (2)	4–511	Qhia qhov sib npaug ntawm M-counter. Qhov kev cai lij choj ntawm M txee yog 4-511. Txawm li cas los xij, kev txwv ntawm qhov tsawg kawg nkaus raws cai PFD zaus thiab qhov siab tshaj plaws raws li txoj cai VCO zaus txwv tsis pub muaj M counter range rau 4–160.
Kev faib ua feem (N-Counter) (2)	1–511	Qhia meej qhov sib faib ntawm N-tus lej. Qhov kev cai lij choj ntawm N txee yog 1-511. Txawm li cas los xij, kev txwv ntawm qhov tsawg kawg nkaus raws cai PFD zaus txwv qhov kev ua tau zoo ntawm N counter rau 1-80.
Kev faib ua feem (C-Counter) (2)	1–511	Qhia meej txog qhov sib faib rau lub moos tso zis (C-counter).

Qhov kev ntsuas no tsuas yog muaj thaum Qhib lub cev tso zis lub moos tsis raug kaw.

Qhov kev ntsuas no tsuas yog muaj thaum Qhib lub cev tso zis lub moos tsis pub dhau.

IOPLL IP Core Parameters - Chaw Tab

Table 2. IOPLL IP Core Parameters – Chaw Tab

Parameter	Tus nqi raug cai	Kev piav qhia
PLL Bandwidth Preset	Tsawg, Nruab nrab, los yog Siab	Qhia meej txog PLL bandwidth preset chaw. Lub neej ntawd xaiv yog Tsawg.
PLL pib pib dua	Tig los yog Tig tawm	Tsis siv neeg rov pib dua PLL ntawm qhov poob ntawm qhov xauv.
Tsim ib lub tswv yim thib ob clk 'refclk1'	Tig los yog Tig tawm	Tig rau muab lub moos thaub qab txuas nrog koj PLL uas tuaj yeem hloov nrog koj lub moos siv thawj zaug.
Lub Sij Hawm Siv Sijhawm thib ob	—	Xaiv qhov zaus ntawm qhov thib ob input moos teeb liab. Tus nqi pib yog 100.0 MHz. Qhov tsawg kawg nkaus thiab siab tshaj tus nqi yog nyob ntawm cov cuab yeej siv.
Tsim ib qho 'active_clk' teeb liab los qhia lub moos input siv	Tig los yog Tig tawm	Tig rau tsim cov activeclk tso zis. Lub activeclk cov zis qhia txog lub moos input uas yog siv los ntawm PLL. Cov zis teeb liab qis qhia tias refclk thiab tso zis teeb liab siab qhia refclk1.
Tsim ib lub teeb liab 'clkbad' rau txhua lub moos input	Tig los yog Tig tawm	Tig rau los tsim ob clkbad outputs, ib qho rau txhua lub moos input. Cov zis teeb liab qis qhia tias lub moos ua haujlwm thiab cov teeb liab tso tawm siab qhia tias lub moos tsis ua haujlwm.
Hloov hom	Automatic Switchover, Phau ntawv Switchover, los yog Automatic Switchover nrog phau ntawv hla dhau	Qhia meej txog hom kev hloov pauv rau kev tsim daim ntawv thov. IP txhawb peb hom kev hloov pauv: • Yog tias koj xaiv qhov Automatic Switchover hom, PLL circuitry saib xyuas lub moos xaiv siv. Yog tias ib lub moos nres, lub voj voog yuav hloov mus rau lub moos thaub qab hauv ob peb lub moos thiab hloov kho cov xwm txheej teeb liab, clkbad thiab activeclk. • Yog tias koj xaiv qhov Phau ntawv Switchover hom, thaum lub teeb liab tswj, extswitch, hloov ntawm logic siab mus rau logic qis, thiab nyob qis qis rau tsawg kawg peb lub voj voog, lub moos input hloov mus rau lwm lub moos. Lub extswitch tuaj yeem tsim los ntawm FPGA core logic lossis input pin. • Yog tias koj xaiv Automatic Switchover nrog phau ntawv hla dhau hom, thaum lub teeb liab extswitch yog tsawg, nws overrides tsis siv neeg hloov ua haujlwm. Tsuav yog extswitch tseem qis, ntxiv kev hloov pauv ntxiv raug thaiv. Txhawm rau xaiv hom no, koj ob lub moos yuav tsum tau khiav thiab qhov zaus ntawm ob lub moos tsis tuaj yeem sib txawv ntau dua 20%. Yog tias ob lub moos tsis nyob rau tib lub sijhawm, tab sis lawv lub sijhawm sib txawv yog nyob rau hauv 20%, lub moos poob kev tshawb nrhiav tuaj yeem ntes lub moos poob. PLL feem ntau yuav poob tawm ntawm lub xauv tom qab lub PLL moos input switchover thiab xav tau sij hawm los xauv dua.
Kev ncua ncua	0–7	Ntxiv ib qho tshwj xeeb ntawm lub voj voog ncua mus rau txoj kev hloov pauv. Tus nqi pib yog 0.
Nkag mus rau PLL LVDS_CLK / LOADEN qhov chaw tso zis	Neeg tsis taus, Pab LVDS_CLK/ LOADEN 0, los yog Pab LVDS_CLK/ LOADEN 0 & 1	Xaiv Pab LVDS_CLK/LOADEN 0 or Pab LVDS_CLK/ LOADEN 0 & 1 txhawm rau pab kom PLL lvds_clk lossis chaw nres nkoj tso zis. Ua kom muaj qhov ntsuas no yog tias PLL pub LVDS SERDES thaiv nrog PLL sab nraud. Thaum siv I/O PLL outclk ports nrog LVDS ports, outclk[0..3] yog siv rau lvds_clk[0,1] thiab loaden[0,1] ports, outclk4 tuaj yeem siv rau coreclk ports.
Pab kom nkag mus rau PLL DPA tso zis chaw nres nkoj	Tig los yog Tig tawm	Tig rau kom pab PLL DPA tso zis chaw nres nkoj.
*txuas ntxiv…*

Parameter	Tus nqi raug cai	Kev piav qhia
Pab kom nkag mus rau PLL sab nraud moos tso zis chaw nres nkoj	Tig los yog Tig tawm	Qhib kom qhib lub PLL sab nraud moos tso zis chaw nres nkoj.
Qhia meej uas outclk yuav siv li extclk_out[0] qhov chaw	C0 – C8	Qhia meej txog qhov chaw nres nkoj outclk los siv ua extclk_out[0] qhov chaw.
Qhia meej uas outclk yuav siv li extclk_out[1] qhov chaw	C0 – C8	Qhia meej txog qhov chaw nres nkoj outclk los siv ua extclk_out[1] qhov chaw.

Cascading Tab

Table 3. IOPLL IP Core Parameters – Cascading Tab3

Parameter	Tus nqi raug cai	Kev piav qhia
Tsim 'cascade tawm' teeb liab los txuas nrog PLL nqes hav	Tig los yog Tig tawm	Tig rau los tsim qhov chaw nres nkoj cascade_out, uas qhia tau hais tias qhov PLL no yog qhov chaw thiab txuas nrog lub hom phiaj (kub ntws) PLL.
Qhia meej qhov twg outclk yuav siv los ua cascading qhov chaw	0–8	Qhia qhov chaw cascading.
Tsim ib qho adjpllin lossis cclk teeb liab los txuas nrog PLL ntws	Tig los yog Tig tawm	Tig rau los tsim qhov chaw nres nkoj nkag, uas qhia tau tias PLL no yog qhov chaw thiab txuas nrog lub hauv paus (sab sauv) PLL.

Dynamic Reconfiguration Tab

Table 4. IOPLL IP Core Parameters – Dynamic Reconfiguration Tab

Parameter	Tus nqi raug cai	Kev piav qhia
Pab kom dynamic reconfiguration ntawm PLL	Tig los yog Tig tawm	Tig rau qhov ua kom lub zog hloov pauv ntawm PLL no (ua ke nrog PLL Reconfig Intel FPGA IP core).
Pab kom nkag mus rau dynamic theem hloov chaw nres nkoj	Tig los yog Tig tawm	Tig rau qhov ua kom lub sijhawm hloov pauv hloov pauv hloov pauv nrog PLL.
MIF tiam Option (3)	Tsim New MIF File, Ntxiv Configuration rau Existing MIF File, thiab Tsim MIF File thaum lub sij hawm IP tiam	Los yog tsim ib qho tshiab .mif file muaj cov kev teeb tsa tam sim no ntawm I/O PLL, lossis ntxiv qhov kev teeb tsa no rau ib qho .mif uas twb muaj lawm file. Koj tuaj yeem siv qhov no .mif file Thaum lub sij hawm dynamic reconfiguration rau reconfigure I/O PLL rau nws tam sim no nqis.
Txoj kev mus rau New MIF file (4)	—	Nkag mus rau qhov chaw thiab file npe .mif file tsim nyog.
Txoj kev mus rau MIF uas twb muaj lawm file (5)	—	Nkag mus rau qhov chaw thiab file npe .mif file koj npaj siab yuav ntxiv rau.
*txuas ntxiv…*

Qhov kev ntsuas no tsuas yog muaj nyob rau thaum Qhib kev teeb tsa dynamic ntawm PLL qhib.

Qhov kev ntsuas no tsuas yog muaj thaum Tsim MIF tshiab File yog xaiv los ua MIF Generation
Kev xaiv.

Parameter	Tus nqi raug cai	Kev piav qhia
Qhib Dynamic Phase Shift rau MIF Streaming (3)	Tig los yog Tig tawm	Tig rau khaws dynamic theem hloov khoom rau PLL reconfiguration.
DPS Counter Xaiv (6)	C0–C8, Txhua tus C, or M	Xaiv lub txee rau kev hloov pauv theem dynamic. M yog qhov ntsuas ntsuas thiab C yog cov ntsuas tom qab ntsuas.
Tus naj npawb ntawm Dynamic Phase Shifts (6)	1–7	Xaiv tus naj npawb ntawm theem ua haujlwm nce ntxiv. Qhov loj ntawm ib theem hloov pauv nce yog sib npaug rau 1/8 ntawm VCO lub sijhawm. Tus nqi pib yog 1.
Dynamic Phase Shift Direction (6)	Qhov zoo or Tsis zoo	Txiav txim siab qhov dynamic theem hloov kev coj mus khaws cia rau hauv PLL MIF.

Qhov kev ntsuas no tsuas yog muaj thaum Ntxiv Configuration rau MIF uas twb muaj lawm File yog xaiv los ua MIF Generation Option

IOPLL IP Core Parameters - Advanced Parameters Tab

Table 5. IOPLL IP Core Parameters – Advanced Parameters Tab

Parameter	Tus nqi raug cai	Kev piav qhia
Advanced Parameters	—	Qhia ib lub rooj ntawm lub cev PLL teeb tsa uas yuav raug siv raws li koj qhov kev tawm tswv yim.

Functional Description

Ib qho I/O PLL yog ib qhov kev tswj xyuas zaus uas tsim cov moos tso zis los ntawm synchronizing nws tus kheej mus rau lub moos input. Lub PLL sib piv cov theem sib txawv ntawm cov teeb liab tawm tswv yim thiab cov teeb liab tso zis ntawm voltage-tswj oscillator (VCO) thiab tom qab ntawd ua cov theem synchronization kom muaj lub kaum sab xis ntawm lub kaum sab xis (xauv) ntawm qhov zaus ntawm cov tswv yim lossis cov teeb liab siv. Lub synchronization lossis kev tawm tswv yim tsis zoo ntawm lub kaw lus yuam kom PLL yuav tsum raug kaw rau theem.
Koj tuaj yeem teeb tsa PLLs ua ntau zaus, sib faib, demodulators, nrhiav cov tshuab hluav taws xob, lossis moos rov qab. Koj tuaj yeem siv PLLs los tsim cov zaus ruaj khov, rov qab cov teeb liab los ntawm kev sib txuas lus nrov, lossis faib cov cim moos thoob plaws hauv koj tus qauv tsim.

Tsev Blocks ntawm PLL

Cov blocks tseem ceeb ntawm I/O PLL yog lub ntsuas zaus ntsuas (PFD), lub twj tso kua mis, lub voj lim, VCO, thiab cov txee, xws li lub txee tawm tswv yim (M), lub txee ua ntej (N), thiab tom qab- ntsuas ntsuas ntsuas (C). PLL architecture nyob ntawm lub cuab yeej koj siv hauv koj tus qauv tsim.

Qhov parameter no tsuas yog muaj thaum Qhib Dynamic Phase Shift rau MIF Streaming yog qhib.

Hom I/O PLL Architecture

Cov ntsiab lus hauv qab no feem ntau siv los piav txog tus cwj pwm ntawm PLL:
PLL lub sijhawm kaw-tseem hu ua PLL lub sijhawm tau txais. PLL lub sijhawm kaw yog lub sijhawm rau PLL kom ncav cuag lub hom phiaj zaus thiab theem kev sib raug zoo tom qab lub zog-up, tom qab lub programmed tso zis zaus hloov, lossis tom qab PLL rov pib dua. Nco tseg: Simulation software tsis ua qauv PLL lub sijhawm kaw tiag tiag. Simulation qhia tau hais tias lub sijhawm xauv nrawm tsis muaj tseeb. Rau qhov tseeb xauv lub sij hawm specification, xa mus rau lub ntaus ntawv datasheet.
PLL kev daws teeb meem - qhov tsawg kawg nkaus tus nqi nce ntawm PLL VCO. Tus naj npawb ntawm cov khoom hauv M thiab N cov txee txiav txim siab PLL tus nqi daws teeb meem.
PLL sample rate — lub FREF sampling zaus yuav tsum tau ua cov theem thiab zaus kho hauv PLL. PLL samptus nqi yog fREF / N.

PLL xauv

PLL ntsuas phoo yog nyob ntawm ob lub tswv yim tawm tswv yim hauv lub sijhawm ntsuas ntsuas. Lub teeb liab xauv yog ib qho asynchronous tso zis ntawm PLLs. Tus naj npawb ntawm cov voj voog uas yuav tsum tau mus rau qhov rooj xauv lub teeb liab yog nyob ntawm PLL input moos uas teev lub rooj vag-lock circuitry. Faib lub sij hawm kaw qhov siab tshaj plaws ntawm PLL los ntawm lub sij hawm ntawm lub sij hawm ntawm PLL input moos los xam cov naj npawb ntawm lub moos cycles yuav tsum tau mus rau lub rooj vag lub xauv teeb liab.

Hom kev ua haujlwm

IOPLL IP core txhawb rau XNUMX hom kev tawm tswv yim sib txawv. Txhua hom tso cai rau lub moos sib npaug thiab sib faib, theem hloov, thiab lub luag haujlwm-lub voj voog programming.

Tso zis moos

IOPLL IP core tuaj yeem tsim tau txog cuaj moos tso zis tawm. Lub moos generated tso zis teeb liab teev cov tub ntxhais los yog cov blocks sab nraud sab nraum lub tub ntxhais.
Koj tuaj yeem siv lub teeb liab pib dua los rov pib lub sijhawm tso zis rau 0 thiab lov tes taw PLL tso zis moos.
Txhua lub moos tso zis muaj cov txheej txheem thov uas koj tuaj yeem qhia qhov xav tau qhov tseem ceeb rau cov zis zaus, theem hloov, thiab lub voj voog ua haujlwm. Cov kev xav tau yog cov chaw uas koj xav siv hauv koj tus qauv tsim.

Qhov tseeb qhov tseem ceeb rau qhov zaus, theem hloov, thiab lub voj voog lub luag haujlwm yog qhov chaw ze tshaj plaws (qhov kwv yees zoo tshaj plaws ntawm qhov xav tau) uas tuaj yeem siv tau hauv PLL circuit.

Siv Clock Switchover

Qhov kev siv moos hloov pauv ua haujlwm tso cai rau PLL hloov ntawm ob lub sij hawm siv tswv yim. Siv cov yam ntxwv no rau lub moos redundancy, lossis rau daim ntawv thov ob lub moos xws li hauv lub kaw lus. Lub kaw lus tuaj yeem qhib lub moos rov ua dua yog tias lub moos tseem ceeb nres.
Siv cov kev siv moos hloov pauv feature, koj tuaj yeem qhia qhov zaus rau lub moos thib ob, thiab xaiv hom thiab ncua sijhawm rau kev hloov pauv.

Lub moos tsis pom thiab siv moos hloov pauv thaiv muaj cov haujlwm hauv qab no:

Saib xyuas cov xwm txheej siv moos. Yog hais tias lub moos siv tsis tau, lub moos cia li hloov mus rau lub moos thaub qab lub tswv yim. Lub moos hloov kho cov xwm txheej ntawm clkbad thiab activeclk teeb liab kom ceeb toom qhov xwm txheej.
Hloov lub moos siv rov qab los ntawm ob qhov sib txawv. Siv lub teeb liab extswitch los tswj tus tes hloov qhov kev txiav txim. Tom qab qhov kev hloov pauv tshwm sim, PLL tuaj yeem poob lub xauv ib ntus thiab dhau los ntawm cov txheej txheem suav.

PLL-rau-PLL Cascading

Yog tias koj cascade PLLs hauv koj tus qauv tsim, lub hauv paus (sab sauv) PLL yuav tsum muaj qhov chaw qis qis, thaum lub hom phiaj (downstream) PLL yuav tsum muaj qhov teeb tsa highbandwidth. Thaum lub sij hawm cascading, cov zis ntawm qhov chaw PLL ua hauj lwm raws li lub moos siv (input) ntawm lub hom phiaj PLL. Kev teeb tsa bandwidth ntawm cascaded PLLs yuav tsum sib txawv. Yog tias qhov teeb tsa bandwidth ntawm cascaded PLLs zoo ib yam, cov cascaded PLLs tuaj yeem amplify theem suab nrov ntawm tej frequencies.Qhov adjpllin input moos qhov chaw yog siv rau inter-cascading ntawm fracturable fractional PLLs.

Chaw nres nkoj

Table 6. IOPLL IP Core Ports

Parameter	Hom	Qhov xwm txheej	Kev piav qhia
refclk ua	Tswv yim	Yuav tsum tau	Lub moos siv lub hauv paus uas tsav I/O PLL.
rst	Tswv yim	Yuav tsum tau	Lub asynchronous reset chaw nres nkoj rau cov zis moos. Tsav qhov chaw nres nkoj no siab kom rov pib dua txhua lub sijhawm tso zis rau tus nqi ntawm 0. Koj yuav tsum txuas qhov chaw nres nkoj no rau cov neeg siv tswj lub teeb liab.
fbclk ua	Tswv yim	Xaiv tau	Lub tswv yim sab nraud input chaw nres nkoj rau I/O PLL. IOPLL IP core tsim qhov chaw nres nkoj no thaum I / O PLL ua haujlwm hauv hom kev tawm tswv yim sab nraud lossis xoom-qhib tsis muaj hom. Txhawm rau ua kom tiav cov lus tawm tswv yim, kev sib txuas ntawm pawg thawj coj yuav tsum txuas rau fbclk chaw nres nkoj thiab lub moos sab nraud tso zis chaw nres nkoj ntawm I / O PLL.
fboutclk ua	Tso zis	Xaiv tau	Qhov chaw nres nkoj uas pub cov chaw nres nkoj fbclk los ntawm kev siv hluav taws xob. Qhov chaw nres nkoj fboutclk tsuas yog muaj yog tias I / O PLL nyob rau hauv hom tawm tswv yim sab nraud.
zdbfclk ua	Ob tog	Xaiv tau	Qhov chaw nres nkoj bidirectional uas txuas mus rau lub mimic circuitry. Qhov chaw nres nkoj no yuav tsum txuas mus rau tus pin bidirectional uas tau muab tso rau ntawm qhov kev tawm tswv yim zoo siab tso tawm tus pin ntawm I / O PLL. Zdbfbclk chaw nres nkoj tsuas yog muaj yog tias I/O PLL nyob rau hauv xoom- ncua tsis hom. Txhawm rau kom tsis txhob muaj kev cuam tshuam lub teeb liab thaum siv xoom-delay tsis hom, tsis txhob tso cov kab khiav ntawm ob sab I / O tus pin.
kaw	Tso zis	Xaiv tau	IOPLL IP core tsav qhov chaw nres nkoj siab thaum PLL tau txais xauv. Qhov chaw nres nkoj tseem nyob siab ntev npaum li IOPLL raug kaw. Lub I/O PLL lees paub qhov chaw nres nkoj xauv thaum cov theem thiab zaus ntawm lub moos siv thiab cov lus tawm tswv yim yog
*txuas ntxiv…*

Parameter	Hom	Qhov xwm txheej	Kev piav qhia
			tib yam los yog nyob rau hauv lub xauv Circuit Court kam rau ua. Thaum qhov sib txawv ntawm ob lub moos teeb liab tshaj qhov ntsuas ntsuas ntsuas ntsuas, I / O PLL poob xauv.
refclk 1	Tswv yim	Xaiv tau	Qhov thib ob siv moos qhov chaw uas tsav I / O PLL rau lub moos hloov pauv.
extswitch	Tswv yim	Xaiv tau	Qhia tawm lub teeb liab extswitch qis (1'b0) rau tsawg kawg 3 lub voj voog mus rau manually hloov lub moos.
ua activeclk	Tso zis	Xaiv tau	Cov teeb liab tso zis los qhia tias siv lub moos twg yog siv los ntawm I/O PLL.
clkbad	Tso zis	Xaiv tau	Cov teeb liab tso zis uas qhia txog cov xwm txheej ntawm kev siv moos yog qhov zoo lossis tsis zoo.
cascade_out	Tso zis	Xaiv tau	Tso zis teeb liab uas pub rau hauv qab I/O PLL.
ua adjpl	Tswv yim	Xaiv tau	Cov teeb liab tawm tswv yim uas pub los ntawm cov dej ntws I/O PLL.
outclk_[]	Tso zis	Xaiv tau	Tso zis moos los ntawm I / O PLL.

IOPLL Intel FPGA IP Core Tus Neeg Siv Phau Ntawv Qhia Archives

Yog tias tus IP core version tsis tau teev tseg, cov lus qhia siv rau tus IP core version dhau los siv

IP Core Version	Cov neeg siv phau ntawv qhia
17.0	Altera I/O Phase-Locked Loop (Altera IOPLL) IP Core User Guide
16.1	Altera I/O Phase-Locked Loop (Altera IOPLL) IP Core User Guide
16.0	Altera I/O Phase-Locked Loop (Altera IOPLL) IP Core User Guide
15.0	Altera I/O Phase-Locked Loop (Altera IOPLL) IP Core User Guide

Cov ntaub ntawv kho dua tshiab rau IOPLL Intel FPGA IP Tus Neeg Siv Khoom Qhia

Cov ntaub ntawv Version	Intel Quartus® Prime Version	Hloov
2019.06.24	18.1	Hloov kho cov lus piav qhia rau cov khoom siv moos tshwj xeeb hauv lub Hom I/O PLL Architecture daim duab.
2019.01.03	18.1	• Hloov kho cov Nkag mus rau PLL LVDS_CLK/LOADEN tso zis chaw nres nkoj parameter nyob rau hauv IOPLL IP Core Parameters - Chaw Tab rooj. • Hloov kho cov lus piav qhia rau qhov chaw nres nkoj zdbfbclk hauv IOPLL IP Core Ports rooj.
2018.09.28	18.1	• Kho cov lus piav qhia rau extswitch hauv IOPLL IP Core Ports rooj. • Renamed tus IP cores hauv qab no raws li Intel rebranding: - Hloov Altera IOPLL IP core rau IOPLL Intel FPGA IP core. - Hloov Altera PLL Reconfig IP core rau PLL Reconfig Intel FPGA IP core. - Hloov Arria 10 FPLL IP core rau fPLL Intel Arria 10 / Cyclone 10 FPGA IP core.

Hnub tim	Version	Hloov
Lub Rau Hli 2017	2017.06.16	• Ntxiv kev txhawb nqa rau Intel Cyclone 10 GX li. • Rebranded li Intel.
Kaum Ob Hlis 2016	2016.12.05	Hloov kho cov lus piav qhia ntawm qhov chaw nres nkoj thawj ntawm IP core.
Lub Rau Hli 2016	2016.06.23	• Hloov tshiab IP Core Parameters – Chaw Tab rooj. - Hloov kho cov lus piav qhia rau Phau Ntawv Hloov Hloov thiab Tsis Siv Neeg Hloov Hloov nrog Phau Ntawv Qhia Tsis Siv Neeg. Lub moos switchover tswj lub teeb liab yog nquag qis. - Hloov kho cov lus piav qhia rau Switchover Delay parameter. • Txhais M thiab C txee rau DPS Counter Selection parameter hauv IP Core Parameters – Dynamic Reconfiguration Tab rooj. • Hloov lub moos switchover chaw nres nkoj lub npe los ntawm clkswitch mus rau extswitch hauv Hom I/O PLL Architecture daim duab.
Peb 2016	2016.05.02	Hloov tshiab IP Core Parameters - Dynamic Reconfiguration Tab rooj.
Peb 2015	2015.05.04	Hloov kho cov lus piav qhia rau Pab kom nkag mus rau PLL LVDS_CLK/LOADEN tso zis chaw nres nkoj tsis nyob hauv IP Core Parameters - Chaw Tab rooj. Ntxiv ib qhov txuas mus rau lub teeb liab Interface ntawm Altera IOPLL thiab Altera LVDS SERDES IP Cores rooj hauv I/O thiab High Speed I/O hauv Arria 10 Devices tshooj.
Lub Yim Hli 2014	2014.08.18	Kev tso tawm thawj zaug.

Cov ntaub ntawv / Cov ntaub ntawv

Intel UG-01155 IOPLL FPGA IP Core [ua pdf] Cov neeg siv phau ntawv qhia
UG-01155 IOPLL FPGA IP Core, UG-01155, IOPLL FPGA IP Core, FPGA IP Core

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Cov neeg siv phau ntawv

Intel UG-01155 IOPLL FPGA IP Core

IOPLL Intel® FPGA IP Core User Guide