Intel AN 837 Dhizaini Mazano eHDMI FPGA IP
Dhizaini Mazano eHDMI Intel® FPGA IP
Iyo dhizaini dhizaini inokubatsira iwe kuita Yepamusoro-Definition Multimedia Interface (HDMI) Intel FPGA IPs uchishandisa FPGA zvishandiso. Aya nhungamiro anofambisa dhizaini yeHDMI Intel® FPGA IP vhidhiyo interfaces.
- HDMI Intel FPGA IP User Guide
- Mufananidzo 745: Dhizaini Mazano eIntel FPGA DisplayPort Interface
HDMI Intel FPGA IP Dhizaini Mazano
Iyo HDMI Intel FPGA interface ine Transition Minimized Differential Signaling (TMDS) data uye wachi chiteshi. Iyo interface inotakura zvakare Vhidhiyo Electronics Standards Association (VESA) Display Data Channel (DDC). Iyo TMDS chiteshi inotakura vhidhiyo, odhiyo, uye data yekubatsira. Iyo DDC yakavakirwa paI2C protocol. Iyo HDMI Intel FPGA IP musimboti inoshandisa iyo DDC kuverenga Yakawedzerwa Display Identification Dhata (EDID) uye kuchinjanisa magadzirirwo uye mamiriro ruzivo pakati peHDMI sosi nekunyura.
HDMI Intel FPGA IP Bhodhi Dhizaini Mazano
Paunenge uchigadzira yako HDMI Intel FPGA IP system, funga anotevera bhodhi dhizaini matipi.
- Shandisa isingasviki maviri vias pane imwe trace uye dzivirira kuburikidza ne stubs
- Matanidza iyo yekusiyanisa maviri impedance kune iyo impedance yekubatanidza uye tambo kusangana (100 ohm ± 10%).
- Deredzai pakati-paviri uye intra-pair skew kusangana neTMDS chiratidzo skew chinodiwa
- Dzivisa kufambisa maviri akasiyana pane gap mundege yepasi
- Shandisa yakajairwa high speed PCB dhizaini maitiro
- Shandisa level shifters kusangana nemagetsi kuteedzera paTX neRX
- Shandisa tambo dzakasimba, dzakadai seCat2 tambo yeHDMI 2.0
Schematic Diagrams
Iyo Bitec schematic dhayagiramu mumanongedzo akapihwa anoratidza iyo topology yeIntel FPGA mabhodhi ekuvandudza. Kushandisa HDMI 2.0 link topology inoda kuti usangane ne3.3 V yemagetsi. Kuti usangane ne 3.3 V kutevedzera paIntel FPGA zvishandiso, unofanirwa kushandisa nhanho shifter. Shandisa DC-yakabatana redhiraivha kana retimer seyero yekuchinja kune transmitter uye inogamuchira.
Iwo ekunze mutengesi zvishandiso TMDS181 uye TDP158RSBT, ese ari kushanda paDCcoupled link. Iwe unoda kwakaringana kudhonza-kumusoro paCEC mitsetse kuti uve nechokwadi chekushanda kana uchipindirana nemamwe evatengi kure ekudzora maturusi. Iyo Bitec schematic diagrams ndeyeCTS-yakasimbiswa. Certification, zvisinei, chigadzirwa-chikamu chakananga. Vagadziri vepuratifomu vanorayirwa kuti vasimbise chigadzirwa chekupedzisira chekushanda kwakaringana.
Related Information
- Schematic Dhiagiramu yeHSMC HDMI Mwanasikana Kadhi Revision 8
- Schematic Dhiagiramu yeFMC HDMI Mwanasikana Kadhi Revision 11
- Schematic Dhiagiramu yeFMC HDMI Mwanasikana Kadhi Revision 6
Hot-plug Detect (HPD)
Chiratidzo cheHPD chinotsamira pane iri kuuya +5V Simba siginecha, kune exampLe, pini yeHPD inogona kusimbiswa chete kana iyo +5V Power siginecha kubva kunobva kwaonekwa. Kuti uwirirane neFPGA, unofanirwa kushandura chiratidzo che5V HPD kuenda kuFPGA I/O vol.tage level (VCCIO), uchishandisa voltage-level muturikiri akadai seTI TXB0102, iyo isina kudhonza-up resistors yakabatanidzwa. Iyo HDMI sosi inoda kudonhedza iyo HPD chiratidzo kuti ikwanise kusiyanisa yakavimbika pakati peinoyangarara HPD chiratidzo uye yakakwira vol.tage level HPD chiratidzo. Singi yeHDMI +5V Sigi yeSimba inofanira kushandurirwa kuFPGA I/O voltage level (VCCIO). Chiratidzo chinofanirwa kudhonzwa zvisina simba pasi neanopikisa (10K) kusiyanisa inoyangarara + 5V Simba chiratidzo kana isiri kufambiswa neHDMI sosi. Iyo HDMI sosi + 5V Simba siginecha ine pamusoro-ikozvino chengetedzo isingapfuure 0.5A.
HDMI Intel FPGA IP Ratidza Dhata Channel (DDC)
Iyo HDMI Intel FPGA IP DDC yakavakirwa paiyo I2C masaini (SCL uye SDA) uye inoda kudhonza-kumusoro resistors. Kuti uwirirane neIntel FPGA, unofanirwa kushandura iyo 5V SCL uye SDA siginecha level kuFPGA I/O vol.tage level (VCCIO) vachishandisa voltage level muturikiri, seTI TXS0102 sekushandiswa muBitec HDMI 2.0 mwanasikana kadhi. Iyo TI TXS0102 voltage level muturikiri mudziyo unobatanidza mukati kudhonza-up resistors kuitira kuti pasave pa-bhodhi kudhonza-up resistors inodiwa.
Gwaro Revisheni Nhoroondo yeAN 837: Dhizaini Mazano eHDMI Intel FPGA IP
| Document Version | Kuchinja |
| 2019.01.28 |
|
| Date | Version | Kuchinja |
| Ndira 2018 | 2018.01.22 | Kusunungurwa kwekutanga.
Ongorora: Gwaro iri rine HDMI Intel FPGA dhizaini dhizaini yakabviswa kubva kuAN 745: Dhizaini Mirayiridzo yeDisplayPort uye HDMI Interfaces uye yakatumidzwa zita rekuti AN 745: Dhizaini Mazano eIntel FPGA DisplayPort Interface. |
Intel Corporation. Kodzero dzese dzakachengetwa. Intel, iyo Intel logo, uye mamwe maIntel mamaki zviratidzo zveIntel Corporation kana vatsigiri vayo. Intel inobvumira kushanda kweFPGA yayo uye semiconductor zvigadzirwa kune zvazvino zvakatemwa zvinoenderana neIntel yakajairwa waranti asi inochengeta kodzero yekuita shanduko kune chero zvigadzirwa nemasevhisi chero nguva pasina chiziviso. Intel haitore mutoro kana mutoro unobva mukushandisa kana kushandiswa kwechero ruzivo, chigadzirwa, kana sevhisi inotsanangurwa pano kunze kwekunge yakabvumiranwa nekunyora neIntel. Vatengi veIntel vanorairwa kuti vawane yazvino vhezheni yezvakatemwa zvemudziyo vasati vavimba nechero ruzivo rwakaburitswa uye vasati vaisa maodha ezvigadzirwa kana masevhisi.
Mamwe mazita nemhando anogona kunzi zvinhu zvevamwe.
ID: 683677
Shanduro: 2019-01-28
Zvinyorwa / Zvishandiso
 |
Intel AN 837 Dhizaini Mazano eHDMI FPGA IP [pdf] Bhuku reMushandisi AN 837 Dhizaini Mirayiridzo yeHDMI FPGA IP, AN 837, Dhizaini Mitemo yeHDMI FPGA IP, Mirayiridzo yeHDMI FPGA IP, HDMI FPGA IP |
