intel UG-01155 IOPLL FPGA IP Core

An sabunta don Intel® Quartus® Prime Design Suite: 18.1

IOPLL Intel® FPGA IP Core User Guide

IOPLL Intel® FPGA IP core yana ba ku damar saita saitunan Intel Arria® 10 da Intel Cyclone® 10 GX I/O PLL.

IOPLL IP core yana goyan bayan fasalulluka masu zuwa:

• Yana goyan bayan yanayin amsa agogo daban-daban guda shida: kai tsaye, martani na waje, na yau da kullun, tushen aiki tare, buffer sifiri, da yanayin LVDS.
• Yana haifar da siginonin fitarwa har zuwa agogo tara don na'urorin Intel Arria 10 da Intel CycloneM 10 GX.
• Yana canzawa tsakanin agogon shigarwar tunani guda biyu.
• Yana goyan bayan shigarwar PLL (adjpllin) kusa don haɗawa tare da PLL na sama a cikin yanayin cascading PLL.
• Yana Ƙirƙirar Ƙaddamar Ƙwaƙwalwar Ƙwaƙwalwar Ƙwaƙwalwar Ƙwaƙwalwar Ƙwaƙwalwar Ƙwaƙwalwar Ƙwaƙwalwar Ƙwaƙwalwar Ƙwaƙwalwar Ƙwaƙwalwa File (.mif) kuma yana ba da damar PLL dynamicVreconfiguration.
• Yana goyan bayan canjin lokaci mai ƙarfi na PLL.

Bayanai masu alaƙa

• Gabatarwa zuwa Intel FPGA IP Cores
  Yana ba da ƙarin bayani game da Intel FPGA IP cores da editan siga.
• Yanayin Aiki a shafi na 9
• Agogon fitarwa a shafi na 10
• Reference Clock Switchover a shafi na 10
• PLL-zuwa-PLL Cascading a shafi na 11
• IOPLL Intel FPGA IP Babban Taskokin Jagoran Mai Amfani akan shafi na 12

Yana ba da jerin jagororin mai amfani don sigar baya na IOPLL Intel FPGA IP core.

Tallafin Iyali na Na'ura

IOPLL IP core kawai yana goyan bayan Intel Arria 10 da Intel Cyclone 10 GX iyalai na na'urar.

IOPLL IP Core Parameters

IOPLL IP core parameter editan yana bayyana a cikin nau'in PLL na IP Catalog.

Siga	Darajar Shari'a	Bayani
Iyalin Na'ura	Intel Arria 10, Intel Cyclone 10 GX	Yana ƙayyade dangin na'urar.
Bangaren	—	Yana ƙayyade na'urar da aka yi niyya.
Saurin Sauri	—	Yana ƙayyadadden ƙimar gudun don na'urar da aka yi niyya.
Yanayin PLL	Integer-N PLL	Yana ƙayyade yanayin da aka yi amfani da shi don IOPLL IP core. Zaɓin doka kawai shine Integer-N PLL. Idan kuna buƙatar ɗan juzu'in PLL, dole ne kuyi amfani da fPLL Intel Arria 10/Cyclone 10 FPGA IP core.
Mitar Agogon Magana	—	Yana ƙayyade mitar shigarwa don agogon shigarwa, refclk, a cikin MHz. Tsohuwar ƙimar ita ce 100.0 MHz. Matsakaicin ƙima da matsakaicin ƙima ya dogara da na'urar da aka zaɓa.
Kunna Tashar Tashar Fitar da Kulle	Kunna ko Kashe	Kunna don kunna tashar tashar da aka kulle.
Kunna sigogin agogon fitarwa na zahiri	Kunna ko Kashe	Kunna don shigar da sigogi na PLL na zahiri maimakon tantance mitar agogon da ake so.
Yanayin Aiki	kai tsaye, martani na waje, al'ada, tushen daidaitacce, sifili jinkirta buffer, ko lvds	Yana ƙayyade aikin PLL. Tsohuwar aiki shine kai tsaye yanayin. • Idan ka zaɓi kai tsaye yanayin, PLL yana rage tsawon tsawon hanyar amsawa don samar da mafi ƙarancin jitter a cikin fitowar PLL. Ƙimar ciki da agogo na waje na PLL suna canzawa lokaci-lokaci dangane da shigar da agogon PLL. A cikin wannan yanayin, PLL ba zai rama kowane cibiyoyin sadarwa na agogo ba. • Idan ka zaɓi al'ada yanayin, PLL yana ramawa ga jinkirin cibiyar sadarwar agogon ciki da aka yi amfani da shi ta hanyar fitowar agogo. Idan kuma ana amfani da PLL don fitar da fil ɗin fitarwa na agogo na waje, canjin lokaci mai dacewa na siginar akan fitin fitarwa yana faruwa. • Idan ka zaɓi tushen daidaitacce yanayin, jinkirin agogo daga fil zuwa rijistar shigarwar I/O yayi daidai da jinkirin bayanai daga fil zuwa rijistar shigarwar I/O. • Idan ka zaɓi martani na waje yanayin, dole ne ku haɗa tashar shigar da fbclk zuwa fil ɗin shigarwa. Haɗin matakin allo dole ne ya haɗa fil ɗin shigarwa da tashar fitarwa na agogo na waje, fboutclk. Tashar fbclk tana daidaita da agogon shigarwa. • Idan ka zaɓi sifili jinkirta buffer yanayin, PLL dole ne ya ciyar da fitin fitarwa na agogo na waje kuma ya rama jinkirin da wannan fil ɗin ya gabatar. Siginar da aka gani akan fil yana aiki tare da agogon shigarwa. Fitowar agogon PLL yana haɗi zuwa tashar jiragen ruwa na altbidir kuma yana tafiyar da zdbfbclk azaman tashar fitarwa. Idan PLL kuma tana tafiyar da cibiyar sadarwar agogo ta ciki, canjin lokaci na wannan hanyar sadarwar yana faruwa. • Idan ka zaɓi lvds yanayin, bayanai iri ɗaya da alaƙar lokacin agogo na fil a cikin rajistar kamawa na SErdES na ciki ana kiyaye su. Yanayin yana ramawa jinkiri a cibiyar sadarwar agogon LVDS, da kuma tsakanin fil ɗin bayanai da na shigar da agogo zuwa hanyoyin rajistar kama SERDES.
Adadin agogo	1–9	Yana ƙayyade adadin agogon fitarwa da ake buƙata don kowace na'ura a cikin ƙirar PLL. Ana nuna saitunan da ake buƙata don mitar fitarwa, canjin lokaci, da zagayowar aiki bisa adadin agogon da aka zaɓa.
Ƙayyade Mitar VCO	Kunna ko Kashe	Yana ba ku damar taƙaita mitar VCO zuwa ƙayyadadden ƙimar. Wannan yana da amfani lokacin ƙirƙirar PLL don yanayin waje na LVDS, ko kuma idan ana son takamaiman girman matakin motsi mai ƙarfi.
ci gaba…

Siga	Darajar Shari'a	Bayani
Mitar VCO (1)	—	• Lokacin Kunna sigogin agogon fitarwa na zahiri An kunna - yana nuna mitar VCO dangane da ƙimar Mitar Agogon Magana, Abubuwan Haɓakawa (M-Counter), kuma Rarraba Factor (N-Counter). • Lokacin Kunna sigogin agogon fitarwa na zahiri an kashe - yana ba ku damar tantance ƙimar da ake buƙata don mitar VCO. Tsohuwar ƙimar ita ce 600.0 MHz.
Ba agogon duniya suna	Kunna ko Kashe	Yana ba ku damar sake suna sunan agogon fitarwa.
Sunan agogo	—	Sunan agogon mai amfani don Ƙuntataccen Ƙirar Ƙira (SDC).
Mitar da ake so	—	Yana ƙayyade mitar agogon fitarwa na tashar agogon fitarwa daidai, outclk[], a cikin MHz. Tsohuwar ƙimar ita ce 100.0 MHz. Matsakaicin ƙima da ƙima sun dogara da na'urar da aka yi amfani da ita. PLL tana karanta lambobi kawai a wurare shida na farko na goma.
Ainihin Mita	—	Yana ba ku damar zaɓar ainihin mitar agogon fitarwa daga jerin mitocin da za a iya cimmawa. Ƙimar tsoho ita ce mafi kusa da mitar da ake iya samu zuwa mitar da ake so.
Raka'a Shift na Mataki	ps or digiri	Yana ƙayyadad da sashin canjin lokaci don tashar agogon fitarwa mai dacewa, outclk[], a cikin picoseconds (ps) ko digiri.
Canjin Matakin da ake so	—	Yana ƙayyadadden ƙimar da ake buƙata don canjin lokaci. Tsohuwar ƙimar ita ce 0ps.
Ainihin Juyin Juya Hali	—	Yana ba ku damar zaɓar ainihin canjin lokaci daga lissafin ƙimar canjin lokaci da za a iya cimma. Ƙimar tsoho ita ce mafi kusancin tafiyar lokaci da ake iya cimmawa zuwa canjin lokaci da ake so.
Zagayowar Aikin da ake so	0.0–100.0	Yana ƙayyade ƙimar da ake buƙata don sake zagayowar aiki. Tsohuwar ƙimar ita ce 50.0%.
Zagayen Layi na Gaskiya	—	Yana ba ku damar zaɓar ainihin sake zagayowar ayyuka daga jerin ƙimar da'irar ayyuka da za a iya cimma. Ƙimar da ta dace ita ce mafi kusancin aikin da za a iya cimma zuwa zagayowar aikin da ake so.
Abubuwan Haɓakawa (M-Counter) (2)	4–511	Yana ƙayyadad da adadin yawan adadin M-counter. Matsakaicin doka na M counter shine 4-511. Koyaya, hane-hane akan mafi ƙarancin mitar PFD na doka da matsakaicin mitar VCO na doka suna taƙaita kewayon ƙidayar M zuwa 4-160.
Rarraba Factor (N-Counter) (2)	1–511	Yana ƙayyadad da rabon rabon N-counter. Matsakaicin doka na N counter shine 1-511. Koyaya, hane-hane akan mafi ƙarancin mitar PFD na doka yana taƙaita kewayon ingantattun kewayon N counter zuwa 1-80.
Rarraba Factor (C-Counter) (2)	1–511	Yana ƙayyadad da abubuwan rarraba don agogon fitarwa (C-counter).

1. Wannan siga yana samuwa kawai lokacin da Kunna sigogin agogo na zahiri na kashe.
2. Wannan siga yana samuwa kawai lokacin da Kunna sigogin agogo na zahiri na zahiri.

IOPLL IP Core Parameters - Saitunan Saituna

Tebur 2. IOPLL IP Core Parameters - Saitunan Saituna

Siga	Darajar Shari'a	Bayani
Saiti na Bandwidth PLL	Ƙananan, Matsakaici, ko Babban	Yana ƙayyadaddun saiti na bandwidth na PLL. Zaɓin tsoho shine Ƙananan.
PLL Sake saitin atomatik	Kunna ko Kashe	Ta atomatik sake saita PLL akan asarar kulle.
Ƙirƙiri shigarwa na biyu clk 'refclk1'	Kunna ko Kashe	Kunna don samar da agogon ajiyar da aka haɗe zuwa PLL ɗinku wanda zai iya canzawa tare da agogon tunani na asali.
Mitar Agogo Na Biyu	—	Yana zaɓar mitar siginar shigarwa na biyu. Tsohuwar ƙimar ita ce 100.0 MHz. Matsakaicin ƙima da matsakaicin ƙima ya dogara da na'urar da aka yi amfani da ita.
Ƙirƙiri siginar 'active_clk' don nuna agogon shigar da ake amfani da shi	Kunna ko Kashe	Kunna don ƙirƙirar fitarwa mai aiki. Fitarwa mai aiki yana nuna agogon shigarwa wanda PLL ke amfani da shi. Ƙananan siginar fitarwa yana nuna refclk kuma siginar fitarwa mai girma yana nuna refclk1.
Ƙirƙiri siginar 'clkbad' don kowane agogon shigarwa	Kunna ko Kashe	Kunna don ƙirƙirar abubuwan clkbad guda biyu, ɗaya don kowane agogon shigarwa. Ƙananan siginar fitarwa yana nuna agogon yana aiki kuma babban siginar fitarwa yana nuna agogon baya aiki.
Yanayin Sauyawa	Sauyawa ta atomatik, Canjawar hannu, ko Canjawa ta atomatik tare da Rufewar Manual	Yana ƙayyade yanayin sauyawa don aikace-aikacen ƙira. IP ɗin yana goyan bayan hanyoyin sauyawa guda uku: • Idan ka zaɓi Sauyawa ta atomatik yanayin, da'irar PLL tana lura da agogon tunani da aka zaɓa. Idan agogo ɗaya ya tsaya, da'irar tana canzawa ta atomatik zuwa agogon ajiya a cikin ƴan zagayowar agogo kuma tana ɗaukaka siginonin matsayi, clkbad da activeclk. • Idan ka zaɓi Canjawar hannu yanayin, lokacin da siginar sarrafawa, extswitch, ya canza daga babban tunani zuwa ƙananan hankali, kuma ya tsaya ƙasa don akalla zagayowar agogo uku, agogon shigarwa yana canzawa zuwa wancan agogon. Ana iya samar da extswitch daga ainihin ma'anar FPGA ko shigar da fil. • Idan ka zaɓa Canjawa ta atomatik tare da Rufewar Manual yanayin, lokacin da siginar extswitch yayi ƙasa, yana ƙetare aikin sauyawa ta atomatik. Muddin extswitch ya kasance ƙasa, ana toshe ƙarin aikin sauyawa. Don zaɓar wannan yanayin, tushen agogon ku biyu dole ne su kasance suna gudana kuma yawan agogon biyu ba zai iya bambanta da fiye da 20%. Idan duka agogon ba su kan mitar guda ɗaya ba, amma bambancin lokacin su yana cikin kashi 20%, toshe asarar agogo zai iya gano agogon da ya ɓace. Da alama PLL ta fita daga kulle bayan shigar da agogon PLL kuma yana buƙatar lokaci don sake kullewa.
Jinkirin Sauyawa	0–7	Yana ƙara takamaiman adadin jinkirin sake zagayowar zuwa tsarin sauyawa. Matsakaicin ƙima shine 0.
Samun dama ga PLL LVDS_CLK/ LOADEN tashar fitarwa	An kashe, Kunna LVDS_CLK/ LOKACI 0, ko Kunna LVDS_CLK/ LOADEN 0 & 1	Zaɓi Kunna LVDS_CLK/LOADEN 0 or Kunna LVDS_CLK/ LOADEN 0 & 1 don kunna PLL lvds_clk ko shigar da tashar fitarwa. Yana kunna wannan siga idan PLL tana ciyar da shingen LVDS SERDES tare da PLL na waje. Lokacin amfani da tashar jiragen ruwa na I/O PLL tare da tashar jiragen ruwa na LVDS, ana amfani da outclk [0..3] don lvds_clk [0,1] da lodawa [0,1] tashar jiragen ruwa, za a iya amfani da outclk4 don tashar jiragen ruwa na coreclk.
Kunna damar shiga tashar fitarwa ta PLL DPA	Kunna ko Kashe	Kunna don kunna tashar fitarwa ta PLL DPA.
ci gaba…

Siga	Darajar Shari'a	Bayani
Kunna damar zuwa tashar fitarwar agogon waje na PLL	Kunna ko Kashe	Kunna don kunna tashar fitarwa agogon PLL ta waje.
Yana ƙayyade abin da za a yi amfani da shi azaman tushen extclk_out[0].	C0 – C8	Yana ƙayyade tashar tashar tashar da za a yi amfani da ita azaman tushen extclk_out[0].
Yana ƙayyade abin da za a yi amfani da shi azaman tushen extclk_out[1].	C0 – C8	Yana ƙayyade tashar tashar tashar da za a yi amfani da ita azaman tushen extclk_out[1].

Cascading Tab

Tebur 3. IOPLL IP Core Parameters - Cascading Tab3

Siga	Darajar Shari'a	Bayani
Ƙirƙiri siginar 'cascade out' don haɗi tare da PLL na ƙasa	Kunna ko Kashe	Kunna don ƙirƙirar tashar jiragen ruwa na cascade_out, wanda ke nuna cewa wannan PLL tushen tushe ne kuma yana haɗi tare da inda ake nufi (ƙasa) PLL.
Yana ƙayyade abin da za a yi amfani da shi azaman tushen cascading	0–8	Yana ƙayyade tushen cascading.
Ƙirƙiri siginar adjpllin ko cclk don haɗi tare da PLL na sama	Kunna ko Kashe	Kunna don ƙirƙirar tashar shigar da bayanai, wanda ke nuna cewa wannan PLL makoma ce kuma tana haɗi tare da tushen (na sama) PLL.

Tab ɗin Sake daidaitawa mai ƙarfi

Tebur 4. IOPLL IP Core Parameters - Tabbataccen Sake Tsari Mai Tsayi

Siga	Darajar Shari'a	Bayani
Kunna sake fasalin PLL mai ƙarfi	Kunna ko Kashe	Kunna kunna ikon sake fasalin wannan PLL (a tare da PLL Reconfig Intel FPGA IP core).
Ba da damar samun dama ga mashigai masu motsi masu ƙarfi	Kunna ko Kashe	Kunna ba da damar mu'amalar canjin lokaci mai ƙarfi tare da PLL.
MIF Generation Option (3)	Ƙirƙira Sabon MIF File, Ƙara Kanfigareshan zuwa MIF na yanzu File, kuma Ƙirƙiri MIF File a lokacin IP Generation	Ko dai ƙirƙirar sabon .mif file dauke da tsarin I/O PLL na yanzu, ko ƙara wannan saitin zuwa .mif da ke akwai file. Kuna iya amfani da wannan .mif file yayin sake daidaitawa mai ƙarfi don sake saita I/O PLL zuwa saitunan sa na yanzu.
Hanyar zuwa Sabuwar MIF file (4)	—	Shigar da wurin kuma file sunan sabuwar .mif file da za a halitta.
Hanyar zuwa MIF na yanzu file (5)	—	Shigar da wurin kuma file sunan data kasance .mif file kuna nufin ƙara zuwa.
ci gaba…

1. Wannan siga yana samuwa ne kawai lokacin da Kunna sake daidaitawa mai ƙarfi na PLL.
2. Wannan siga yana samuwa ne kawai lokacin Ƙirƙirar Sabon MIF File an zaba azaman MIF Generation
   Zabin.

   Siga	Darajar Shari'a	Bayani
   Kunna Canjin Mataki Mai Sauƙi don Yawo na MIF (3)	Kunna ko Kashe	Kunna don adana kaddarorin canjin lokaci masu ƙarfi don sake fasalin PLL.
   Zaɓin Ma'aunin DPS (6)	C0-C8, Duk C, or M	Yana zaɓar ma'aunin ƙira don jujjuya canjin lokaci. M shine ma'aunin martani kuma C shine ma'aunin ma'auni.
   Yawan Juyin Juya Hali (6)	1–7	Yana zaɓin adadin ƙarin canje-canjen lokaci. Girman haɓaka juzu'i guda ɗaya yana daidai da 1/8 na lokacin VCO. Tsohuwar ƙimar ita ce 1.
   Hanyar Canjin Mataki Mai Tsanani (6)	M or Korau	Yana ƙayyade jagoran canjin lokaci mai ƙarfi don adanawa cikin PLL MIF.

3. Wannan sigar tana samuwa ne kawai lokacin Ƙara Kanfigareshan zuwa MIF mai wanzuwa File an zaba azaman MIF Generation Option

IOPLL IP Core Parameters - Babban Ma'auni Tab

Tebur 5. IOPLL IP Core Parameters - Advanced Parameters Tab

Siga	Darajar Shari'a	Bayani
Nagartattun Ma'auni	—	Yana nuna tebur na saitunan PLL na zahiri waɗanda za a aiwatar bisa ga shigar da ku.

Bayanin Aiki

• I/O PLL shine tsarin sarrafa mitoci wanda ke haifar da agogon fitarwa ta hanyar aiki tare da kanta zuwa agogon shigarwa. PLL yana kwatanta bambancin lokaci tsakanin siginar shigarwa da siginar fitarwa na voltage-controlled oscillator (VCO) sannan yana aiwatar da aiki tare na lokaci don kiyaye madaidaicin kusurwar lokaci (kulle) akan mitar shigarwa ko siginar tunani. Aiki tare ko madauki mara kyau na tsarin yana tilasta PLL ta kasance kulle-kulle.
• Kuna iya saita PLLs azaman masu haɓaka mitar mitoci, masu rarrabawa, masu rarrabawa, masu jan wuta, masu jan wuta, ko da'irorin dawo da agogo. Kuna iya amfani da PLLs don samar da mitoci masu tsayi, dawo da sigina daga tashar sadarwa mai hayaniya, ko rarraba siginonin agogo cikin ƙirarku.

Tubalan Ginin PLL

Babban tubalan I/O PLL sune mai gano mitar lokaci (PFD), famfo caji, tace madauki, VCO, da ƙididdiga, kamar ma'aunin martani (M), counter-sele counter (N), da bayan- ma'aunin ma'auni (C). Tsarin gine-ginen PLL ya dogara da na'urar da kuke amfani da ita a cikin ƙirar ku.

Wannan sigar tana samuwa ne kawai lokacin da Kunna Canjin Lokaci Mai Sauƙi don Yawo na MIF.

Yawan I/O PLL Architecture

• Ana amfani da waɗannan sharuɗɗan da yawa don bayyana halin PLL:
  Lokacin kulle PLL-wanda kuma aka sani da lokacin sayan PLL. Lokacin kulle PLL shine lokacin PLL don samun mitar manufa da dangantakar lokaci bayan haɓakawa, bayan canjin mitar fitarwa da aka tsara, ko bayan sake saitin PLL. Lura: Software na kwaikwaiyo baya yin ƙirar ainihin lokacin kulle PLL. Kwaikwayo yana nuna lokacin kullewa mara gaskiya. Don ainihin ƙayyadaddun lokacin kullewa, koma zuwa takaddar bayanan na'urar.
• Ƙaddamar PLL—mafi ƙarancin ƙimar ƙarar mitar PLL VCO. Adadin ragowa a cikin masu ƙidayar M da N suna ƙayyade ƙimar ƙudurin PLL.
• PLL sampdarajar - FREF sampmitar ling da ake buƙata don yin lokaci da gyaran mita a cikin PLL. Farashin PLLsampMatsakaicin adadin shine fREF/N.

Kulle PLL

Kulle PLL ya dogara da siginar shigarwa guda biyu a cikin mai gano mitar lokaci. Siginar kulle fitowar asynchronous ce ta PLLs. Adadin zagayowar da ake buƙata don ƙofar siginar kulle ya dogara da agogon shigarwar PLL wanda ke agogon kewayawar kulle-kulle. Raba matsakaicin lokacin kulle PLL ta lokacin agogon shigarwar PLL don ƙididdige adadin zagayowar agogon da ake buƙata don ƙofar siginar kulle.

Hanyoyin Aiki

IOPLL IP core yana goyan bayan yanayin amsa agogo daban-daban guda shida. Kowane yanayi yana ba da damar haɓaka agogo da rarrabuwa, canjin lokaci, da shirye-shiryen sake zagayowar aiki.

Agogon fitarwa

• IOPLL IP core na iya samar da siginonin fitarwa har zuwa agogo tara. Fitowar agogon da aka samar yana sigina agogon tsakiya ko tubalan waje a wajen ainihin.
• Zaka iya amfani da siginar sake saitin don sake saita ƙimar agogon fitarwa zuwa 0 kuma ka kashe agogon fitarwar PLL.
• Kowane agogon fitarwa yana da saitin saitin da ake buƙata inda zaku iya ƙididdige ƙimar da ake so don mitar fitarwa, canjin lokaci, da zagayowar aiki. Saitunan da ake so sune saitunan da kuke son aiwatarwa a cikin ƙirar ku.
• Haƙiƙanin ƙimar mitar, canjin lokaci, da sake zagayowar aiki sune saitunan mafi kusa (mafi kyawun kusan saitunan da ake so) waɗanda za'a iya aiwatarwa a cikin da'irar PLL.

Reference Clock Switchover

Siffar sauya agogon tunani yana ba PLL damar canzawa tsakanin agogon shigar da bayanai guda biyu. Yi amfani da wannan fasalin don sake aikin agogo, ko don aikace-aikacen yanki na agogo biyu kamar a cikin tsari. Na'urar na iya kunna agogon da ba ta da yawa idan agogon farko ya daina aiki.
Yin amfani da fasalin sauya agogon tunani, zaku iya ƙididdige mitar agogon shigarwa na biyu, sannan zaɓi yanayin da jinkiri don sauyawa.

Gano hasarar agogo da toshewar agogo yana da ayyuka masu zuwa:

• Yana lura da matsayin agogon tunani. Idan agogon tunani ya gaza, agogon yana canzawa ta atomatik zuwa tushen shigar da agogon baya. Agogon yana sabunta matsayin clkbad da sigina masu aiki don faɗakar da taron.
• Yana juya agogon tunani baya da gaba tsakanin mitoci daban-daban guda biyu. Yi amfani da siginar extswitch don sarrafa aikin sauyawa da hannu. Bayan an sami canji, PLL na iya rasa kullewa na ɗan lokaci kuma ta bi tsarin lissafin.

PLL-zuwa-PLL Cascading

Idan kun jefar da PLLs a cikin ƙirar ku, tushen (na sama) PLL dole ne ya kasance yana da saitunan ƙaramar bandwidth, yayin da wurin (ƙasa) PLL dole ne ya sami saitin bandwidth mai girma. Lokacin cascading, fitowar tushen PLL yana aiki azaman agogon tunani (shigarwa) na PLL. Saitunan bandwidth na PLLs da aka caje dole ne su bambanta. Idan saitunan bandwidth na PLLs ɗin da aka caje iri ɗaya ne, PLLs ɗin na iya ampinganta hayaniyar lokaci a wasu mitoci. Ana amfani da tushen shigarwar agogon adjpllin don tsaka-tsaki tsakanin PLLs masu ɓarna.

Tashoshi

Tebur 6. IOPLL IP Core Ports

Siga	Nau'in	Sharadi	Bayani
refclk	Shigarwa	Da ake bukata	Tushen agogon tunani wanda ke tafiyar da I/O PLL.
na farko	Shigarwa	Da ake bukata	Tashar tashar sake saitin asynchronous don agogon fitarwa. Fitar da wannan tashar jiragen ruwa sama don sake saita duk agogon fitarwa zuwa ƙimar 0. Dole ne ku haɗa wannan tashar jiragen ruwa zuwa siginar sarrafa mai amfani.
fbclk	Shigarwa	Na zaɓi	Tashar shigar da martani na waje don I/O PLL. IOPLL IP core yana ƙirƙira wannan tashar jiragen ruwa lokacin da I/O PLL ke aiki a cikin yanayin martani na waje ko yanayin buffer-sifiri. Don kammala madauki na martani, haɗin matakin allo dole ne ya haɗa tashar fbclk da tashar fitar da agogon waje na I/O PLL.
fboutclk	Fitowa	Na zaɓi	Tashar jiragen ruwa da ke ciyar da tashar fbclk ta hanyar mimic circuitry. Ana samun tashar tashar fboutclk kawai idan I/O PLL yana cikin yanayin martani na waje.
zdbfbclk	Bidire	Na zaɓi	Tashar tashar jiragen ruwa guda biyu wacce ke haɗuwa da kewayar mimic. Dole ne wannan tashar jiragen ruwa ta haɗa zuwa fil ɗin bidirectional wanda aka sanya akan ingantaccen ra'ayin da aka keɓe na fitin fitarwa na I/O PLL. Ana samun tashar tashar zdbfbclk kawai idan I/O PLL yana cikin yanayin buffer sifili. Don guje wa tunanin sigina lokacin amfani da yanayin ɓoyayyen sifili, kar a sanya alamun allo akan finin I/O na biyu.
kulle	Fitowa	Na zaɓi	IOPLL IP core yana motsa wannan tashar jiragen ruwa lokacin da PLL ta sami kulle. Tashar tashar jiragen ruwa ta kasance babba muddin IOPLL yana kulle. I/O PLL yana tabbatar da tashar tashar da aka kulle lokacin da matakai da mitoci na agogon tunani da agogon martani sune
ci gaba…

Siga	Nau'in	Sharadi	Bayani
			iri ɗaya ko a cikin haƙurin da'ira na kullewa. Lokacin da bambanci tsakanin siginonin agogo biyu ya zarce juriyar da'irar kulle, I/O PLL ya rasa kullewa.
refclk1	Shigarwa	Na zaɓi	Tushen agogo na biyu wanda ke tafiyar da I/O PLL don fasalin sauya agogo.
extswitch	Shigarwa	Na zaɓi	Sanya siginar extswitch low (1'b0) don aƙalla zagayowar agogo 3 don canza agogo da hannu.
aiki clk	Fitowa	Na zaɓi	Siginar fitarwa don nuna wace tushen agogon tunani ke amfani da I/O PLL.
klkbad	Fitowa	Na zaɓi	Sigina na fitarwa wanda ke nuna matsayin tushen agogo yana da kyau ko mara kyau.
cascade_out	Fitowa	Na zaɓi	Sigina na fitarwa wanda ke ciyarwa zuwa I/O PLL na ƙasa.
adjpllin	Shigarwa	Na zaɓi	Siginar shigar da ke ciyarwa daga sama I/O PLL.
fita_[]	Fitowa	Na zaɓi	Agogon fitarwa daga I/O PLL.

IOPLL Intel FPGA IP Core Rukunin Jagorar Mai Amfani

Idan ba a jera sigar ainihin IP ba, jagorar mai amfani don sigar ainihin IP ta baya tana aiki

IP Core Version	Jagorar Mai Amfani
17.0	Altera I/O Madaidaicin Madaidaicin Matsayi (Altera IOPLL) Jagorar Mai Amfani na IP
16.1	Altera I/O Madaidaicin Madaidaicin Matsayi (Altera IOPLL) Jagorar Mai Amfani na IP
16.0	Altera I/O Madaidaicin Madaidaicin Matsayi (Altera IOPLL) Jagorar Mai Amfani na IP
15.0	Altera I/O Madaidaicin Madaidaicin Matsayi (Altera IOPLL) Jagorar Mai Amfani na IP

Tarihin Bita daftarin aiki don IOPLL Intel FPGA IP Core User Guide

Sigar Takardu	Intel Quartus® Babban Sigar	Canje-canje
2019.06.24	18.1	An sabunta bayanin don shigar da agogon sadaukarwa a cikin Yawan I/O PLL Architecture zane.
2019.01.03	18.1	• An sabunta ta Samun dama ga PLL LVDS_CLK/LOADEN tashar fitarwa siga a cikin IOPLL IP Core Parameters - Saitunan Saituna tebur. • An sabunta bayanin tashar tashar zdbfbclk a cikin IOPLL IP Core Ports tebur.
2018.09.28	18.1	• Gyara bayanin extswitch a cikin IOPLL IP Core Ports tebur. • Sake suna na waɗannan nau'ikan IP masu zuwa kamar yadda Intel rebranding: - Canza Altera IOPLL IP core zuwa IOPLL Intel FPGA IP core. - Canza Altera PLL Reconfig IP core zuwa PLL Reconfig Intel FPGA IP core. - Canza Arria 10 FPLL IP core zuwa fPLL Intel Arria 10/Cyclone 10 FPGA IP core.

Kwanan wata	Sigar	Canje-canje
Yuni 2017	2017.06.16	• Ƙara tallafi don na'urorin Intel Cyclone 10 GX. • Sake suna a matsayin Intel.
Disamba 2016	2016.12.05	An sabunta bayanin tashar tashar farko ta ainihin IP.
Yuni 2016	2016.06.23	• Abubuwan da aka sabunta IP Core Parameter - Tebur na Saituna. - An sabunta bayanin don Canjawar Manual da Sauyawa ta atomatik tare da sigogin Sauke Manual. Siginar sarrafa agogon agogo baya aiki kaɗan. - An sabunta bayanin don sigar Jinkirin Sauyawa. • Ƙididdigar M da C don ma'aunin Zaɓin Counter na DPS a cikin Matsalolin Mahimmancin IP - Teburin Sake daidaitawa mai ƙarfi. • Canja sunan tashar tashar jiragen ruwa mai sauya agogo daga clkswitch zuwa extswitch a cikin Tsarin Tsarin I/O PLL na Al'ada.
Mayu 2016	2016.05.02	Abubuwan da aka sabunta IP Core Parameters - Teburin sake daidaitawa mai ƙarfi.
Mayu 2015	2015.05.04	An sabunta bayanin don Ƙaddamar da damar zuwa PLL LVDS_CLK/LOADEN siginar tashar fitarwa a cikin IP Core Parameters - Tebur na Saituna. An ƙara hanyar haɗi zuwa Mutuwar Siginar Tsakanin Altera IOPLL da Altera LVDS SERDES IP Cores tebur a cikin I/O da Babban Gudun I/O a cikin Arria 10 Babin Na'urori.
Agusta 2014	2014.08.18	Sakin farko.

Takardu / Albarkatu

intel UG-01155 IOPLL FPGA IP Core [pdf] Jagorar mai amfani UG-01155 IOPLL FPGA IP Core, UG-01155, IOPLL FPGA IP Core, FPGA IP Core

Magana

• Manual mai amfani