Intel UG-01155 IOPLL FPGA IP Core
Zasinthidwa kwa Intel® Quartus® Prime Design Suite: 18.1
IOPLL Intel® FPGA IP Core User Guide
IOPLL Intel® FPGA IP core imakulolani kuti musinthe zosintha za Intel Arria® 10 ndi Intel Cyclone® 10 GX I/O PLL.
IOPLL IP core imathandizira izi:
- Imathandizira mitundu isanu ndi umodzi yoyankha mawotchi: achindunji, mayankho akunja, abwinobwino, magwero osakanikirana, zero kuchedwa buffer, ndi mawonekedwe a LVDS.
- Amapanga ma siginecha opitilira 10 otuluka pazida za Intel Arria 10 ndi Intel CycloneM XNUMX GX.
- Kusintha pakati pa mawotchi awiri olowera.
- Imathandizira zolowetsa zapafupi ndi PLL (adjpllin) kuti zilumikizane ndi PLL yakumtunda mumayendedwe a PLL.
- Amapanga Memory Initialization File (.mif) ndipo imalola PLL dynamicVreconfiguration.
- Imathandizira kusintha kwa gawo la PLL.
Zambiri Zogwirizana
- Chiyambi cha Intel FPGA IP Cores
Amapereka zambiri za Intel FPGA IP cores ndi parameter editor. - Njira zogwirira ntchito patsamba 9
- Mawotchi Otulutsa patsamba 10
- Reference Clock Switchover patsamba 10
- Kutulutsa kwa PLL-to-PLL patsamba 11
- IOPLL Intel FPGA IP Core User Guide Archives patsamba 12
Imapereka mndandanda wazowongolera zamagwiritsidwe akale a IOPLL Intel FPGA IP core.
Chipangizo Thandizo la Banja
IOPLL IP core imangothandizira mabanja a Intel Arria 10 ndi Intel Cyclone 10 GX.
IOPLL IP Core Parameters
The IOPLL IP core parameter editor imapezeka mu gulu la PLL la IP Catalog.
| Parameter | Mtengo Walamulo | Kufotokozera |
| Chipangizo Banja | Intel Arria 10, Intel
Cyclone 10 GX |
Imatchula banja la chipangizocho. |
| Chigawo | — | Imatchula chipangizo chomwe mukufuna. |
| Liwiro la Gulu | — | Imatchula liwiro la chipangizo chomwe mukufuna. |
| Njira ya PLL | Nambala-N PLL | Imatchula njira yomwe imagwiritsidwa ntchito pa IOPLL IP core. Kusankhidwa kovomerezeka kokha ndiko Chiwerengero cha Integer-N PLL. Ngati mukufuna PLL yochepa, muyenera kugwiritsa ntchito fPLL Intel Arria 10/Cyclone 10 FPGA IP pachimake. |
| Mafupipafupi a Clock Clock | — | Imatchula kuchuluka kwa wotchi yolowera, refclk, mu MHz. Mtengo wokhazikika ndi 100.0 MHz. Mtengo wocheperako komanso wapamwamba kwambiri umadalira chipangizo chosankhidwa. |
| Yambitsani Port Locked Output Port | Yatsani kapena Zimitsani | Yatsani kuti mutsegule doko lokhoma. |
| Yambitsani magawo a wotchi yotulutsa | Yatsani kapena Zimitsani | Yatsani kuti mulowetse magawo owerengera a PLL m'malo motchula ma frequency omwe mukufuna. |
| Operation Mode | mwachindunji, ndemanga zakunja, zabwinobwino, gwero synchronous, zero kuchedwa buffer, kapena lvs ndi | Imatchula ntchito ya PLL. Ntchito yokhazikika ndi mwachindunji
mode. • Ngati inu kusankha mwachindunji mode, PLL imachepetsa kutalika kwa njira yoyankhira kuti ipange jitter yaying'ono kwambiri pa zotsatira za PLL.Zotsatira zamkati-wotchi ndi kunja-wotchi zotuluka za PLL zimasinthidwa ndi gawo pokhudzana ndi kulowetsa kwa wotchi ya PLL. Munjira iyi, PLL silipira ma network aliwonse. • Ngati inu kusankha zabwinobwino mode, PLL imalipira kuchedwa kwa mawotchi amkati omwe amagwiritsidwa ntchito ndi kutulutsa koloko. Ngati PLL imagwiritsidwanso ntchito kuyendetsa pini yotulutsa wotchi yakunja, kusintha kofananira kwa chizindikiro pa pini yotulutsa kumachitika. • Ngati inu kusankha gwero synchronous Mode, kuchedwa kwa wotchi kuchoka pa pin kupita ku regista ya I/O kumagwirizana ndi kuchedwa kwa data kuchokera pa pin kupita ku register ya I/O. • Ngati inu kusankha ndemanga zakunja mode, muyenera kulumikiza cholowera cha fbclk ku pini yolowera. Kulumikizana kwapagulu kuyenera kulumikiza pini yolowera ndi doko lakunja lotulutsa wotchi, fboutclk. Doko la fbclk limagwirizana ndi wotchi yolowera. • Ngati inu kusankha zero kuchedwa buffer mode, PLL iyenera kudyetsa pini yotulutsa wotchi yakunja ndikubwezera kuchedwa komwe kunayambitsidwa ndi piniyo. Chizindikiro chomwe chimawonedwa pa pini chimalumikizidwa ndi wotchi yolowera. Kutulutsa kwa wotchi ya PLL kumalumikizana ndi doko la altbidir ndikuyendetsa zdbfbclk ngati doko lotulutsa. Ngati PLL imayendetsanso netiweki yamkati ya wotchi, kusintha kofananira kwa netiweki kumachitika. • Ngati inu kusankha lvs ndi Mawonekedwe, deta yofananira ndi ubale wa nthawi ya wotchi ya zikhomo mkati mwa zolembera zamkati za SEDES zimasungidwa. Njirayi imathandizira kuchedwa kwa netiweki ya wotchi ya LVDS, komanso pakati pa pini ya data ndi pini yolowetsa wotchi kupita kunjira zolembetsera SERDES. |
| Nambala ya Mawotchi | 1–9 | Imatchula kuchuluka kwa mawotchi omwe amafunikira pa chipangizo chilichonse pamapangidwe a PLL. Zokonda zomwe zapemphedwa za ma frequency otulutsa, kusintha kwa gawo, ndi kuzungulira kwa ntchito zikuwonetsedwa kutengera kuchuluka kwa mawotchi osankhidwa. |
| Tchulani pafupipafupi VCO | Yatsani kapena Zimitsani | Imakulolani kuti muchepetse ma frequency a VCO pamtengo womwe watchulidwa. Izi ndizothandiza popanga PLL yamawonekedwe akunja a LVDS, kapena ngati gawo linalake losinthira gawo likufunidwa. |
| anapitiriza… | ||
| Parameter | Mtengo Walamulo | Kufotokozera |
| Kusintha kwa mtengo wa VCO (1) | — | • Liti Yambitsani magawo a wotchi yotulutsa imayatsidwa- imawonetsa ma frequency a VCO kutengera zomwe zili Mafupipafupi a Clock Clock, Multiply Factor (M-Counter),ndi Gawani Factor (N-Counter).
• Liti Yambitsani magawo a wotchi yotulutsa yazimitsidwa- imakupatsani mwayi kuti mutchule mtengo womwe wapemphedwa pama frequency a VCO. Mtengo wokhazikika ndi 600.0 MHz. |
| Perekani dzina ladziko lonse la wotchi | Yatsani kapena Zimitsani | Limakupatsani kutchula dzina linanena bungwe wotchi. |
| Dzina la Wotchi | — | Dzina la wotchi ya Synopsis Design Constraints (SDC). |
| Kufuna pafupipafupi | — | Imatchula mafupipafupi a wotchi yotuluka padoko lofananira, outclk[], mu MHz. Mtengo wokhazikika ndi 100.0 MHz. Zochepa komanso zotsika kwambiri zimadalira chipangizo chogwiritsidwa ntchito. PLL imangowerenga manambala m'malo asanu ndi limodzi oyamba. |
| Nthawi Yeniyeni | — | Imakulolani kuti musankhe ma frequency enieni a wotchi kuchokera pamndandanda wamafuriji otheka. Mtengo wosasinthika ndiwoyandikira kwambiri kufikika kwa ma frequency omwe mukufuna. |
| Magawo a Phase Shift | ps or madigiri | Imatchula gawo losinthira gawo la doko lofananira la wotchi,
outclk[], mu picoseconds (ps) kapena madigiri. |
| Desired Phase Shift | — | Imatchula mtengo womwe wapemphedwa pakusintha kwagawo. Mtengo wokhazikika ndi
0 masalimo. |
| Yeniyeni Phase Shift | — | Zimakulolani kuti musankhe kusintha kwenikweni kwa gawo kuchokera pamndandanda wazomwe mungakwaniritse. Mtengo wosasinthika ndiye gawo loyandikira kwambiri lomwe lingatheke kufika pagawo lomwe mukufuna. |
| Desired Duty Cycle | 0.0–100.0 | Imatchula mtengo womwe wapemphedwa wanthawi yantchito. Mtengo wokhazikika ndi
50.0%. |
| Yeniyeni Duty Cycle | — | Zimakulolani kuti musankhe zochita zenizeni kuchokera pamndandanda wazomwe mungakwaniritse. Mtengo wokhazikika ndiwo ntchito yomwe ingatheke kuyandikira nthawi yomwe mukufuna. |
| Multiply Factor (M-Counter)
(2) |
4–511 | Imatchula kuchuluka kwa M-counter.
Mitundu yovomerezeka ya M counter ndi 4-511. Komabe, zoletsa pamafupipafupi ovomerezeka a PFD komanso kuchuluka kwalamulo kwa VCO kumalepheretsa kuwerengera kwa M kukhala 4-160. |
| Gawani Factor (N-Counter) (2) | 1–511 | Imatchula gawo la magawo a N-counter.
Mitundu yovomerezeka ya kauntala ya N ndi 1-511. Komabe, zoletsa pamafupipafupi ovomerezeka a PFD amaletsa kuchuluka kwa kauntala ya N mpaka 1-80. |
| Gawani Factor (C-Counter) (2) | 1–511 | Imatchula gawo la wotchi yotulutsa (C-counter). |
- Izi zimangopezeka pamene Yambitsani zotuluka za wotchi yazimitsidwa.
- Izi zimangopezeka pamene Yambitsani magawo a wotchi yakuthupi yayatsidwa.
IOPLL IP Core Parameters - Zikhazikiko Tab
Table 2. IOPLL IP Core Parameters - Tabu ya Zikhazikiko
| Parameter | Mtengo Walamulo | Kufotokozera |
| PLL Bandwidth Preset | Zochepa, Wapakati, kapena Wapamwamba | Imatchula makonda a PLL bandwidth preset. Kusankha kosasintha ndi
Zochepa. |
| PLL Auto Bwezerani | Yatsani kapena Zimitsani | Ingodzikhazikitsani nokha PLL ikatayika loko. |
| Pangani cholowa chachiwiri clk 'refclk1' | Yatsani kapena Zimitsani | Yatsani kuti mupereke wotchi yosunga zobwezeretsera yolumikizidwa ku PLL yanu yomwe ingasinthe ndi wotchi yanu yoyambira. |
| Nthawi Yachiwiri Yolozera Wotchi | — | Imasankha kuchuluka kwa chizindikiro cha wotchi yachiwiri. Mtengo wokhazikika ndi 100.0 MHz. Mtengo wocheperako komanso wapamwamba kwambiri umadalira chipangizo chomwe chimagwiritsidwa ntchito. |
| Pangani chizindikiro cha 'active_clk' kuti muwonetse wotchi yolowera yomwe ikugwiritsidwa ntchito | Yatsani kapena Zimitsani | Yatsani kuti mupange activeclk output. Zotulutsa activeclk zikuwonetsa wotchi yolowera yomwe ikugwiritsidwa ntchito ndi PLL. Kutsika kwa chizindikiro kumawonetsa refclk ndi kuchuluka kwa siginecha kukuwonetsa refclk1. |
| Pangani chizindikiro cha 'clkbad' pa wotchi iliyonse yolowetsamo | Yatsani kapena Zimitsani | Yatsani kuti mupange zotulutsa ziwiri za clkbad, imodzi pa wotchi iliyonse yolowetsa. Kutsika kwa chizindikiro kumasonyeza kuti wotchi ikugwira ntchito ndipo chizindikiro chokwera chimasonyeza kuti wotchiyo sikugwira ntchito. |
| Switchover Mode | Kusintha kwa Automatic, Manual Switchover, kapena Automatic Switchover yokhala ndi Kulemba Pamanja | Imatchulanso masinthidwe amomwe amagwirira ntchito. IP imathandizira mitundu itatu yosinthira:
• Ngati inu kusankha Kusintha kwa Automatic mode, PLL yozungulira imayang'anira wotchi yosankhidwa. Wotchi imodzi ikayima, wotchiyo imangosintha kupita ku wotchi yosunga zobwezeretsera pamawotchi angapo ndikusinthira ma siginecha, clkbad ndi activeclk. • Ngati inu kusankha Manual Switchover mawonekedwe, pomwe chizindikiro chowongolera, chosinthira, chikusintha kuchoka pamalingaliro kupita ku logic yotsika, ndikukhalabe otsika kwa mawotchi osachepera atatu, wotchi yolowera imasinthira ku wotchi ina. Extswitch ikhoza kupangidwa kuchokera ku FPGA core logic kapena pini yolowetsa. • Ngati mwasankha Automatic Switchover yokhala ndi Kulemba Pamanja mode, pamene chizindikiro cha extswitch chili chochepa, chimaposa ntchito yosinthira yokha. Malingana ngati extswitch ikadali yotsika, kusintha kwina kumatsekedwa. Kuti musankhe mawonekedwe awa, mawotchi anu awiri a wotchi ayenera kukhala akuthamanga ndipo mawotchi awiriwa sangasiyane ndi 20%. Ngati mawotchi onsewa sali pafupipafupi, koma kusiyana kwa nthawi kuli mkati mwa 20%, chotchinga chozindikira kutayika kwa wotchi chimatha kuzindikira wotchi yotayika. PLL nthawi zambiri imatuluka pakhoma pambuyo pa kusintha kwa wotchi ya PLL ndipo imafunika nthawi yotsekanso. |
| Kuchedwa kwa Switchover | 0–7 | Imawonjezera kuchuluka kwa kuchedwetsa kwa mkombero kunjira yosinthira. Mtengo wokhazikika ndi 0. |
| Kufikira ku doko la PLL LVDS_CLK/ LOADEN | Wolumala, Yambitsani LVDS_CLK/ KULIMBITSA 0, kapena
Yambitsani LVDS_CLK/ TULANI 0 & 1 |
Sankhani Yambitsani LVDS_CLK/LOADEN 0 or Yambitsani LVDS_CLK/ LOADEN 0 & 1 kuti mutsegule PLL lvds_clk kapena doko lotulutsa. Imayatsa gawoli ngati PLL idyetsa chipika cha LVDS SERDES ndi PLL yakunja.
Mukamagwiritsa ntchito madoko a I/O PLL outclk okhala ndi madoko a LVDS, outclk[0..3] amagwiritsidwa ntchito pa lvds_clk[0,1] ndi loaden [0,1] madoko, outclk4 ingagwiritsidwe ntchito pamadoko a coreclk. |
| Yambitsani mwayi wofikira kudoko la PLL DPA | Yatsani kapena Zimitsani | Yatsani kuti mutsegule doko la PLL DPA. |
| anapitiriza… | ||
| Parameter | Mtengo Walamulo | Kufotokozera |
| Yambitsani mwayi wofikira kudoko lakunja la wotchi ya PLL | Yatsani kapena Zimitsani | Yatsani kuti mutsegule doko la PLL lakunja lotulutsa wotchi. |
| Imatchula outclk yomwe ingagwiritsidwe ntchito ngati gwero la extclk_out[0] | C0 – C8 | Imatchula doko la outclk kuti ligwiritsidwe ntchito ngati gwero la extclk_out[0]. |
| Imatchula outclk yomwe ingagwiritsidwe ntchito ngati gwero la extclk_out[1] | C0 – C8 | Imatchula doko la outclk kuti ligwiritsidwe ntchito ngati gwero la extclk_out[1]. |
Cascading Tab
Table 3. IOPLL IP Core Parameters - Cascading Tab3
| Parameter | Mtengo Walamulo | Kufotokozera |
| Pangani chizindikiro cha 'cascade out' kuti mugwirizane ndi PLL yotsika | Yatsani kapena Zimitsani | Yatsani kuti mupange cascade_out port, zomwe zikuwonetsa kuti PLL iyi ndi gwero ndipo imalumikizana ndi kopita (kumunsi) PLL. |
| Imatchula outclk yoti igwiritsidwe ntchito ngati gwero la cascading | 0–8 | Imatchula gwero la cascading. |
| Pangani chizindikiro cha adjpllin kapena cclk kuti mulumikizane ndi PLL yakumtunda | Yatsani kapena Zimitsani | Yatsani kuti mupange doko lolowera, zomwe zikuwonetsa kuti PLL iyi ndi kopita ndipo imalumikizana ndi gwero (kumtunda) PLL. |
Dynamic Reconfiguration Tab
Table 4. IOPLL IP Core Parameters - Dynamic Reconfiguration Tab
| Parameter | Mtengo Walamulo | Kufotokozera |
| Yambitsani kusinthanso kwamphamvu kwa PLL | Yatsani kapena Zimitsani | Yatsani kuyatsa kukonzanso kwamphamvu kwa PLL iyi (mogwirizana ndi PLL Reconfig Intel FPGA IP core). |
| Yambitsani mwayi wofikira ku madoko osinthira magawo | Yatsani kapena Zimitsani | Yatsani kuyatsa mawonekedwe a dynamic phase shift ndi PLL. |
| MIF Generation Option (3) | Pangani MIF yatsopano File, Onjezani Kusintha kwa MIF yomwe ilipo File,ndi Pangani MIF File pa IP Generation | Kapena pangani .mif yatsopano file zomwe zili ndi kasinthidwe kamakono ka I/O PLL, kapena onjezerani izi ku .mif yomwe ilipo file. Mutha kugwiritsa ntchito izi .mif file pakusinthanso kwamphamvu kuti mukonzenso I/O PLL kumayendedwe ake apano. |
| Njira yopita ku MIF Yatsopano file (4) | — | Lowani malo ndi file dzina la latsopano .mif file kulengedwa. |
| Njira yopita ku MIF yomwe ilipo file (5) | — | Lowani malo ndi file dzina la omwe alipo .mif file mukufuna kuwonjezera. |
| anapitiriza… | ||
- Izi zimangopezeka pamene Yambitsani kusinthanso kwamphamvu kwa PLL kuyatsa.
- Parameter iyi imapezeka pokhapokha Pangani MIF Yatsopano File imasankhidwa ngati MIF Generation
Njira.Parameter Mtengo Walamulo Kufotokozera Yambitsani Dynamic Phase Shift kuti MIF ikukhamukira (3) Yatsani kapena Zimitsani Yatsani kuti musunge zinthu zosinthira magawo kuti mukonzenso PLL. DPS Counter Selection (6) C0–C8, Zonse C, or M
Imasankha kauntala kuti isinthe magawo osinthika. M ndiye kauntala ya mayankho ndipo C ndi zowerengera za post-scale. Chiwerengero cha Zosintha Zamphamvu (6) 1–7 Imasankha kuchuluka kwa magawo osinthika. Kukula kwa gawo limodzi losinthira kuwonjezereka kuli kofanana ndi 1/8 ya nthawi ya VCO. Mtengo wokhazikika ndi 1. Dynamic Phase Shift Direction (6) Zabwino or Zoipa
Imasankha njira yosinthira magawo kuti isungidwe mu PLL MIF. - Gawoli limapezeka pokhapokha Onjezani Kusintha kwa MIF yomwe ilipo File imasankhidwa ngati MIF Generation Option
IOPLL IP Core Parameters - Advanced Parameters Tab
Table 5. IOPLL IP Core Parameters - Advanced Parameters Tab
| Parameter | Mtengo Walamulo | Kufotokozera |
| Ma Parameters apamwamba | — | Imawonetsa tebulo la zoikamo za PLL zomwe zidzakhazikitsidwa malinga ndi zomwe mwalemba. |
Kufotokozera Kwantchito
- I/O PLL ndi makina owongolera pafupipafupi omwe amapanga wotchi yotulutsa podzigwirizanitsa ndi wotchi yolowera. PLL imafanizira kusiyana kwa gawo pakati pa siginecha yolowera ndi chizindikiro chotulutsa cha voltage-controlled oscillator (VCO) ndiyeno amalumikizana ndi gawo kuti azikhala ndi gawo lokhazikika (loko) pafupipafupi pakulowetsa kapena chizindikiro. Kulumikizana kapena kusokoneza maganizo kwadongosolo kumakakamiza PLL kuti ikhale yotsekedwa.
- Mutha kusintha ma PLL ngati ochulukitsa pafupipafupi, ogawa, ma demodulators, majenereta otsata, kapena mabwalo obwezeretsa mawotchi. Mutha kugwiritsa ntchito ma PLL kupanga ma frequency okhazikika, kubwezeretsanso ma siginecha kuchokera panjira yaphokoso, kapena kugawa mawotchi pamapangidwe anu.
Zomangamanga za PLL
Mipiringidzo yayikulu ya I/O PLL ndi gawo la frequency detector (PFD), pampu yojambulira, loop filter, VCO, ndi zowerengera, monga chowerengera cha mayankho (M), chowerengera choyambirira (N), ndi positi- zowerengera zowerengera (C). Zomangamanga za PLL zimatengera chipangizo chomwe mumagwiritsa ntchito pakupanga kwanu.
Izi zimangopezeka pamene Yambitsani Dynamic Phase Shift ya MIF Streaming yayatsidwa.
Zomangamanga za I/O PLL
- Mawu otsatirawa amagwiritsidwa ntchito kufotokoza khalidwe la PLL:
Nthawi yotseka ya PLL-yomwe imadziwikanso kuti nthawi yopezera PLL. Nthawi yotsekera ya PLL ndi nthawi yoti PLL ipeze ma frequency omwe mukufuna komanso ubale wagawo pambuyo pokweza mphamvu, pambuyo pakusintha kwanthawi yayitali, kapena kukonzanso kwa PLL. Chidziwitso: Mapulogalamu oyeserera satengera nthawi yotseka ya PLL. Kuyerekeza kumawonetsa nthawi yotseka mwachangu mopanda kutero. Kuti mudziwe zenizeni za nthawi yotseka, onani tsatanetsatane wa chipangizocho. - Kusintha kwa PLL - mtengo wocheperako pafupipafupi wa PLL VCO. Chiwerengero cha ma bits mu zowerengera za M ndi N zimatsimikizira mtengo wa PLL.
- Chithunzi cha PLLampmtengo - FREF sampma frequency ofunikira kuti apange gawo ndi kuwongolera pafupipafupi mu PLL. Chithunzi cha PLLampmtengo ndi fREF/N.
PLL Lock
Chotsekera cha PLL chimadalira ma siginecha awiri olowera mu chowunikira pafupipafupi. Chizindikiro chotsekera ndi kutulutsa kosasinthika kwa ma PLL. Kuchuluka kwa mikombero yofunikira kuti mutsegule chizindikiro chotseka kumadalira wotchi yolowera ya PLL yomwe imawotchi yotchinga-lock-lock. Gawani nthawi yotseka kwambiri ya PLL ndi nthawi ya wotchi yolowera ya PLL kuti muwerenge kuchuluka kwa mawotchi ofunikira kuti mutsegule chizindikiro chotseka.
Njira Zogwirira Ntchito
IOPLL IP Core imathandizira mitundu isanu ndi umodzi yoyankha mawotchi. Mtundu uliwonse umalola kuchulutsa kwa wotchi ndi kugawa, kusuntha kwa gawo, ndikukonzekera ntchito.
Mawotchi Otulutsa
- IOPLL IP pachimake imatha kupanga mpaka mawotchi asanu ndi anayi. The kwaiye wotchi linanena bungwe zizindikiro wotchi pachimake kapena kunja midadada kunja pachimake.
- Mutha kugwiritsa ntchito chizindikiro chokhazikitsanso kuti mukhazikitsenso mtengo wa wotchi yotulutsa kukhala 0 ndikuletsa mawotchi otulutsa a PLL.
- Wotchi iliyonse yotulutsa imakhala ndi makonda omwe afunsidwa komwe mungatchule zomwe mukufuna kuti muzitha kutulutsa pafupipafupi, kusintha magawo, ndi kuzungulira kwa ntchito. Zokonda zomwe mukufuna ndizomwe mukufuna kukhazikitsa pakupanga kwanu.
- Miyezo yeniyeni ya mafupipafupi, kusintha kwa gawo, ndi kayendetsedwe ka ntchito ndizomwe zimakhala zapafupi kwambiri (pafupifupi bwino zomwe mukufuna) zomwe zingagwiritsidwe ntchito mu dera la PLL.
Reference Clock Switchover
Chiwongolero chosinthira wotchi imalola PLL kusintha pakati pa mawotchi awiri olowera. Gwiritsani ntchito izi pakusintha kwa mawotchi, kapena kugwiritsa ntchito mawotchi apawiri monga pamakina. Dongosololi limatha kuyatsa wotchi yocheperako ngati wotchi yoyamba isiya kugwira ntchito.
Pogwiritsa ntchito mawonekedwe osinthira wotchiyo, mutha kufotokoza kuchuluka kwa wotchi yachiwiri, ndikusankha mawonekedwe ndi kuchedwa kwa switchover.
Kuzindikira kutayika kwa mawotchi ndi chotchinga chosinthira wotchi chili ndi izi:
- Imayang'anira momwe wotchi ilili. Ngati wotchiyo ikulephera, wotchiyo imangosintha kupita kugwero lolowera koloko. Wotchiyo imasintha mawonekedwe a clkbad ndi activeclk siginecha kuti ichenjeze zomwe zikuchitika.
- Imasintha wotchi yolozera mmbuyo ndi mtsogolo pakati pa ma frequency awiri osiyana. Gwiritsani ntchito siginecha yotuluka kuti muwongolere pamanja kusinthaku. Kusintha kukachitika, PLL ikhoza kutaya loko kwakanthawi ndikudutsa njira yowerengera.
PLL-to-PLL Cascading
Ngati mutayika ma PLL pamapangidwe anu, gwero (kumtunda) PLL liyenera kukhala ndi malo otsika, pamene malo opita (pansi pamtsinje) PLL ayenera kukhala ndi mawonekedwe apamwamba. Pakutsitsa, kutulutsa kwa gwero la PLL kumakhala ngati wotchi yolozera (zolowetsa) za komwe mukupita PLL. Makonda a bandwidth a ma PLL otsika ayenera kukhala osiyana. Ngati makonda a bandwidth a ma PLL otsika ali ofanana, ma PLL otsika akhoza ampLify phase noise pama frequency ena. Gwero la wotchi ya adjpllin imagwiritsidwa ntchito pa inter-cascading between fracturable fractional PLLs.
Madoko
Table 6. IOPLL IP Core Ports
| Parameter | Mtundu | Mkhalidwe | Kufotokozera |
| refclk | Zolowetsa | Chofunikira | Gwero la wotchi yomwe imayendetsa I/O PLL. |
| woyamba | Zolowetsa | Chofunikira | The asynchronous reset port kwa mawotchi otulutsa. Yendetsani dokoli mmwamba kuti mukonzenso mawotchi onse otulutsa kuti akhale pamtengo wa 0. Muyenera kulumikiza dokoli ku siginecha yowongolera ogwiritsa ntchito. |
| fbclk | Zolowetsa | Zosankha | Doko lolowera kunja kwa I/O PLL.
IOPLL IP core imapanga doko ili pamene I/O PLL ikugwira ntchito mumayendedwe akunja kapena kuchedwa kwa zero. Kuti mutsirize kuyankhapo, kulumikizana kwa mulingo wa bolodi kuyenera kulumikiza doko la fbclk ndi doko lakunja lotulutsa wotchi ya I/O PLL. |
| fboutclk | Zotulutsa | Zosankha | Doko lomwe limadyetsa doko la fbclk kudzera mumayendedwe otsanzira.
Doko la fboutclk limapezeka pokhapokha ngati I/O PLL ili mumayendedwe akunja. |
| zdbfclk | Bilida | Zosankha | Doko la bidirectional lomwe limalumikizana ndi ma mimic circuitry. Dokoli liyenera kulumikizana ndi pini yolumikizirana yomwe imayikidwa pamapini abwino operekedwa ndi I/O PLL.
Doko la zdbfbclk likupezeka pokhapokha ngati I/O PLL ili munjira yochedwa zero. Kuti mupewe kuwonetsa ma siginecha mukamagwiritsa ntchito kuchedwa kwa zero, osayika zolozera pa pini ya I/O ya bidirectional. |
| zokhoma | Zotulutsa | Zosankha | IOPLL IP core imayendetsa doko ili pamwamba pomwe PLL ipeza loko. Doko limakhalabe lalitali bola IOPLL itatsekedwa. I/O PLL imatsimikizira doko lotsekedwa pomwe magawo ndi ma frequency a wotchi yolozera ndi wotchi yoyankha ndi |
| anapitiriza… | |||
| Parameter | Mtundu | Mkhalidwe | Kufotokozera |
| mofanana kapena mkati mwa kulolerana kwa dera lotseka. Kusiyana pakati pa mawotchi awiriwa kupitilira kulolerana kwa lock, I/O PLL imataya loko. | |||
| refclk1 | Zolowetsa | Zosankha | Gwero lachiwiri la wotchi yomwe imayendetsa I/O PLL pakusintha kwa wotchi. |
| extswitch | Zolowetsa | Zosankha | Onetsani kuti siginecha yotuluka ili yotsika (1'b0) kwa mawotchi osachepera atatu kuti musinthe wotchiyo pamanja. |
| activeclk | Zotulutsa | Zosankha | Chizindikiro chotulutsa chosonyeza kuti ndi gwero la wotchi yomwe I/O PLL ikugwiritsidwa ntchito. |
| clkbad | Zotulutsa | Zosankha | Chizindikiro chotulutsa chomwe chikuwonetsa momwe gwero la wotchi ilili yabwino kapena yoyipa. |
| kutuluka_kutuluka | Zotulutsa | Zosankha | Chizindikiro chotulutsa chomwe chimadya mumtsinje wa I/O PLL. |
| adjpllin | Zolowetsa | Zosankha | Chizindikiro cholowetsa chomwe chimadya kuchokera kumtunda kwa I/O PLL. |
| outclk_[] | Zotulutsa | Zosankha | Wotchi yotulutsa kuchokera ku I/O PLL. |
IOPLL Intel FPGA IP Core User Guide Archives
Ngati mtundu wa IP core sunatchulidwe, chiwongolero cha ogwiritsa ntchito pamtundu wakale wa IP akugwira ntchito
| IP Core Version | Wogwiritsa Ntchito |
| 17.0 | Altera I/O Phase-Locked Loop (Altera IOPLL) IP Core User Guide |
| 16.1 | Altera I/O Phase-Locked Loop (Altera IOPLL) IP Core User Guide |
| 16.0 | Altera I/O Phase-Locked Loop (Altera IOPLL) IP Core User Guide |
| 15.0 | Altera I/O Phase-Locked Loop (Altera IOPLL) IP Core User Guide |
Mbiri Yokonzanso Zolemba za IOPLL Intel FPGA IP Core User Guide
| Document Version | Intel Quartus® Prime Version | Zosintha |
| 2019.06.24 | 18.1 | Sinthani mafotokozedwe a mawotchi odzipereka mu Zomangamanga za I/O PLL chithunzi. |
| 2019.01.03 | 18.1 | • Kusinthidwa Kufikira kudoko la PLL LVDS_CLK/LOADEN
parameter mu IOPLL IP Core Parameters - Zikhazikiko Tab tebulo. • Kusintha malongosoledwe a doko la zdbfbclk mu IOPLL IP Core Ports tebulo. |
| 2018.09.28 | 18.1 | • Anakonza kufotokozera kwa exswitch mu IOPLL IP Core Ports
tebulo. • Anatchanso ma IP cores otsatirawa monga momwe Intel adasinthiranso: - Kusintha kwa Altera IOPLL IP core kukhala IOPLL Intel FPGA IP core. - Kusintha kwa Altera PLL Reconfig IP core kukhala PLL Reconfig Intel FPGA IP pachimake. - Adasinthidwa Arria 10 FPLL IP core kukhala fPLL Intel Arria 10/Cyclone 10 FPGA IP pachimake. |
| Tsiku | Baibulo | Zosintha |
| Juni 2017 | 2017.06.16 | • Zowonjezera zothandizira zida za Intel Cyclone 10 GX.
• Adasinthidwanso kukhala Intel. |
| Disembala 2016 | 2016.12.05 | Kusintha malongosoledwe a doko loyamba la IP core. |
| Juni 2016 | 2016.06.23 | • Zosintha za IP Core Parameters - Tabu ya Zikhazikiko.
- Sinthani mafotokozedwe a Manual Switchover ndi Automatic Switchover yokhala ndi magawo a Manual Override. Chizindikiro chowongolera wotchi chimagwira ntchito chochepa. - Sinthani mafotokozedwe a Switchover Delay parameter. • Zofotokozera M ndi C zowerengera za DPS Counter Selection parameter mu IP Core Parameters - Dynamic Reconfiguration Tab Tab. • Dzina ladoko losinthira wotchi yosinthidwa kuchoka ku clkswitch kupita ku extswitch mu chithunzi cha Typical I/O PLL Architecture. |
| Meyi 2016 | 2016.05.02 | Zosinthidwa IP Core Parameters - Dynamic Reconfiguration Tab Tab. |
| Meyi 2015 | 2015.05.04 | Sinthani malongosoledwe a Yambitsani mwayi wofikira ku PLL LVDS_CLK/LOADEN potuluka parameter mu IP Core Parameters - Tabu ya Zikhazikiko. Anawonjezera ulalo ku Signal Interface Pakati pa Altera IOPLL ndi Altera LVDS SERDES IP Cores tebulo mu I/O ndi High Speed I/O mu Arria 10 Devices mutu. |
| Ogasiti 2014 | 2014.08.18 | Kutulutsidwa koyamba. |
Zolemba / Zothandizira
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Intel UG-01155 IOPLL FPGA IP Core [pdf] Buku Logwiritsa Ntchito UG-01155 IOPLL FPGA IP Core, UG-01155, IOPLL FPGA IP Core, FPGA IP Core |
