intel HDMI PHY FPGA IP Design Example ntuziaka onye ọrụ
HDMI PHY Design ExampNtuziaka mmalite ngwa ngwa maka ngwaọrụ Intel® Arria® 10
HDMI PHY Intel® FPGA IP imewe exampmaka ngwaọrụ Intel Arria® 10 nwere ihe nrụpụta HDMI 2.0 RX-TX na-akwado nchikota na nnwale ngwaike.
Mgbe ị na-emepụta design example, paramita nchịkọta akụkọ na-akpaghị aka na-emepụta filedị mkpa iji megharịa, chịkọta, na nwalee imewe na ngwaike.
Ọgụgụ 1. Nzọụkwụ mmepe
Ozi metụtara
HDMI PHY Intel FPGA IP ntuziaka onye ọrụ
Ịmepụta Nhazi
Jiri HDMI PHY Intel FPGA IP parameter nchịkọta akụkọ na Intel Quartus® Prime software iji mepụta ihe ngosi nka.amples.
Onyonyo 2. Ịmepụta usoro nhazi
- Mepụta oru ngo ezubere iche maka ezinụlọ ngwaọrụ Intel Arria 10 wee họrọ ngwaọrụ achọrọ.
- N'ime katalọgụ IP, chọta wee pịa Protocols Interface ugboro abụọ ➤ Audio & Video ➤ HDMI TX PHY Intel FPGA IP (ma ọ bụ HDMI RX PHY Intel FPGA IP). Ụdị IP ọhụrụ ma ọ bụ mpio mgbanwe IP ọhụrụ na-egosi.
- Ezipụta aha ọkwa dị elu maka ụdị IP gị nkeonwe. Onye ndezi paramita na-echekwa ntọala IP dị iche na a file aha ya bụ .ip ma ọ bụ .qsys.
- Pịa OK. Ihe ndezi paramita na-egosi.
Ụlọ ọrụ Intel. Ikike niile echekwabara. Intel, akara Intel, na akara Intel ndị ọzọ bụ ụghalaahịa nke Intel
Corporation ma ọ bụ ndị enyemaka ya. Intel nyere ikike ịrụ ọrụ nke FPGA na ngwaahịa semiconductor na nkọwapụta ugbu a dịka akwụkwọ ikike ọkọlọtọ Intel siri dị, mana nwere ikike ịme mgbanwe na ngwaahịa na ọrụ ọ bụla n'oge ọ bụla na-enweghị ọkwa. Intel anaghị ewere ọrụ ọ bụla ma ọ bụ ụgwọ sitere na ngwa ma ọ bụ iji ozi ọ bụla, ngwaahịa ma ọ bụ ọrụ akọwara n'ime ebe a belụsọ dị ka Intel kwetara na ederede. A dụrụ ndị ahịa Intel ọdụ ka ha nweta ụdị nkọwa ngwaọrụ kachasị ọhụrụ tupu ha adabere na ozi ọ bụla ebipụtara yana tupu ịnye iwu maka ngwaahịa ma ọ bụ ọrụ.
Enwere ike ịzọrọ aha na akara ndị ọzọ dị ka ihe onwunwe nke ndị ọzọ. - Na imewe Exampna tab, họrọ Arria 10 HDMI RX-TX Nyefee.
- Họrọ Simulation ka ịmepụta testbench, wee họrọ Synthesis iji mepụta ngwaike imewe example.
Ị ga-ahọrọ ma ọ dịkarịa ala otu n'ime nhọrọ ndị a ka ịmepụta example files.
Ọ bụrụ na ị họrọ ha abụọ, oge ọgbọ na-adị ogologo. - Maka imepụta File Hazie, họrọ Verilog ma ọ bụ VHDL.
- Maka ngwa mmepe Target, họrọ Intel Arria 10 GX FPGA Development
Kit. Ọ bụrụ na ị họrọ mmepe kit, mgbe ahụ iche ngwaọrụ mgbanwe dakọtara na ngwaọrụ na iche osisi. Maka ngwa mmepe Intel Arria 10 GX FPGA, ngwaọrụ ndabara bụ 10AX115S2F4I1SG. - Pịa n'ịwa Example Design.
Ịchịkọta na Nnwale Nhazi
Iji chịkọta ma mee nnwale ngosi na ngwaike exampka imewe, soro usoro ndị a:
- Gbaa mbọ hụ na ngwaike example imewe ọgbọ zuru ezu.
- Mepee sọftụwia Intel Quartus Prime wee mepee ya .qpf file: /quartus/a10_hdmi2_demo.qpf
- Pịa Nhazi ➤ Malite Nchịkọta.
- Mgbe nchịkọta nke ọma gasịrị, .sof file emepụtara na quartus/mpụta_files ndekọ.
- Jikọọ Bitec HDMI 2.0 FMC Daughter Card Rev 11 na ọdụ ụgbọ mmiri FMC B (J2).
- Jikọọ TX (P1) nke kaadị nwa nwanyị Bitec FMC na isi iyi vidiyo mpụga.
- Jikọọ RX (P2) nke kaadị nwa nwanyị Bitec FMC na sink vidiyo mpụga ma ọ bụ ihe nyocha vidiyo.
- Gbaa mbọ hụ na mgba ọkụ niile dị na bọọdụ mmepe nọ n'ọnọdụ ndabara.
- Hazie ngwaọrụ Intel Arria 10 ahọpụtara na bọọdụ mmepe site na iji .sof emepụtara file (Ngwaọrụ ➤ Programmer).
- Onye nyocha kwesịrị igosipụta vidiyo ewepụtara site na isi mmalite. Ịchịkọta na Nnwale Nhazi
Ozi metụtara
Ntuziaka onye ọrụ ngwa ngwa Intel Arria 10 FPGA
HDMI PHY Intel FPGA IP Design Example Parameters
Tebụl 1. HDMI PHY Intel FPGA IP Design Example Parameters maka Intel Arria 10
Ngwaọrụ
Nhọrọ ndị a dị maka naanị ngwaọrụ Intel Arria 10.
| Oke | Uru | Nkọwa |
| Imepụta dị Example | ||
| Họrọ imewe | Arria 10 HDMI RX-TX Nyefee | Họrọ imewe example ka emeputa. |
| Imepụta Example Files | ||
| ịme anwansị | Gbanyụọ, Gbanyụọ | Gbanwuo nhọrọ a ka ịmepụta ihe dị mkpa files maka simulation testbench. |
| Synthesis | Gbanyụọ, Gbanyụọ | Gbanwuo nhọrọ a ka ịmepụta ihe dị mkpa files maka mkpokọta Intel Quartus Prime na ngosipụta ngwaike. |
| Ụdị HDL emepụtara | ||
| Mepụta File Usoro | Verilog, VHDL | Họrọ usoro HDL nke masịrị gị maka imewe emepụtara example filesetịpụrụ.
Mara: Nhọrọ a na-ekpebi naanị usoro maka ọkwa IP dị elu emepụtara files. Ndị ọzọ niile files (dịka ọmụmaatụ, example testbenches na elu larịị files maka ngosipụta ngwaike) dị na ụdị Verilog HDL. |
| Ngwa mmepe ebumnuche | ||
| Họrọ bọọdụ | Enweghị ngwa mmepe, | Họrọ osisi maka atụmatụ ezubere iche example. |
| Aria 10 GX FPGA Development Kit,
Ngwa mmepe omenala |
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| Ngwa ebumnuche | ||
| Gbanwee ngwaọrụ ebumnuche | Gbanyụọ, Gbanyụọ | Gbanwuo nhọrọ a wee họrọ ụdị ngwaọrụ dị iche iche maka ngwa mmepe. |
HDMI 2.0 PHY Design Example
HDMI PHY Intel FPGA IP imewe example na-egosi otu HDMI ihe atụ yiri loopback nke nwere ọwa RX atọ na ọwa TX anọ, na-arụ ọrụ na ọnụego data ruru 6 Gbps.
Ihe emepụtara HDMI PHY Intel FPGA IP imewe example bụ otu ihe ahụ dị ka imewe example emebere na HDMI Intel FPGA IP isi. Otú ọ dị, nke a imewe example na-eji ọhụrụ TX PHY, RX PHY, na PHY arbiter kama omenala RTL na HDMI Intel FPGA IP core design ex.ample.
Ọgụgụ 3. HDMI 2.0 PHY Design Example
| Modul | Nkọwa |
| RX PHY | RX PHY na-eweghachite data HDMI serial wee ziga nke a na HDMI RX core n'ụdị ya na ngalaba elekere enwetara (rx_clk[2:0]). A na-emegharị data ahụ ka ọ bụrụ vidiyo |
| Modul | Nkọwa |
| A ga-ewepụta data site na vidiyo iyi AXI4. RX PHY na-ezigakwa akara vid_clk na ls_clk na HDMI RX core site na interface PHY. | |
| HDMI TX Core | Isi HDMI TX na-enweta data vidiyo AXI4-iyi wee tinye nke a n'ime data usoro HDMI. Isi HDMI TX na-eziga data a na TX PHY. |
| HDMI RX Core | IP na-enweta data serial site na RX PHY ma na-arụ nhazi data, deskew channel, TMDS decoding, ntinye data inyeaka, ngbanwe data vidiyo, ngbanwe data ọdịyo, na descrambling. |
| TX PHY | Na-anata ma na-ahazi data agbakwunyere site na isi HDMI TX wee wepụta iyi iyi HDMI TMDS. TX PHY na-emepụta tx_clk maka isi HDMI TX. TX PHY na-ewepụtakwa vid_clk na ls_clk wee zipu akara ndị a na isi HDMI TX site na interface PHY. |
| IOPLL | Na-emepụta elekere 300 MHz AXI serial iyi maka interface iyi iyi AXI4. |
| I2C Nna-ukwu | Iji hazie akụrụngwa PCB dị iche iche. |
Achọrọ ngwaike na ngwanrọ
Intel na-eji ngwaike na ngwanrọ ndị a iji nwalee imewe example.
Akụrụngwa
- Intel Arria 10 GX FPGA Development Kit
- Isi iyi HDMI (Unit Processor Graphics (GPU)
- HDMI Sink (nleba anya)
- Bitec HDMI FMC 2.0 kaadị ada nwanyị (Ntụgharị 11)
- HDMI eriri
Ngwa ngwa
- Intel Quartus Prime Pro Edition (maka nnwale ngwaike)
- ModelSim* – Intel FPGA Edition, ModelSim – Intel FPGA Starter Edition, NCSim,
Riviera-PRO*, VCS* (Verilog HDL naanị)/VCS MX, ma ọ bụ Xcelium* Simulator yiri
Ọdịdị ndekọ
Akwụkwọ ndekọ aha nwere ihe emepụtara file maka HDMI Intel FPGA IP imewe example.
Ọgụgụ 4. Nhazi ndekọ aha maka imewe Example
Ntugharị Usoro nhazigharị
Ọgụgụ 5. Usoro nhazigharị ọnụọgụ ọtụtụ ọnụọgụ
Ọnụọgụ a na-egosi usoro nhazigharị ọnụọgụ ọtụtụ ọnụọgụ nke njikwa mgbe ọ na-enweta iyi data ntinye yana ugboro elekere, ma ọ bụ mgbe emeghere transceiver.
Ihe nrịbama ihu
Tebụl ndị a depụtara akara ngosi maka HDMI PHY Intel FPGA IP imewe example.
Tebụl 3. Ngosipụta ọkwa dị elu
| Signal | Ntuziaka | Obosara | Nkọwa |
| Mgbama Oscillator nọ n'ụgbọ | |||
| clk_fpga_b3_p | Ntinye | 1 | 100 MHz elekere na-agba ọsọ efu maka elekere ntụaka isi |
| refclk_fmcb_p | Ntinye | 1 | Elekere nrụtụ aka ka edobere maka nkwalite ike nke transceiver. Ọ bụ 625 MHz na ndabara mana ọ nwere ike ịbụ ugboro ọ bụla |
| bọtịnụ Push onye ọrụ na LEDs | |||
| cpu_resetn | Ntinye | 1 | Ntọgharị zuru ụwa ọnụ |
| onye ọrụ_led_g | Mpụta | 2 | Green LED ngosi |
| HDMI FMC Nwanyị Kaadị pin na FMC Port B | |||
| fmcb_gbtclk_m2c_p_0 | Ntinye | 1 | HDMI RX TMDS elekere |
| fmcb_dp_m2c_p | Ntinye | 3 | Ọwa data HDMI RX uhie, akwụkwọ ndụ akwụkwọ ndụ na acha anụnụ anụnụ
• Bite kaadị nlegharị anya 11 - [0]: RX TMDS Channel 1 (Green) - [1]: RX TMDS Channel 2 (Uhie Uhie) - [2]: RX TMDS Channel 0 (Blue) |
| fmcb_dp_c2m_p | Mpụta | 4 | Ọwa data HDMI TX, uhie, akwụkwọ ndụ akwụkwọ ndụ, na acha anụnụ anụnụ
• Bite kaadị nlegharị anya 11 - [0]: TX TMDS Channel 2 (Uhie Uhie) - [1]: TX TMDS Channel 1 (Green) - [2]: TX TMDS Channel 0 (Blue) - [3]: Ọwa elekere TX TMDS |
| fmcb_la_rx_p_9 | Ntinye | 1 | HDMI RX +5V ike chọpụta |
| fmcb_la_rx_p_8 | Ntinye | 1 | HDMI RX nkwụnye ọkụ chọpụta |
| fmcb_la_rx_n_8 | Ntinye | 1 | HDMI RX I2C SDA maka DDC na SCDC |
| fmcb_la_tx_p_10 | Ntinye | 1 | HDMI RX I2C SCL maka DDC na SCDC |
| fmcb_la_tx_p_12 | Ntinye | 1 | HDMI TX hot plug chọpụta |
| fmcb_la_tx_n_12 | Ntinye | 1 | HDMI I2C SDA maka DDC na SCDC |
| fmcb_la_rx_p_10 | Ntinye | 1 | HDMI I2C SCL maka DDC na SCDC |
| fmcb_la_tx_p_11 | Ntinye | 1 | HDMI I2C SDA maka njikwa redriver |
| fmcb_la_rx_n_9 | Ntinye | 1 | HDMI I2C SCL maka njikwa redriver |
Atụmatụ elekere
Ihe na-esonụ bụ atụmatụ clocking nke HDMI PHY Intel FPGA IP imewe exampLe:
- clk_fpga_b3_p bụ elekere ọnụego 100 MHz maka ịrụ ọrụ nhazi na njikwa NIOS. Ọ bụrụ na ugboro ewepụtara ziri ezi, user_led_g[1] na-atụgharị maka sekọnd ọ bụla.
- refclk_fmcb_p bụ elekere nrụtụ aka maka nrụzi ike nke transceivers. Ọ bụ 625 MHz na ndabara mana ọ nwere ike ịbụ ugboro ọ bụla.
- fmcb_gbtclk_m2c_p_0 bụ elekere TMDS maka HDMI RX. A na-ejikwa elekere a na-ebugharị ndị transceivers HDMI TX. Ọ bụrụ na ugboro ewepụtara bụ 148.5 MHz, user_led_g[0] na-atụgharị maka sekọnd ọ bụla.
Ntọala ngwaike
HDMI PHY Intel FPGA IP imewe example bụ HDMI 2.0b nwere ike ma na-eme ngosi akaghị aka maka iyi vidiyo HDMI ọkọlọtọ.
Iji mee ule ngwaike, jikọọ ngwaọrụ HDMI-enyere ya aka dị ka kaadị eserese nwere interface HDMI na njikọ HDMI RX na kaadị nwa nwanyị Bitec HDMI 2.0, nke na-ebuga data na ngọngọ RX transceiver na HDMI RX.
- The HDMI sink decoded ọdụ ụgbọ mmiri n'ime a ọkọlọtọ video iyi na-eziga ya na elekere mgbake isi.
- Isi HDMI RX na-ekpebi vidiyo, inyeaka, na data ọdịyo a ga-atụgharị azụ site na interface AXI4-stream gaa na isi HDMI TX.
- Ọdụ ụgbọ mmiri HDMI nke kaadị nwanyị FMC na-ebufe ihe onyonyo a na onye nleba anya.
- Pịa bọtịnụ cpu_resetn otu ugboro ka ịrụ nrụpụta sistemụ.
Mara: Ọ bụrụ na ịchọrọ iji bọọdụ mmepe Intel FPGA ọzọ, ị ga-agbanwerịrị ọrụ ngwaọrụ yana ọrụ ntụtụ. A nwalere ntọala analog transceiver maka ngwa mmepe Intel Arria 10 FPGA yana kaadị Bitec HDMI 2.0. Ị nwere ike gbanwee ntọala maka bọọdụ nke gị.
Akụkọ ngbanwe akwụkwọ maka HDMI PHY Intel
FPGA IP Design Example ntuziaka onye ọrụ
| Ụdị akwụkwọ | Intel Quartus Prime Version | Ụdị IP | Mgbanwe |
| 2022.07.20 | 22.2 | 1.0.0 | Ntọhapụ mbụ. |
Akwụkwọ / akụrụngwa
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intel HDMI PHY FPGA IP Design Example [pdf] Ntuziaka onye ọrụ HDMI PHY FPGA IP Design Example, HDMI PHY, FPGA IP Design Example, HDMI PHY IP Design Example, FPGA IP Design Example, IP Design Exampnke, 732781 |
