F-Tile DisplayPort FPGA IP Design Example
Ntuziaka onye ọrụ

F-Tile DisplayPort FPGA IP Design Example

Emelitere maka Intel® Quartus® Prime Design Suite: 22.2 Ụdị IP: 21.0.1

DisplayPort Intel FPGA IP Design Exampna Ntuziaka mmalite ngwa ngwa

Ngwa DisplayPort Intel® F-tile na-egosipụta testbench simulating na ngwaike na-akwado mkpokọta na nnwale ngwaike FPGA IP imewe ex.amples maka Intel Agilex™
The DisplayPort Intel FPGA IP na-enye ndị a imewe examples:

• DisplayPort SST yiri loopback na-enweghị modul Pixel Clock Recovery (PCR).
• DisplayPort SST yiri loopback na AXIS Video Interface

Mgbe ị na-emepụta design example, paramita nchịkọta akụkọ na-akpaghị aka na-emepụta filedị mkpa iji megharịa, chịkọta, na nwalee imewe na ngwaike.
Ọgụgụ 1. Mmepe StagesOzi metụtara

• DisplayPort Intel FPGA IP ntuziaka onye ọrụ
• Na-akwaga na Intel Quartus Prime Pro Edition

Ụlọ ọrụ Intel. Ikike niile echekwabara. Intel, akara Intel, na akara Intel ndị ọzọ bụ ụghalaahịa nke Intel Corporation ma ọ bụ ndị enyemaka ya. Intel nyere ikike ịrụ ọrụ nke FPGA na ngwaahịa semiconductor na nkọwapụta ugbu a dịka akwụkwọ ikike ọkọlọtọ Intel siri dị, mana nwere ikike ịme mgbanwe na ngwaahịa na ọrụ ọ bụla n'oge ọ bụla na-enweghị ọkwa. Intel anaghị ewere ọrụ ọ bụla ma ọ bụ ụgwọ sitere na ngwa ma ọ bụ iji ozi ọ bụla, ngwaahịa ma ọ bụ ọrụ akọwara n'ime ebe a belụsọ dị ka Intel kwetara na ederede. A dụrụ ndị ahịa Intel ọdụ ka ha nweta ụdị nkọwa ngwaọrụ kachasị ọhụrụ tupu ha adabere na ozi ọ bụla ebipụtara yana tupu ịnye iwu maka ngwaahịa ma ọ bụ ọrụ.
* Enwere ike ịzọrọ aha na akara ndị ọzọ dị ka ihe onwunwe nke ndị ọzọ.
ISO 9001: 2015 edebanye aha
1.1. Ọdịdị ndekọ
Ọgụgụ 2. Nhazi ndekọ aha

Tebụl 1. Imepụta Exampna akụrụngwa

Mpempe akwụkwọ	Files
rtl/isi	dp_core.ip
	dp_rx . ip
	dp_tx . ip
rtl/rx_phy	dp_gxb_rx/ ((DP PMA UX ngọngọ ụlọ)
	dp_rx_data_fifo . ip
	rx_top_phy . sv
rtl/tx_phy	dp_gxb_rx/ ((DP PMA UX ngọngọ ụlọ)
	dp_tx_data_fifo.ip
	dp_tx_data_fifo.ip

1.2. Achọrọ ngwaike na ngwanrọ
Intel na-eji ngwaike na ngwanrọ ndị a iji nwalee imewe exampLe:
Akụrụngwa

• Agilex I-Series Development Kit
• GPU isi iyi DisplayPort
• DisplayPort Sink (nleba anya)
• Bitec DisplayPort FMC nwa nwanyị kaadị Revision 8C
• Igwe eriri DisplayPort

Ngwa ngwa

• Intel Quartus® Prime
• Synopsys* VCS Simulator

1.3. Ịmepụta Nhazi
Jiri DisplayPort Intel FPGA IP parameter editọ na Intel Quartus Prime sọftụwia iji wepụta ihe nrụpụta example.
Onyonyo 3. Ịmepụta usoro nhazi

1.  Họrọ Ngwaọrụ ➤ IP katalọgụ, wee họrọ Intel Agilex F-tile dị ka ezinụlọ ngwaọrụ ebumnuche.
   Mara: Imewe example naanị akwado Intel Agilex F-tile ngwaọrụ.
2. Na katalọgụ IP, chọta wee pịa DisplayPort Intel FPGA IP ugboro abụọ. Window mgbanwe IP ọhụrụ na-egosi.
3. Ezipụta aha ọkwa dị elu maka ụdị IP gị nkeonwe. Onye ndezi paramita na-echekwa ntọala IP dị iche na a file aha ya .ip.
4. Họrọ ngwaọrụ Intel Agilex F-tile n'ọhịa ngwaọrụ, ma ọ bụ dobe ngwaọrụ ngwanrọ Intel Quartus Prime ndabara.
5. Pịa OK. Ihe ndezi paramita na-egosi.
6. Hazie paramita achọrọ maka ma TX na RX.
7. N'okpuru imewe Exampna tab, họrọ DisplayPort SST Parallel Loopback enweghị PCR.
8. Họrọ Simulation ka ịmepụta testbench, wee họrọ Synthesis iji mepụta ngwaike imewe example. Ị ga-ahọrọ ma ọ dịkarịa ala otu n'ime nhọrọ ndị a ka ịmepụta example files. Ọ bụrụ na ịhọrọ ha abụọ, oge ọgbọ na-adị ogologo.
9. Maka ngwa mmepe Target, họrọ Intel Agilex I-Series SOC Development Kit. Nke a na-eme ka lekwasịrị ngwaọrụ họrọ na nzọụkwụ 4 ịgbanwe ka dakọtara na ngwaọrụ na mmepe kit. Maka Intel Agilex I-Series SOC Development Kit, ngwaọrụ ndabara bụ AGIB027R31B1E2VR0.
10. Pịa n'ịwa Example Design.

1.4. Ịmepụta atụmatụ ahụ
Ihe ngosi DisplayPort Intel FPGA IP imewe example testbench na-egosipụta usoro loopback serial site na ihe atụ TX ruo ihe atụ RX. Modul ihe nrụpụta vidiyo dị n'ime na-ebugharị ihe atụ DisplayPort TX yana mmepụta vidiyo RX na-ejikọ na ndị na-enyocha CRC na testbench.
Ọgụgụ 4. Ntugharị Simulation Design

1. Gaa na folda simulator Synopsys wee họrọ VCS.
2. Gbaa edemede ịme anwansị.
   Isi mmalite vcs_sim.sh
3. Edemede a na-arụ Quartus TLG, na-achịkọta ma na-agba testbench na simulator.
4. Nyochaa nsonaazụ ya.
   Simulation na-aga nke ọma na-ejedebe na ntụnyere Source na Sink SRC.

1.5. Ịchịkọta na Nnwale Nhazi
Ọgụgụ 5. Ịchịkọta na Ịmepụta Nhazi ahụIji chịkọta ma mee nnwale ngosi na ngwaike exampka imewe, soro usoro ndị a:

1. Gbaa mbọ hụ na ngwaike example imewe ọgbọ zuru ezu.
2. Mepee sọftụwia Intel Quartus Prime Pro wee mepee / quartus/agi_dp_demo.qpf.
3. Pịa Nhazi ➤ Malite Nchịkọta.
4. Mgbe nchịkọta nke ọma gasịrị, Intel Quartus Prime Pro Edition software na-emepụta .sof file n'ime ndekọ aha gị akọwapụtara.
5. Jikọọ njikọ DisplayPort RX na kaadị nwa nwanyị Bitec na isi iyi DisplayPort, dị ka kaadị eserese na PC.
6. Jikọọ njikọ DisplayPort TX na kaadị nwa nwanyị Bitec na ngwaọrụ sink DisplayPort, dị ka ihe nyocha vidiyo ma ọ bụ ihe nleba anya PC.
7.  Gbaa mbọ hụ na mgba ọkụ niile dị na bọọdụ mmepe nọ n'ọnọdụ ndabara.
8. Hazie ngwaọrụ Intel Agilex F-Tile ahọpụtara na bọọdụ mmepe site na iji .sof emepụtara file (Ngwaọrụ ➤ Programmer).
9. Ngwaọrụ sink DisplayPort na-egosiputa vidiyo ewepụtara site na isi iyi vidiyo.

Ozi metụtara
Intel Agilex I-Series FPGA Development Kit Guide/
1.5.1. Na-emegharị ELF File
Site na ndabara, ELF file na-eme mgbe ị na-emepụta dynamic imewe example.
Agbanyeghị, n'ọnọdụ ụfọdụ, ịkwesịrị ịmaliteghachi ELF file ọ bụrụ na ị gbanwee ngwa ngwa file ma ọ bụ megharịa dp_core.qsys file. Na-emegharị dp_core.qsys file na-emelite .sopcinfo file, nke chọrọ ka ị megharịa ELF file.

1. Gaa na /software ma dezie koodu ma ọ bụrụ na ọ dị mkpa.
2. Gaa na /edemede wee gbuo edemede nrụpụta ndị a: source build_sw.sh
   • Na Windows, chọọ ma mepee Shell Iwu Nios II. Na Nios II Command Shell, gaa na / edemede wee mebie isi mmalite build_sw.sh.
   Mara: Iji mebe edemede ewu na Windows 10, sistemụ gị chọrọ sistemụ Windows maka Linux (WSL). Maka ozi ndị ọzọ gbasara usoro nrụnye WSL, rụtụ aka na Akwụkwọ ntuziaka Onye Mmepụta Ngwa Nios II.
   • Na Linux, malite Platform Designer, ma mepee Ngwaọrụ ➤ Nios II Command Shell. Na Nios II Command Shell, gaa na / edemede wee mebie isi mmalite build_sw.sh.
3. Gbaa mbọ hụ na .elf file emepụtara na /software/dp_demo.
4. Budata .elf emepụtara file banye na FPGA na-edoghị .sof file site na iji edemede a: nios2-download /software/dp_demo/*.elf
5. Pịa bọtịnụ nrụpụta na bọọdụ FPGA maka ngwanro ọhụrụ ahụ ka ọ rụọ ọrụ.

1.6. DisplayPort Intel FPGA IP Design Example Parameters
Tebụl 2. DisplayPort Intel FPGA IP Design Exampna mmachi QSF maka Intel Agilex Ftile Device

Mgbochi QSF	Nkọwa
set_global_assignment - aha VERILOG_MACRO "__DISPLAYPORT_support__=1"	Site na Quartus 22.2 gaa n'ihu, a chọrọ mmachi QSF a iji mee ka DisplayPort omenala SRC (Soft Reset Controller) nwee ike iru.

Tebụl 3. DisplayPort Intel FPGA IP Design ExampNhọrọ maka Intel Agilex F-tile Device

Oke	Uru	Nkọwa
Imepụta dị Example
Họrọ imewe	• Ọ dịghị •DisplayPort SST Parallel Loopback na-enweghị PCR •DisplayPort SST Parallel Loopback na AXIS Vidiyo Interface	Họrọ imewe example ka emeputa. • Ọ dịghị: Ọ dịghị imewe example dị maka nhọrọ oke dị ugbu a. •DisplayPort SST Parallel Loopback enweghị PCR: Nke a imewe example na-egosiputa loopback yiri ya site na DisplayPort sink gaa na isi iyi DisplayPort na-enweghị modul Pixel Clock Recovery (PCR) mgbe ị na-agbanye Kwado ihe ntinye ihe onyonyo vidiyo. •DisplayPort SST Parallel Loopback na AXIS Vidiyo Interface: Nke a imewe example na-egosiputa loopback yiri ya site na DisplayPort sink gaa na isi iyi DisplayPort nwere AXIS Video interface mgbe edobere usoro data data vidiyo na-arụ ọrụ na AXIS-VVP zuru oke.
Imepụta Example Files
ịme anwansị	Gbanyụọ, Gbanyụọ	Gbanwuo nhọrọ a ka ịmepụta ihe dị mkpa files maka simulation testbench.
Synthesis	Gbanyụọ, Gbanyụọ	Gbanwuo nhọrọ a ka ịmepụta ihe dị mkpa files maka nhazi Intel Quartus Prime na nhazi ngwaike.
Ụdị HDL emepụtara
Mepụta File Usoro	Verilog, VHDL	Họrọ usoro HDL nke masịrị gị maka imewe emepụtara example filesetịpụrụ. Mara: Nhọrọ a na-ekpebi naanị usoro maka ọkwa IP emepụtara files. Ndị ọzọ niile files (dịka ọmụmaatụample testbenches na elu larịị files maka ngosipụta ngwaike) dị na ụdị Verilog HDL.
Ngwa mmepe ebumnuche
Họrọ bọọdụ	• Enweghị ngwa mmepe •Intel Agilex I-Series Ngwa mmepe	Họrọ osisi maka atụmatụ ezubere iche example.

Oke	Uru	Nkọwa
		• Enweghị ngwa mmepe: Nhọrọ a na-ewepu akụkụ ngwaike niile maka imewe example. Isi P na-edobe ọrụ ntụtụ niile na ntụtụ mebere. •Intel Agilex I-Series FPGA Development Kit: Nke a na-akpaghị aka na-ahọrọ ngwaọrụ ezubere iche nke oru ngo ka dakọtara na ngwaọrụ a mmepe ngwa. Ị nwere ike ịgbanwe iche ngwaọrụ site na iji Change Target Device oke ma ọ bụrụ na gị osisi revision nwere dị iche iche ngwaọrụ variant. Isi IP na-edobe ọrụ ntụtụ niile dịka ngwa mmepe siri dị. Mara: Nhazi mbido ExampA naghị akwado nke ọma na ngwaike na ntọhapụ Quartus a. • Ngwa mmepe omenala: Nhọrọ a na-enye ohere imewe exampA ga-anwale ya na ngwa mmepe nke ndị ọzọ yana Intel FPGA. Ị nwere ike ịtọ ntọala pin n'onwe gị.
Ngwa ebumnuche
Gbanwee ngwaọrụ ebumnuche	Gbanyụọ, Gbanyụọ	Gbanwuo nhọrọ a wee họrọ ụdị ngwaọrụ dị iche iche maka ngwa mmepe.

Myirịta Loopback Design Examples

Ihe ngosi DisplayPort Intel FPGA IP imewe examples igosi loopback yiri nke ahụ site na ihe atụ DisplayPort RX ruo ihe atụ DisplayPort TX na-enweghị modul Pixel Clock Recovery (PCR).
Tebụl 4. DisplayPort Intel FPGA IP Design Exampmaka Intel Agilex F-tile Device

Imepụta Example	Nhọpụta	Ọnụego data	Ọnọdụ Channel	Ụdị Loopback
DisplayPort SST yiri loopback na-enweghị PCR	DisplayPort SST	RBR, HRB, HRB2, HBR3	Simplex	Yiri na-enweghị PCR
DisplayPort SST yiri loopback na AXIS Video Interface	DisplayPort SST	RBR, HRB, HRB2, HBR3	Simplex	Yiri na Interface vidiyo AXIS

2.1. Intel Agilex F-tile DisplayPort SST Parallel Loopback Design Atụmatụ
The SST yiri loopback imewe examples gosi nnyefe nke otu iyi vidiyo si na DisplayPort sink na isi iyi DisplayPort.
Ụlọ ọrụ Intel. Ikike niile echekwabara. Intel, akara Intel, na akara Intel ndị ọzọ bụ ụghalaahịa nke Intel Corporation ma ọ bụ ndị enyemaka ya. Intel nyere ikike ịrụ ọrụ nke FPGA na ngwaahịa semiconductor na nkọwapụta ugbu a dịka akwụkwọ ikike ọkọlọtọ Intel siri dị, mana nwere ikike ịme mgbanwe na ngwaahịa na ọrụ ọ bụla n'oge ọ bụla na-enweghị ọkwa. Intel anaghị ewere ọrụ ọ bụla ma ọ bụ ụgwọ sitere na ngwa ma ọ bụ iji ozi ọ bụla, ngwaahịa ma ọ bụ ọrụ akọwara n'ime ebe a belụsọ dị ka Intel kwetara na ederede. A dụrụ ndị ahịa Intel ọdụ ka ha nweta ụdị nkọwa ngwaọrụ kachasị ọhụrụ tupu ha adabere na ozi ọ bụla ebipụtara yana tupu ịnye iwu maka ngwaahịa ma ọ bụ ọrụ. * Enwere ike ịzọrọ aha na akara ndị ọzọ dị ka ihe onwunwe nke ndị ọzọ.
ISO 9001: 2015 edebanye aha
Ọgụgụ 6. Intel Agilex F-tile DisplayPort SST Parallel Loopback na-enweghị PCR

• N'ụdị dị iche iche a, agbanyere paramita isi iyi DisplayPort, TX_SUPPORT_IM_ENABLE ma jiri ihu onyonyo onyonyo.
• The DisplayPort sink na-enweta vidiyo na ma ọ bụ ọdịyo ọdịyo sitere na isi iyi vidiyo dị n'èzí dị ka GPU wee depụta ya na interface vidiyo yiri ya.
• Mmepụta vidiyo sink nke DisplayPort na-ebugharị ngwa ngwa vidiyo isi iyi nke DisplayPort wee tinye ya na njikọ isi DisplayPort tupu ebunye ya na onye nleba anya.
• IOPLL na-ebugharị ma DisplayPort sink na isi iyi vidiyo na oge a kapịrị ọnụ.
• Ọ bụrụ na ahaziri ihe ngosi DisplayPort na isi iyi MAX_LINK_RATE ka HBR3 wee hazie PIXELS_PER_CLOCK ka ọ bụrụ Quad, elekere vidiyo na-aga na 300 MHz iji kwado ọnụego pikselụ 8Kp30 (1188/4 = 297 MHz).

Ọgụgụ 7. Intel Agilex F-tile DisplayPort SST Parallel Loopback na vidiyo AXIS Interface

• N'ụdị a dị iche iche, isi iyi DisplayPort na paramita sink, họrọ AXIS-VVP FULL na ENWETA ACTIVE VIDEO DATA PROTOCOLS iji mee ka Interface Data Axis Video.
• The DisplayPort sink na-enweta vidiyo na ma ọ bụ ọdịyo ọdịyo sitere na isi iyi vidiyo dị n'èzí dị ka GPU wee depụta ya na interface vidiyo yiri ya.
• DisplayPort Sink na-atụgharị iyi data vidiyo n'ime data vidiyo axis ma na-ebuga ihe ngosi data vidiyo axis isi iyi site na VVP Video Frame Buffer. Isi mmalite DisplayPort na-atụgharị data vidiyo axis ka ọ bụrụ isi njikọ DisplayPort tupu ibunye na onye nleba anya.
• N'ime ụdị nhazi a, enwere clocks isi vidiyo atọ, ya bụ rx/tx_axi4s_clk, rx_vid_clk, na tx_vid_clk. axi4s_clk na-agba na 300 MHz maka ma modul AXIS na Isi iyi na Sink. rx_vid_clk na-agba ọsọ pipeline Video Sink na 300 MHz (iji kwado mkpebi ọ bụla ruo 8Kp30 4PIPs), ebe tx_vid_clk na-agba DP Source Video pipeline n'ezie Pixel Clock ugboro (nke PIP kewara).
• Nke a imewe variant akpaaka configure tx_vid_clk ugboro site I2C mmemme ka on-board SI5391B OSC mgbe imewe chọpụtara a mgba ọkụ na mkpebi.
• Ụdị atụmatụ a na-egosipụta naanị ọnụọgụ mkpebi dị ka akọwara ya na ngwanrọ DisplayPort, ya bụ:
  - 720p60, RGB
  - 1080p60, RGB
  - 4K30, RGB
  - 4K60, RGB

2.2. Atụmatụ elekere
Atụmatụ clocking na-egosi ngalaba elekere na DisplayPort Intel FPGA IP imewe example.
Ọgụgụ 8. Intel Agilex F-tile DisplayPort Transceiver clocking atụmatụTebụl 5. Ngosipụta atụmatụ elekere

Elekere na eserese	Nkọwa
SysPLL refclk	F-tile Sistemu Ntụaka Elekere PLL nke nwere ike ịbụ ugboro elekere ọ bụla nke Sistemu PLL na-eke maka oge mmepụta ahụ. Na nke a imewe example, system_pll_clk_link na rx/tx refclk_link na-ekekọrịta otu 150 MHz SysPLL refclk.

Elekere na eserese	Nkọwa
	Ọ ga-abụrịrị elekere na-agba ọsọ n'efu nke ejikọtara site na pin elekere ntụgharị transceiver raara onwe ya nye n'ọdụ ụgbọ mmiri ntinye aka nke Reference na Sistemụ PLL Clocks IP, tupu ijikọ ọdụ ụgbọ mmiri kwekọrọ na DisplayPort Phy Top. Mara: Maka imewe a example, hazie elekere njikwa GUI Si5391A OUT6 ka 150 MHz.
usoro pll clk njikọ	Opekempe mmepụta PLL Sistemu iji kwado ọnụego DisplayPort niile bụ 320 MHz. Nke a imewe example na-eji 900 MHz (kachasị elu) mmepụta ugboro ka SysPLL refclk nwere ike ịkekọrịta na rx/tx refclk_link nke bụ 150 MHz.
rx_cdr_refclk_link / tx_pll_refclk_link	Rx CDR na Tx PLL Link refclk nke edobere na 150 MHz iji kwado ọnụego data DisplayPort niile.
rx_ls_clkout / tx_ls_clkout	DisplayPort Njikọ Ọsọ elekere ruo elekere DisplayPort IP isi. Ugboro nke dabara na nkewa ọnụego data site na obosara data yiri ya. ExampLe: Ugboro = ọnụego data / obosara data = 8.1G (HBR3) / 40 ibe n'ibe = 202.5 MHz

2.3. Testbench Simulation
Testbench simulation na-eme ka ngosipụta nke DisplayPort TX laghachi azụ na RX.
Ọgụgụ 9. DisplayPort Intel FPGA IP Simplex Mode Simulation Testbench Block EsereseTebụl 6. Ngwa Testbench

Akụkụ	Nkọwa
Ihe Nlereanya vidiyo	Igwe ọkụ a na-emepụta ụkpụrụ mmanya agba nke ị nwere ike hazie. Ị nwere ike parameterize video usoro oge.
Njikwa Testbench	Ihe mgbochi a na-achịkwa usoro ule nke ịme anwansị ahụ ma wepụta akara mkpali dị mkpa na isi TX. Ihe mgbochi testbench na-agụkwa uru CRC sitere na isi mmalite na sink iji mee ntụnyere.
Onye nlele elekere ọsọ ọsọ RX	Ihe nlele anya a na-enyocha ma ọ bụrụ na transceiver RX enwetara ugboro elekere dabara na ọnụego data achọrọ.
TX Njikọ Ọsọ elekere ugboro ugboro	Ihe nlele a na-enyocha ma ọ bụrụ na transceiver TX enwetara ugboro elekere dabara na ọnụego data achọrọ.

Testbench simulation na-eme nkwenye ndị a:
Tebụl 7. Nyocha Testbench

Nlele ule	Nyocha
• Ọzụzụ njikọ na ọnụego data HBR3 • Gụọ ndekọ DPCD ka ịlele ma Ọnọdụ DP na-ahazi ma tụọ ma TX na RX Njikọ Ọsọ ọsọ.	Na-ejikọta ihe nlele ugboro ugboro iji tụọ ọsọ Njikọ mmepụta ugboro elekere site na TX na RX transceiver.
• Gbaa ụkpụrụ vidiyo site na TX ruo RX. • Nyochaa CRC maka isi iyi na sink ka ịlele ma ha dabara	• Jikọọ vidiyo ụkpụrụ generator na DisplayPort Isi iyi ka iwepụta video ụkpụrụ. • Njikwa Testbench na-agụpụta ma Source na Sink CRC sitere na ndekọ DPTX na DPRX ma tụnyere iji hụ na ụkpụrụ CRC abụọ ahụ bụ otu. Mara: Iji hụ na agbakọrọ CRC, ị ga-emerịrị ihe nkwado CTS akpaaka akpaaka.

Akụkọ ngbanwe akwụkwọ maka F-Tile DisplayPort Intel FPGA IP Design Example ntuziaka onye ọrụ

Ụdị akwụkwọ	Intel Quartus Prime Version	Ụdị IP	Mgbanwe
2022.09.02	22.	20.0.1	• Aha akwụkwọ gbanwere site na DisplayPort Intel Agilex F-Tile FPGA IP Design ExampNtuziaka onye ọrụ na F-Tile DisplayPort Intel FPGA IP Design Example ntuziaka onye ọrụ. • Akwanyere AXIS Video Design Example iche. • Wepụrụ atụmatụ Static Rate wee jiri Multi Rate Design Example. • Wepụrụ ndetu dị na DisplayPort Intel FPGA IP Design ExampNtuziaka mmalite ngwa ngwa nke na-ekwu ụdị sọftụwia Intel Quartus Prime 21.4 na-akwado naanị Preliminary Design Examples. • Jiri ọnụ ọgụgụ ziri ezi dochie ọnụ ọgụgụ akwụkwọ ndekọ aha. • Agbakwunyere ngalaba Na-eweghachi ELF File n'okpuru Ịchịkọta na ịnwale imewe ahụ. • Emelitere ngalaba chọrọ ngwaike na ngwanrọ iji tinye ngwaike agbakwunyere chọrọ.
2021.12.13	21.	20.0.0	Ntọhapụ mbụ.

Ụlọ ọrụ Intel. Ikike niile echekwabara. Intel, akara Intel, na akara Intel ndị ọzọ bụ ụghalaahịa nke Intel Corporation ma ọ bụ ndị enyemaka ya. Intel nyere ikike ịrụ ọrụ nke FPGA na ngwaahịa semiconductor na nkọwapụta ugbu a dịka akwụkwọ ikike ọkọlọtọ Intel siri dị, mana nwere ikike ịme mgbanwe na ngwaahịa na ọrụ ọ bụla n'oge ọ bụla na-enweghị ọkwa. Intel anaghị ewere ọrụ ọ bụla ma ọ bụ ụgwọ sitere na ngwa ma ọ bụ iji ozi ọ bụla, ngwaahịa ma ọ bụ ọrụ akọwara n'ime ebe a belụsọ dị ka Intel kwetara na ederede. A dụrụ ndị ahịa Intel ọdụ ka ha nweta ụdị nkọwa ngwaọrụ kachasị ọhụrụ tupu ha adabere na ozi ọ bụla ebipụtara yana tupu ịnye iwu maka ngwaahịa ma ọ bụ ọrụ.
* Enwere ike ịzọrọ aha na akara ndị ọzọ dị ka ihe onwunwe nke ndị ọzọ.
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Version nke Ntanetị
Zipu nzaghachi
UG-20347
Nọmba ederede: 709308
Ụdị: 2022.09.02

Akwụkwọ / akụrụngwa

intel F-Tile DisplayPort FPGA IP Design Example [pdf] Ntuziaka onye ọrụ F-Tile DisplayPort FPGA IP Design Example, F-Tile DisplayPort, DisplayPort, FPGA IP Design Example, IP Design Example, UG-20347, 709308

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