intel HDMI PHY FPGA IP Design ExampJagorar Mai Amfani
HDMI PHY Design ExampJagorar farawa mai sauri don Intel® Arria® 10 na'urori
HDMI PHY Intel® FPGA IP ƙiraampna'urorin Intel Arria® 10 sun ƙunshi ƙirar mai sake watsawa ta HDMI 2.0 RX-TX wacce ke goyan bayan haɗawa da gwajin kayan aiki.
Lokacin da kuka samar da zane exampHar ila yau, editan siga yana ƙirƙirar ta atomatik fileya zama dole don kwaikwaya, tarawa, da gwada ƙira a cikin kayan masarufi.
Hoto 1. Matakan Ci gaba
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HDMI PHY Intel FPGA IP Jagorar Mai amfani
Samar da Zane
Yi amfani da HDMI PHY Intel FPGA IP editan siga a cikin Intel Quartus® Prime software don samar da tsohon ƙira.amples.
Hoto 2. Samar da Tsarin Zane
- Ƙirƙiri aikin da ke niyya dangin na'urar Intel Arria 10 kuma zaɓi na'urar da ake so.
- A cikin Catalog na IP, gano wuri kuma danna ƙa'idodin Interface Protocol sau biyu ➤ Audio & Bidiyo ➤ HDMI TX PHY Intel FPGA IP (ko HDMI RX PHY Intel FPGA IP). Sabuwar Bambancin IP ko Sabuwar taga Bambancin IP yana bayyana.
- Ƙayyade sunan babban matakin don bambancin IP na al'ada. Editan siga yana adana saitunan bambancin IP a cikin a file mai suna .ip ko .qsys.
- Danna Ok. Editan siga ya bayyana.
Kamfanin Intel. An kiyaye duk haƙƙoƙi. Intel, tambarin Intel, da sauran alamun Intel alamun kasuwanci ne na Intel
Kamfanin ko rassan sa. Intel yana ba da garantin aiwatar da samfuran FPGA da semiconductor zuwa ƙayyadaddun bayanai na yanzu daidai da daidaitaccen garanti na Intel, amma yana da haƙƙin yin canje-canje ga kowane samfuri da sabis a kowane lokaci ba tare da sanarwa ba. Intel ba ya ɗaukar wani nauyi ko alhaki da ya taso daga aikace-aikacen ko amfani da kowane bayani, samfur, ko sabis da aka kwatanta a nan sai dai kamar yadda Intel ya yarda da shi a rubuce. An shawarci abokan cinikin Intel su sami sabon sigar ƙayyadaddun na'urar kafin su dogara ga kowane bayanan da aka buga kuma kafin sanya oda don samfur ko ayyuka.
Ana iya da'awar wasu sunaye da alamun a matsayin mallakin wasu. - Akan Zane Exampa shafin, zaɓi Arria 10 HDMI RX-TX Sake aikawa.
- Zaɓi Simulation don samar da benci na gwaji, kuma zaɓi Synthesis don samar da ƙirar kayan masarufiample.
Dole ne ku zaɓi aƙalla ɗaya daga cikin waɗannan zaɓuɓɓukan don samar da ƙirar tsohuwarample files.
Idan kun zaɓi duka biyun, lokacin tsara ya fi tsayi. - Don Ƙirƙiri File Tsara, zaɓi Verilog ko VHDL.
- Don Kit ɗin Ci gaban Target, zaɓi Intel Arria 10 GX FPGA Development
Kit. Idan ka zaɓi kayan haɓakawa, to, na'urar da aka yi niyya ta canza don dacewa da na'urar da ke kan jirgin da aka yi niyya. Don Kit ɗin Haɓakawa na Intel Arria 10 GX FPGA, na'urar tsoho ita ce 10AX115S2F4I1SG. - Danna Ƙirƙirar Exampda Design.
Haɗawa da Gwajin Zane
Don haɗawa da gudanar da gwajin gwaji akan hardware exampdon tsarawa, bi waɗannan matakan:
- Tabbatar da hardware example zane tsara ya cika.
- Kaddamar da Intel Quartus Prime software kuma bude .qpf file: /quartus/a10_hdmi2_demo.qpf
- Danna Processing ➤ Fara Tari.
- Bayan nasarar hadawa, a .sof file Ana haifar da shi a cikin kwatanci/ fitarwa_files directory.
- Haɗa Bitec HDMI 2.0 FMC Daughter Card Rev 11 zuwa tashar jirgin ruwa ta FMC B (J2).
- Haɗa TX (P1) na katin 'yar Bitec FMC zuwa tushen bidiyo na waje.
- Haɗa RX (P2) na katin 'yar Bitec FMC zuwa madaidaicin bidiyo na waje ko mai nazarin bidiyo.
- Tabbatar cewa duk masu sauyawa akan allon haɓaka suna cikin tsoho matsayi.
- Sanya na'urar Intel Arria 10 da aka zaɓa akan allon haɓaka ta amfani da .sof da aka samar file (Kayan aiki ➤ Mai shirye-shirye).
- Ya kamata mai nazari ya nuna bidiyon da aka samar daga tushen. Haɗawa da Gwajin Zane
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Intel Arria 10 Jagorar Mai Amfani da Kit ɗin Ci gaban FPGA
HDMI PHY Intel FPGA IP Design Exampda Parameters
Tebur 1. HDMI PHY Intel FPGA IP Design ExampLe Parameters don Intel Arria 10
Na'urori
Ana samun waɗannan zaɓuɓɓuka don na'urorin Intel Arria 10 kawai.
| Siga | Daraja | Bayani |
| Akwai Zane Example | ||
| Zaɓi Zane | Arria 10 HDMI RX-TX Sake aikawa | Zaɓi zane exampda za a haifar. |
| Zane Example Files | ||
| kwaikwayo | Kunnawa, Kashe | Kunna wannan zaɓi don samar da abin da ake bukata files don simulation testbench. |
| Magana | Kunnawa, Kashe | Kunna wannan zaɓi don samar da abin da ake bukata files don Haɗin Intel Quartus Prime da nunin kayan aiki. |
| Samar da Tsarin HDL | ||
| Ƙirƙira File Tsarin | Verilog, VHDL | Zaɓi tsarin HDL da kuka fi so don ƙirar ƙiraample filesaita.
Lura: Wannan zaɓin yana ƙayyadaddun tsari ne kawai don babban matakin IP da aka samar files. Duk sauran files (misali, misaliample testbenches da babban matakin files don zanga-zangar hardware) suna cikin tsarin Verilog HDL. |
| Kit ɗin Ci gaban Target | ||
| Zaɓi Board | Babu Kayan Ci gaba, | Zaɓi allon don ƙirar da aka yi niyya example. |
| Arria 10 GX FPGA Development Kit,
Kit ɗin Ci gaban Al'ada |
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| Na'urar Target | ||
| Canja Na'urar Target | Kunnawa, Kashe | Kunna wannan zaɓi kuma zaɓi bambance-bambancen na'urar da aka fi so don kayan haɓakawa. |
HDMI 2.0 PHY Design Example
HDMI PHY Intel FPGA IP zane example yana nuna misali guda ɗaya na HDMI mai layi ɗaya wanda ya ƙunshi tashoshi RX uku da tashoshi huɗu na TX, suna aiki akan ƙimar bayanai har zuwa 6 Gbps.
An samar da HDMI PHY Intel FPGA IP ƙirar misaliample daidai yake da zane exampLe generated a cikin HDMI Intel FPGA IP core. Duk da haka, wannan zane example yana amfani da sabon TX PHY, RX PHY, da PHY arbiter maimakon RTL na al'ada a cikin HDMI Intel FPGA IP core design ex.ample.
Hoto 3. HDMI 2.0 PHY Design Example
| Module | Bayani |
| RX PHY | RX PHY yana dawo da bayanan HDMI na serial kuma ya aika wannan zuwa ga HDMI RX core a layi daya a kan yankunan agogo da aka kwato (rx_clk[2:0]). Ana canza bayanan zuwa bidiyo |
| Module | Bayani |
| bayanan da za a fitar ta hanyar bidiyo na AXI4-stream. Hakanan RX PHY yana aika sigina na vid_clk da ls_clk zuwa HDMI RX core ta hanyar PHY interface. | |
| HDMI TX Core | HDMI TX core yana karɓar bayanan bidiyo na AXI4-rafi kuma yana ɓoye wannan cikin bayanan daidaitaccen tsarin HDMI. HDMI TX core yana aika wannan bayanan zuwa TX PHY. |
| HDMI RX Core | IP ɗin yana karɓar bayanan serial daga RX PHY kuma yana aiwatar da daidaitawar bayanai, deskew tashoshi, ƙididdigewa na TMDS, ƙaddamar da bayanan ƙarin bayanai, ƙaddamar da bayanan bidiyo, ƙaddamar da bayanan sauti, da lalatawa. |
| Farashin TX PHY | Yana karɓa da jera bayanan daidaitattun bayanai daga jigon HDMI TX kuma yana fitar da rafukan HDMI TMDS. TX PHY yana samar da tx_clk don ainihin HDMI TX. TX PHY kuma yana haifar da vid_clk da ls_clk kuma yana aika waɗannan sigina zuwa ainihin HDMI TX ta hanyar PHY interface. |
| IOPLL | Yana samar da agogon serial rafi na 300 MHz AXI don dubawar rafi na AXI4. |
| Babban darajar I2C | Don saita abubuwan PCB daban-daban. |
Bukatun Hardware da Software
Intel yana amfani da kayan masarufi da software masu zuwa don gwada ƙirar ƙiraample.
Hardware
- Intel Arria 10 GX FPGA Development Kit
- Madogararsa HDMI (Sashin sarrafawar Hotuna (GPU)
- HDMI nutsewa (Monitor)
- Bitec HDMI katin 'yar mata FMC 2.0 (Bita 11)
- HDMI igiyoyi
Software
- Intel Quartus Prime Pro Edition (don gwajin kayan aiki)
- ModelSim* - Intel FPGA Edition, ModelSim - Intel FPGA Starter Edition, NCSim,
Riviera-PRO*, VCS* (Verilog HDL kawai)/VCS MX, ko Xcelium* Daidaitaccen na'urar kwaikwayo.
Tsarin Jagora
Kundayen adireshi sun ƙunshi abubuwan da aka samar file don HDMI Intel FPGA IP zane example.
Hoto 4. Tsarin Jagora don Zane Example
Gudun Tsarin Sake saitawa
Hoto 5. Matsakaicin Matsakaicin Matsakaicin Matsakaicin Matsala
Hoton yana misalta sauye-sauyen jeri na sake daidaita ƙima na mai sarrafawa lokacin da ya karɓi rafin bayanan shigarwa da mitar agogo, ko lokacin da aka buɗe transceiver.
Siginonin Sadarwa
Teburan sun jera sigina na HDMI PHY Intel FPGA IP ƙirar misaliample.
Tebur 3. Sigina na Babban-Mataki
| Sigina | Hanyar | Nisa | Bayani |
| Siginar Oscillator na kan jirgi | |||
| clk_fpga_b3_p | Shigarwa | 1 | 100 MHz agogon gudu na kyauta don ainihin agogon tunani |
| refclk_fmcb_p | Shigarwa | 1 | Kafaffen agogon nunin ƙima don haɓaka ƙarfin wutar lantarki na transceiver. Yana da 625 MHz ta tsohuwa amma yana iya zama na kowane mita |
| Maɓallin Tura masu amfani da LEDs | |||
| cpu_sake saitin | Shigarwa | 1 | Sake saitin duniya |
| mai amfani_led_g | Fitowa | 2 | Green LED nuni |
| HDMI FMC Katin Katin 'yar mata akan FMC Port B | |||
| fmcb_gbtclk_m2c_p_0 | Shigarwa | 1 | HDMI RX TMDS agogo |
| fmcb_dp_m2c_p | Shigarwa | 3 | HDMI RX ja, kore, da tashoshi bayanan bayanai
• Biec yar katin bita 11 - [0]: RX TMDS Channel 1 (Green) - [1]: RX TMDS Channel 2 (Ja) - [2]: RX TMDS Channel 0 (Blue) |
| fmcb_dp_c2m_p | Fitowa | 4 | HDMI TX agogo, ja, kore, da tashoshi bayanai
• Biec yar katin bita 11 - [0]: TX TMDS Channel 2 (Ja) - [1]: TX TMDS Channel 1 (Green) - [2]: TX TMDS Channel 0 (Blue) - [3]: TX TMDS Clock Channel |
| fmcb_la_rx_p_9 | Shigarwa | 1 | HDMI RX + 5V gano wutar lantarki |
| fmcb_la_rx_p_8 | Shigarwa | 1 | HDMI RX hot plug gano |
| fmcb_la_rx_n_8 | Shigarwa | 1 | HDMI RX I2C SDA don DDC da SCDC |
| fmcb_la_tx_p_10 | Shigarwa | 1 | HDMI RX I2C SCL don DDC da SCDC |
| fmcb_la_tx_p_12 | Shigarwa | 1 | HDMI TX hot plug gano |
| fmcb_la_tx_n_12 | Shigarwa | 1 | HDMI I2C SDA don DDC da SCDC |
| fmcb_la_rx_p_10 | Shigarwa | 1 | HDMI I2C SCL don DDC da SCDC |
| fmcb_la_tx_p_11 | Shigarwa | 1 | HDMI I2C SDA don sarrafa mai sakewa |
| fmcb_la_rx_n_9 | Shigarwa | 1 | HDMI I2C SCL don sarrafa mai sakewa |
Tsarin agogo
Mai zuwa shine tsarin agogo na HDMI PHY Intel FPGA IP ƙiraampda:
- clk_fpga_b3_p shine ƙayyadaddun agogo mai ƙayyadaddun 100 MHz don gudanar da na'ura na NIOS da ayyukan sarrafawa. Idan mitar da aka kawo daidai ne, mai amfani_led_g[1] yana jujjuyawar kowane daƙiƙa.
- refclk_fmcb_p shine ƙayyadadden agogon nunin ƙima don haɓaka ƙarfin wutar lantarki na transceivers. Yana da 625 MHz ta tsohuwa amma yana iya zama na kowane mita.
- fmcb_gbtclk_m2c_p_0 shine agogon TMDS na HDMI RX. Hakanan ana amfani da wannan agogon don fitar da masu ɗaukar hoto na HDMI TX. Idan mitar da aka kawo shine 148.5 MHz, mai amfani_led_g[0] yana jujjuyawar kowane daƙiƙa.
Saitin Hardware
HDMI PHY Intel FPGA IP zane example shine HDMI 2.0b mai iyawa kuma yana yin madauki-ta zanga-zangar don daidaitaccen rafin bidiyo na HDMI.
Don gudanar da gwajin kayan aiki, haɗa na'urar da aka kunna HDMI kamar katin zane tare da kewayon HDMI zuwa mai haɗin HDMI RX akan katin 'yar Bitec HDMI 2.0, wanda ke ba da bayanan zuwa block RX transceiver da HDMI RX.
- Ruwa na HDMI yana yanke tashar tashar jiragen ruwa zuwa daidaitaccen rafi na bidiyo kuma yana aika shi zuwa ainihin dawo da agogo.
- Harshen HDMI RX yana ƙaddamar da bidiyo, ƙarin bayanai, da bayanan mai jiwuwa da za a mayar da su ta hanyar AXI4-stream interface zuwa HDMI TX core.
- Tashar tashar tashar HDMI ta katin 'yar FMC tana watsa hoton zuwa mai duba.
- Danna maɓallin cpu_resetn sau ɗaya don sake saitin tsarin.
Lura: Idan kana son yin amfani da wani kwamitin ci gaban Intel FPGA, dole ne ka canza ayyukan na'urar da ayyukan fil. Ana gwada saitin analog ɗin transceiver don kayan haɓakawa na Intel Arria 10 FPGA da katin 'yar Bitec HDMI 2.0. Kuna iya canza saitunan allon ku.
Tarihin Bita na Takardu don HDMI PHY Intel
FPGA IP Design ExampJagorar Mai Amfani
| Sigar Takardu | Intel Quartus Prime Version | Sigar IP | Canje-canje |
| 2022.07.20 | 22.2 | 1.0.0 | Sakin farko. |
Takardu / Albarkatu
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intel HDMI PHY FPGA IP Design Example [pdf] Jagorar mai amfani HDMI PHY FPGA IP Design Example, HDMI PHY, FPGA IP Design Example, HDMI PHY IP Design Example, FPGA IP Design Example, IP Design Exampku, 732781 |
