intel HDMI PHY FPGA IP Design Example alakaʻi hoʻohana
HDMI PHY Design ExampʻO ke alakaʻi hoʻomaka wikiwiki no nā polokalamu Intel® Arria® 10
ʻO ka HDMI PHY Intel® FPGA IP hoʻolālā example no nā polokalamu Intel Arria® 10 e hōʻike ana i kahi hoʻolālā hoʻouna hou HDMI 2.0 RX-TX e kākoʻo ana i ka hōʻuluʻulu ʻana a me ka hoʻāʻo ʻana i nā lako.
Ke hana ʻoe i kahi hoʻolālā example, hana 'akomi ka mea hooponopono parameter i ka files pono e simulate, hōʻuluʻulu, a ho'āʻo i ka hoʻolālā i ka lako.
Kiʻi 1. Nā ʻanuʻu hoʻomohala
ʻIke pili
HDMI PHY Intel FPGA IP alakaʻi hoʻohana
Hana i ka Hoʻolālā
E hoʻohana i ka HDMI PHY Intel FPGA IP hoʻoponopono hoʻoponopono ma ka polokalamu Intel Quartus® Prime e hana i ka hoʻolālā examples.
Kiʻi 2. Hana ʻana i ke Kahe Hoʻolālā
- E hana i kahi papahana e ʻimi ana i ka ʻohana polokalamu Intel Arria 10 a koho i ka mea makemake.
- Ma ka IP Catalog, e huli a kaomi pālua i nā Interface Protocols ➤ Audio & Video ➤ HDMI TX PHY Intel FPGA IP (a i ʻole HDMI RX PHY Intel FPGA IP). Hōʻike ʻia ka puka aniani IP Variant hou a i ʻole New IP Variant.
- E wehewehe i kahi inoa kiʻekiʻe no kāu hoʻololi IP maʻamau. Mālama ka mea hoʻoponopono hoʻoponopono i nā hoʻonohonoho hoʻololi IP ma kahi file kapa ʻia ʻo .ip a i ʻole .qsys.
- Kaomi OK. Hōʻike ʻia ka mea hoʻoponopono hoʻohālikelike.
Huina Intel. Ua mālama ʻia nā kuleana āpau. ʻO Intel, ka Intel logo, a me nā hōʻailona Intel ʻē aʻe he mau hōʻailona o Intel
ʻO ka hui a i ʻole kāna mau lālā. Mālama ʻo Intel i ka hana o kāna mau huahana FPGA a me semiconductor i nā kikoʻī o kēia manawa e like me ka palapala hōʻoia maʻamau o Intel, akā aia ke kuleana e hoʻololi i nā huahana a me nā lawelawe i kēlā me kēia manawa me ka ʻole o ka hoʻolaha. ʻAʻole ʻo Intel i kuleana a i ʻole kuleana e puka mai ana mai ka noi a i ʻole ka hoʻohana ʻana i kekahi ʻike, huahana, a i ʻole lawelawe i wehewehe ʻia ma ʻaneʻi koe wale nō i ʻae ʻia ma ke kākau ʻana e Intel. Manaʻo ʻia nā mea kūʻai aku Intel e loaʻa i ka mana hou o nā kikoʻī o nā hāmeʻa ma mua o ka hilinaʻi ʻana i kekahi ʻike i paʻi ʻia a ma mua o ke kau ʻana i nā kauoha no nā huahana a i ʻole nā lawelawe.
Hiki ke koi ʻia nā inoa a me nā hōʻailona ʻē aʻe ma ke ʻano he waiwai o nā poʻe ʻē aʻe. - Ma ka Design Exampma ka ʻaoʻao, koho iā Arria 10 HDMI RX-TX Retransmit.
- E koho i ka Simulation e hoʻohua i ka papa hoʻāʻo, a koho i ka Synthesis e hana i ka hoʻolālā ʻenehana example.
Pono ʻoe e koho i hoʻokahi o kēia mau koho no ka hana ʻana i ka hoʻolālā example files.
Inā koho ʻoe i nā mea ʻelua, ʻoi aku ka lōʻihi o ka manawa hana. - No Hanau File Hōʻano, koho iā Verilog a i ʻole VHDL.
- No ka pahu hoʻomohala pahuhopu, koho iā Intel Arria 10 GX FPGA Development
Kit. Inā koho ʻoe i kahi pahu hoʻomohala, a laila hoʻololi ka mea i hoʻopaʻa ʻia e hoʻohālikelike i ka hāmeʻa ma ka papa kuhikuhi. No Intel Arria 10 GX FPGA Development Kit, ʻo 10AX115S2F4I1SG ka mea paʻamau. - Kaomi Generate Example Hoʻolālā.
Hoʻopili a hoʻāʻo i ka Hoʻolālā
No ka hōʻuluʻulu ʻana a me ka holo ʻana i kahi hōʻike hōʻike ma ka ʻenehana exampka hoʻolālā, e hahai i kēia mau ʻanuʻu:
- E hōʻoia i ka lako kamepiula exampua pau ka hana hoʻolālā.
- E wehe i ka polokalamu Intel Quartus Prime a wehe i ka .qpf file: /quartus/a10_hdmi2_demo.qpf
- Kaomi i ka Processing ➤ Start Compilation.
- Ma hope o ka hōʻuluʻulu kūleʻa, a .sof file hana ʻia ma ka quartus/output_files papa kuhikuhi.
- Hoʻohui ʻo Bitec HDMI 2.0 FMC Daughter Card Rev 11 i ke awa FMC ma luna o ka papa B (J2).
- Hoʻohui iā TX (P1) o ke kāleka kaikamahine Bitec FMC i kahi kumu wikiō waho.
- Hoʻohui iā RX (P2) o ke kāleka kaikamahine Bitec FMC i kahi pahu wikiō waho a i ʻole ka mea nānā wikiō.
- E hōʻoia i nā hoʻololi āpau ma ka papa hoʻomohala ma ke kūlana paʻamau.
- E hoʻonohonoho i ka polokalamu Intel Arria 10 i koho ʻia ma ka papa hoʻomohala me ka hoʻohana ʻana i ka .sof file (Nā Mea Hana ➤ Programmer).
- Pono e hōʻike ʻia ka wikiō i hana ʻia mai ke kumu. Hoʻopili a hoʻāʻo i ka hoʻolālā
ʻIke pili
Intel Arria 10 FPGA Development Kit Ke alakaʻi hoʻohana
HDMI PHY Intel FPGA IP Design Example Nā ʻāpana
Papa 1. HDMI PHY Intel FPGA IP Design ExampNā ʻāpana no Intel Arria 10
Nā lakohana
Loaʻa kēia mau koho no nā polokalamu Intel Arria 10 wale nō.
| ʻĀpana | Waiwai | wehewehe |
| Loaʻa Design Example | ||
| E koho i ka Hoʻolālā | Hoʻouna hou ʻia ʻo Arria 10 HDMI RX-TX | E koho i ka hoʻolālā example e hanaia. |
| Hoʻolālā Example Files | ||
| Hoʻohālikelike | Pau, pio | E ho'ā i kēia koho e hana i nā mea e pono ai files no ka papa hoʻokolohua simulation. |
| Hoʻohuihui | Pau, pio | E ho'ā i kēia koho e hana i nā mea e pono ai files no ka hui pū ʻana o Intel Quartus Prime a me ka hōʻike ʻana i nā lako. |
| Hana ʻia ka ʻano HDL | ||
| Hanau File Hōʻano | ʻO Verilog, VHDL | E koho i kāu ʻano HDL makemake no ka hoʻolālā hana example filehoʻonoho.
Nānā: Hoʻoholo wale kēia koho i ke ʻano no ka IP pae kiʻekiʻe i hana ʻia files. ʻO nā mea ʻē aʻe a pau files (eg, example testbenches a me ka pae kiʻekiʻe files no ka hōʻike hāmeʻa) aia ma Verilog HDL format. |
| Puke Hoʻomohala Pahu | ||
| E koho i ka Papa | ʻAʻohe pahu hoʻomohala, | E koho i ka papa no ka hoʻolālā i manaʻo ʻia example. |
| Arria 10 GX FPGA Development Kit,
Kiko Hoʻomohala Kuʻuna |
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| Mea paahana | ||
| E hoʻololi i ka hāmeʻa pahuhopu | Pau, pio | E hoʻā i kēia koho a koho i ka ʻano mea hana i makemake ʻia no ka pahu hoʻomohala. |
HDMI 2.0 PHY Design Example
ʻO ka HDMI PHY Intel FPGA IP hoʻolālā exampHōʻike ʻo ia i hoʻokahi ala HDMI hoʻohālikelike ʻano loopback me ʻekolu mau kaha RX a me ʻehā mau kaha TX, e hana ana ma nā helu ʻikepili a hiki i 6 Gbps.
ʻO ka HDMI PHY Intel FPGA IP design example like me ka hoʻolālā exampi hana ʻia ma ka HDMI Intel FPGA IP core. Eia naʻe, kēia hoʻolālā exampHoʻohana ʻo ia i ka mea hoʻoponopono TX PHY, RX PHY, a me PHY hou ma kahi o ka RTL maʻamau i ka HDMI Intel FPGA IP core design example.
Kiʻi 3. HDMI 2.0 PHY Design Example
| Module | wehewehe |
| RX PHY | Hoʻihoʻi ka RX PHY i ka ʻikepili HDMI serial a hoʻouna i kēia i ke kumu HDMI RX ma ke ʻano like ʻole ma nā kikowaena uaki i hoʻihoʻi ʻia (rx_clk[2:0]). Hoʻololi ʻia ka ʻikepili i ke wikiō |
| Module | wehewehe |
| ʻikepili e hoʻopuka ʻia ma o ka wikiō AXI4-stream. Hoʻouna pū ka RX PHY i nā hōʻailona vid_clk a me ls_clk i ke kumu HDMI RX ma o ka pilina PHY. | |
| HDMI TX Core | Loaʻa i ka HDMI TX core ka ʻikepili wikiō AXI4-stream a hoʻopili i kēia i ka ʻikepili parallel format HDMI. Hoʻouna ka HDMI TX core i kēia ʻikepili i ka TX PHY. |
| HDMI RX Core | Loaʻa ka IP i ka ʻikepili serial mai ka RX PHY a hana i ka alignment data, channel deskew, TMDS decoding, auxiliary data decoding, video data decoding, audio data decoding, and descrambling. |
| TX PHY | Loaʻa a hoʻokaʻawale i nā ʻikepili like mai ka HDMI TX core a hoʻopuka i nā kahawai HDMI TMDS. Hoʻopuka ka TX PHY i ka tx_clk no ke kumu HDMI TX. Hoʻopuka pū ka TX PHY i ka vid_clk a me ls_clk a hoʻouna i kēia mau hōʻailona i ke kumu HDMI TX ma o ka interface PHY. |
| IOPLL | Hoʻopuka i ka 300 MHz AXI stream stream clock no ka AXI4-stream interface. |
| I2C Kumu | No ka hoʻonohonoho ʻana i nā ʻāpana PCB like ʻole. |
Pono nā lako lako a me nā lako polokalamu
Hoʻohana ʻo Intel i ka lako a me ka lako polokalamu e hoʻāʻo ai i ka hoʻolālā example.
Lako lako
- ʻO Intel Arria 10 GX FPGA Development Kit
- Puna HDMI (Ui Hana Kaʻina Hana Kiʻi (GPU)
- Hoʻomoʻa HDMI (Mono)
- Kāleka kaikamahine Bitec HDMI FMC 2.0 (Hoʻoponopono 11)
- Nā kaula HDMI
lako polokalamu
- ʻO Intel Quartus Prime Pro Edition (no ka hoʻāʻo ʻana i nā lako lako)
- ModelSim* – Intel FPGA Edition, ModelSim – Intel FPGA Starter Edition, NCSim,
Riviera-PRO*, VCS* (Verilog HDL wale nō)/VCS MX, a i ʻole Xcelium* ʻO ka simulator Parallel
Papa kuhikuhi
Aia nā papa kuhikuhi i nā mea i hana ʻia file no ka HDMI Intel FPGA IP hoʻolālā example.
Kiʻi 4. Papa kuhikuhi no ka Design Example
Kahe Kaʻina Hana Hou
Kiʻi 5. Kahe ʻana o ka hoʻonohonoho hou ʻana i nā helu he nui
Hōʻike ke kiʻi i ke kahe o ka hoʻonohonoho hou ʻana o ka mea hoʻoponopono i ka wā e loaʻa ai ke kahawai ʻikepili komo a me ke alapine o ka uaki kuhikuhi, a i ʻole ke wehe ʻia ka transceiver.
Nā hōʻailona Interface
Hoʻopaʻa nā papa i nā hōʻailona no ka HDMI PHY Intel FPGA IP design example.
Papa 3. Nā hōʻailona kiʻekiʻe
| hōʻailona | Kuhikuhi | Laulā | wehewehe |
| Hōʻailona Oscillator ma luna o ka moku | |||
| clk_fpga_b3_p | Hookomo | 1 | 100 MHz uaki holo manuahi no ka uaki kuhikuhi kumu |
| refclk_fmcb_p | Hookomo | 1 | Uaki kuhikuhi helu paʻa no ka calibration mana o ka transceiver. ʻO 625 MHz ma ka paʻamau akā hiki ke hana i kēlā me kēia alapine |
| Nā pihi hoʻohana a me nā LED | |||
| cpu_resetn | Hookomo | 1 | Hoʻoponopono honua |
| mea hoʻohana_led_g | Hoʻopuka | 2 | Hōʻike LED ʻōmaʻomaʻo |
| Nā Pin Kāleka Kāleka HDMI FMC ma FMC Port B | |||
| fmcb_gbtclk_m2c_p_0 | Hookomo | 1 | HDMI RX TMDS uaki |
| fmcb_dp_m2c_p | Hookomo | 3 | ʻO HDMI RX ʻulaʻula, ʻōmaʻomaʻo, a me nā kahawai ʻikepili uliuli
• ka hoʻoponopono hou ʻana o ke kāleka kaikamahine Bitec 11 — [0]: RX TMDS Channel 1 (Omaomao) — [1]: RX TMDS Channel 2 (ʻulaʻula) — [2]: RX TMDS Channel 0 (Blue) |
| fmcb_dp_c2m_p | Hoʻopuka | 4 | ʻO ka uaki HDMI TX, ʻulaʻula, ʻōmaʻomaʻo, a me nā kahawai ʻikepili polū
• ka hoʻoponopono hou ʻana o ke kāleka kaikamahine Bitec 11 — [0]: TX TMDS Channel 2 (ʻulaʻula) — [1]: TX TMDS Channel 1 (Omaomao) — [2]: TX TMDS Channel 0 (Blue) — [3]: TX TMDS Clock Channel |
| fmcb_la_rx_p_9 | Hookomo | 1 | ʻIke ʻia ka mana HDMI RX +5V |
| fmcb_la_rx_p_8 | Hookomo | 1 | ʻIke ʻia ke plug wela HDMI RX |
| fmcb_la_rx_n_8 | Hookomo | 1 | HDMI RX I2C SDA no DDC a me SCDC |
| fmcb_la_tx_p_10 | Hookomo | 1 | HDMI RX I2C SCL no DDC a me SCDC |
| fmcb_la_tx_p_12 | Hookomo | 1 | ʻIke ʻia ke plug wela HDMI TX |
| fmcb_la_tx_n_12 | Hookomo | 1 | HDMI I2C SDA no DDC a me SCDC |
| fmcb_la_rx_p_10 | Hookomo | 1 | HDMI I2C SCL no DDC a me SCDC |
| fmcb_la_tx_p_11 | Hookomo | 1 | HDMI I2C SDA no ka mana redriver |
| fmcb_la_rx_n_9 | Hookomo | 1 | HDMI I2C SCL no ka mana redriver |
Papahana Uku
ʻO kēia ka papa kuhikuhi o ka hoʻolālā ʻana o ka HDMI PHY Intel FPGA IP design example:
- ʻO clk_fpga_b3_p he 100 MHz i hoʻopaʻa ʻia no ka holo ʻana i ka ʻōnaehana NIOS a me nā hana mana. Inā pololei ka alapine i hāʻawi ʻia, huli ka mea hoʻohana_led_g[1] no kēlā me kēia kekona.
- ʻO refclk_fmcb_p he uaki kuhikuhi paʻa no ka calibration mana o nā transceivers. ʻO 625 MHz ma ka paʻamau akā hiki ke hana i kēlā me kēia alapine.
- ʻO fmcb_gbtclk_m2c_p_0 ka uaki TMDS no HDMI RX. Hoʻohana ʻia kēia uaki e hoʻokele i nā transceivers HDMI TX. Inā he 148.5 MHz ka alapine i hāʻawi ʻia, huli ka mea hoʻohana_led_g[0] no kēlā me kēia kekona.
Hoʻonohonoho lako lako
ʻO ka HDMI PHY Intel FPGA IP hoʻolālā exampHiki iā ia ke HDMI 2.0b a hana i kahi hōʻike loop-through no kahi kahawai wikiō HDMI maʻamau.
No ka holo ʻana i ka hoʻāʻo hāmeʻa, hoʻopili i kahi mea hana HDMI e like me ke kāleka kiʻi me ka interface HDMI i ka mea hoʻohui HDMI RX ma ke kāleka kaikamahine Bitec HDMI 2.0, e hoʻokele i ka ʻikepili i ka poloka transceiver RX a me HDMI RX.
- Hoʻokaʻawale ka pahu HDMI i ke awa i loko o kahi kahawai wikiō maʻamau a hoʻouna iā ia i ke kumu hoʻihoʻi o ka uaki.
- ʻO ka HDMI RX core e hoʻokaʻawale i ka wikiō, kōkua, a me ka ʻikepili leo e hoʻihoʻi ʻia ma o AXI4-stream interface i ka HDMI TX core.
- ʻO ke awa kumu HDMI o ke kāleka kaikamahine FMC e hoʻouna i ke kiʻi i kahi nānā.
- E kaomi i ke pihi cpu_resetn i hoʻokahi manawa e hana hou i ka ʻōnaehana.
Nānā: Inā makemake ʻoe e hoʻohana i kahi papa hoʻomohala Intel FPGA ʻē aʻe, pono ʻoe e hoʻololi i nā haʻawina a me nā hana pin. Hoʻāʻo ʻia ka hoʻonohonoho analog transceiver no ka Intel Arria 10 FPGA development kit a me ke kāleka kaikamahine Bitec HDMI 2.0. Hiki iā ʻoe ke hoʻololi i nā hoʻonohonoho no kāu papa ponoʻī.
Moʻolelo Hoʻoponopono Hou no ka HDMI PHY Intel
FPGA IP Design Example alakaʻi hoʻohana
| Palapala Palapala | ʻO Intel Quartus Prime Version | Manaʻo IP | Nā hoʻololi |
| 2022.07.20 | 22.2 | 1.0.0 | Hoʻokuʻu mua. |
Palapala / Punawai
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intel HDMI PHY FPGA IP Design Example [pdf] Ke alakaʻi hoʻohana HDMI PHY FPGA IP Design Example, HDMI PHY, FPGA IP Design Example, HDMI PHY IP Design Example, FPGA IP Design Example, IP Design Example, 732781 |
