intel HDMI PHY FPGA IP Design Example User Guide
HDMI PHY Design Example Ta'iala Amata vave mo Intel® Arria® 10 Masini
Le HDMI PHY Intel® FPGA IP design example mo Intel Arria® 10 masini o loʻo faʻaalia ai le HDMI 2.0 RX-TX retransmit mamanu e lagolagoina le tuʻufaʻatasia ma suʻega meafaigaluega.
A e fatuina se mamanu example, e otometi lava ona fatuina e le faatonu parameter le files e manaʻomia e faʻataʻitaʻi, faʻapipiʻi, ma suʻe le mamanu i meafaigaluega.
Ata 1. Laasaga Atina'e
Fa'amatalaga Fa'atatau
HDMI PHY Intel FPGA IP Taiala mo Tagata Fa'aoga
Fausiaina o le Fuafuaga
Fa'aoga le HDMI PHY Intel FPGA IP fa'ata'ita'iga fa'atonu i le Intel Quartus® Prime software e fa'atupu ai le mamanu fa'atasiamples.
Ata 2. Fa'atupuina o le Fa'asologa o Fuafuaga
- Fausia se poloketi e faʻatatau i le Intel Arria 10 masini aiga ma filifili le masini manaʻomia.
- I le IP Catalog, su'e ma kiliki-lua Interface Protocols ➤ Audio & Vitio ➤ HDMI TX PHY Intel FPGA IP (po'o HDMI RX PHY Intel FPGA IP). O lo'o fa'aali mai le fa'amalama o le New IP Variant po'o le New IP Variation.
- Fa'ailoa se igoa pito i luga mo lau suiga masani IP. E fa'asaoina e le fa'atonu fa'amaufa'ailoga le fa'atulagaina o suiga o le IP ile a file igoa .ip poʻo .qsys.
- Kiliki OK. E aliali mai le fa'atonu fa'amaufa'ailoga.
Intel Corporation. Ua taofia aia tatau uma. Intel, le Intel logo, ma isi fa'ailoga Intel o fa'ailoga fa'atau a Intel
Faalapotopotoga po'o ona lala. E fa'amaonia e Intel le fa'atinoina o ana oloa FPGA ma semiconductor i fa'amatalaga o lo'o iai nei e tusa ai ma le fa'atonuga masani a Intel, ae fa'asaoina le aia tatau e fai ai suiga i so'o se oloa ma auaunaga i so'o se taimi e aunoa ma se fa'aaliga. E leai se tiute po'o se noataga e afua mai i le talosaga po'o le fa'aogaina o so'o se fa'amatalaga, oloa, po'o se auaunaga o lo'o fa'amatalaina i i'i se'i vagana ua malilie i ai i se faiga tusitusia e Intel. Ua fautuaina tagata fa'atau Intel ina ia maua le fa'amatalaga lata mai o fa'amatalaga masini a'o le'i fa'alagolago i so'o se fa'amatalaga fa'asalalau ma a'o le'i tu'uina atu oka mo oloa po'o tautua.
O isi igoa ma fa'ailoga e mafai ona ta'ua o se meatotino a isi. - I luga ole Design Exampi le tab, filifili Arria 10 HDMI RX-TX Retransmit.
- Filifili Fa'ata'ita'iga e fa'atupu ai le su'ega, ma filifili Fa'atasi e fa'atupuina ai le fa'asologa o meafaigaluegaample.
E tatau ona e filifilia se tasi o nei filifiliga e fa'atupu ai le fa'ata'ita'igaample files.
Afai e te filifilia uma e lua, o le taimi o le gaosiga e umi atu. - Mo Fausia File Fa'asologa, filifili Verilog po'o VHDL.
- Mo le Pusa Atina'e, filifili le Intel Arria 10 GX FPGA Development
Pusa. Afai e te filifilia se pusa atinaʻe, ona suia lea o le masini sini e fetaui ma le masini i luga o le laupapa sini. Mo Intel Arria 10 GX FPGA Development Kit, o le masini fa'aletonu o le 10AX115S2F4I1SG. - Kiliki Fausia Example Design.
Tu'ufa'atasia ma Fa'ata'ita'i le Fuafuaga
E fa'aputu ma fa'atino se su'ega fa'ata'ita'iga ile meafaigaluega fa'aample mamanu, mulimuli i laasaga nei:
- Ia mautinoa meafaigaluega exampua mae'a le fausiaina o mamanu.
- Tatala le polokalama Intel Quartus Prime ma tatala le .qpf file: /quartus/a10_hdmi2_demo.qpf
- Kiliki Processing ➤ Amata Fa'aopoopo.
- A mae'a le fa'aputuga manuia, a .sof file e gaosia i le quartus/output_files directory.
- Fa'afeso'ota'i le Bitec HDMI 2.0 FMC Daughter Card Rev 11 i le FMC port B (J2).
- Fa'afeso'ota'i le TX (P1) o le Bitec FMC daughter card i se puna vitiō fafo.
- Fa'afeso'ota'i le RX (P2) o le kata tama'ita'i Bitec FMC i se atigi vitiō i fafo po'o se su'esu'e vitiō.
- Ia mautinoa o ki uma i luga o le laupapa atina'e o lo'o i le tulaga le lelei.
- Fa'atulaga le masini Intel Arria 10 filifilia i luga o le laupapa atina'e e fa'aaoga ai le .sof file (Meafaigaluega ➤ Polokalama).
- E tatau i le tagata su'esu'e ona fa'aalia le vitio na gaosia mai le puna. Tu'ufa'atasia ma Fa'ata'ita'i le Fuafuaga
Fa'amatalaga Fa'atatau
Intel Arria 10 FPGA Development Kit Taiala mo Tagata
HDMI PHY Intel FPGA IP Design Example Parameter
Laulau 1. HDMI PHY Intel FPGA IP Design Example Parameters mo Intel Arria 10
Meafaigaluega
O avanoa nei e avanoa mo Intel Arria 10 masini.
| Parameter | Taua | Fa'amatalaga |
| Avanoa Design Example | ||
| Filifili Design | Arria 10 HDMI RX-TX Toe lafo | Filifili le mamanu example e gaosia. |
| Design Example Files | ||
| Fa'ata'oto | Ua pe, ua pe | Fa'aola lenei filifiliga e fa'atupu ai mea e mana'omia files mo le su'ega fa'ata'ita'iga. |
| Fa'asologa | Ua pe, ua pe | Fa'aola lenei filifiliga e fa'atupu ai mea e mana'omia filemo Intel Quartus Prime tu'ufa'atasiga ma fa'ata'ita'iga meafaigaluega. |
| Fausia le HDL Format | ||
| Fa'atupu File Fa'asologa | Verilog, VHDL | Filifili lau fa'atulagaga HDL e te mana'o iai mo le fa'ata'ita'iga fa'atupuample fileseti.
Fa'aaliga: O lenei filifiliga e na'o le fa'atulagaina mo le fa'atupuina o le tulaga maualuga IP files. O isi uma files (faataitaiga, example testbenches ma le tulaga maualuga files mo meafaigaluega faʻataʻitaʻiga) o loʻo i le Verilog HDL format. |
| Pusa Atina'e Sini | ||
| Filifili le Komiti Faatino | Leai se atigi pusa, | Filifili le laupapa mo le mamanu fa'atatauample. |
| Arria 10 GX FPGA Development Kit,
Pusa Atina'e aganu'u |
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| Meafaigaluega Sini | ||
| Suia Mea Fa'atatau | Ua pe, ua pe | Fa'aola le filifiliga lea ma filifili le mea e sili ona fiafia i ai masini mo le atina'e pusa. |
HDMI 2.0 PHY Design Example
Le HDMI PHY Intel FPGA IP design exampO lo'o fa'aalia ai le tasi HDMI fa'ata'ita'iga fa'ata'ita'i fa'atasi e aofia ai laina RX e tolu ma laina TX e fa, o lo'o fa'agaoioia i fua fa'amaumauga e o'o atu i le 6 Gbps.
Le fa'atupuina HDMI PHY Intel FPGA IP design example tutusa ma le mamanu example gaosia i le HDMI Intel FPGA IP autu. Ae ui i lea, o lenei mamanu exampe fa'aaoga le TX PHY, RX PHY, ma le PHY fou arbiter nai lo le RTL masani ile HDMI Intel FPGA IP core design example.
Ata 3. HDMI 2.0 PHY Design Example
| Module | Fa'amatalaga |
| RX PHY | O le RX PHY e toe fa'afo'i mai fa'amaumauga HDMI ma lafo atu i le HDMI RX autu i le fa'atusa tutusa i luga o le uati toe maua (rx_clk[2:0]). O faʻamatalaga e faʻavasegaina i le vitio |
| Module | Fa'amatalaga |
| fa'amatalaga e tu'uina atu e ala ile AXI4-stream video. O le RX PHY fo'i e tu'uina atu faailoilo vid_clk ma ls_clk i le HDMI RX autu e ala i le PHY interface. | |
| HDMI TX Core | O le HDMI TX autu e mauaina AXI4-stream vitio faʻamatalaga ma faʻapipiʻi lenei mea ile HDMI faʻatulagaina faʻamaumauga tutusa. O le HDMI TX autu e auina atu nei faʻamatalaga i le TX PHY. |
| HDMI RX Core | E maua e le IP le fa'asologa o fa'amaumauga mai le RX PHY ma fa'atino le fa'aogaina o fa'amaumauga, kesi ala, decoding TMDS, fa'avasegaina o fa'amatalaga fesoasoani, fa'avasegaina o fa'amatalaga vitio, fa'avasegaina o fa'amatalaga leo, ma le fa'avasegaina. |
| TX PHY | Maua ma fa'asalalau fa'amaumauga tutusa mai le HDMI TX autu ma fa'auluina ala HDMI TMDS. Le TX PHY maua tx_clk mo le HDMI TX autu. O le TX PHY fo'i e fa'atupuina le vid_clk ma le ls_clk ma tu'uina atu nei fa'ailoga i le HDMI TX autu e ala i le fa'aoga PHY. |
| IOPLL | Fa'atupuina 300 MHz AXI uati vaitafe faasologa mo le AXI4- vaitafe atina'e. |
| I2C Matai | E faʻapipiʻi vaega eseese PCB. |
Meafaigaluega ma Polokalama Manaoga
E fa'aogaina e Intel meafaigaluega ma polokalama fa'akomepiuta nei e su'e ai le mamanu example.
Meafaigaluega
- Intel Arria 10 GX FPGA Atina'e Kit
- Punavai HDMI (Vaega Fa'ata'ita'i Ata (GPU)
- Su'ega HDMI (Monitor)
- Bitec HDMI FMC 2.0 kata tama teine (Fa'aaliga 11)
- Uaea HDMI
Polokalama
- Intel Quartus Prime Pro Edition (mo su'ega meafaigaluega)
- ModelSim* – Intel FPGA Edition, ModelSim – Intel FPGA Starter Edition, NCSim,
Riviera-PRO*, VCS* (Verilog HDL na'o)/VCS MX, po'o le Xcelium* Parallel simulator
Fa'atonuga Fa'atonu
O fa'atonuga o lo'o i ai mea na gaosia file mo le HDMI Intel FPGA IP mamanu example.
Ata 4. Fa'atonuga Fa'atonu mo le Design Example
Toe fa'atulagaina Fa'asologa Fa'asologa
Ata 5. Fa'asologa o Fa'asologa Fa'asologa Fa'atele
O le ata o loʻo faʻaalia ai le tele-rate reconfiguration sequence faʻasologa o le pule pe a maua faʻamatalaga faʻamatalaga ma faʻasino taimi masani, poʻo le taimi e tatala ai le transceiver.
Fa'ailoga Fa'afeso'ota'i
O laulau o lo'o lisiina ai fa'ailoga mo le HDMI PHY Intel FPGA IP design example.
Laulau 3. Fa'ailoga Tulaga Maualuga
| Fa'ailoga | Fa'atonuga | Lautele | Fa'amatalaga |
| Fa'ailoga ole Oscillator i luga ole laupapa | |||
| clk_fpga_b3_p | Ulufale | 1 | 100 MHz uati tamo'e fua mo le uati faasinomaga autu |
| refclk_fmcb_p | Ulufale | 1 | Uati fa'asino fua fa'atatau mo le fa'avasegaina o le eletise o le transceiver. E 625 MHz ona o le faaletonu ae e mafai ona o soo se taimi |
| Fa'aoga Push Buttons ma LED | |||
| cpu_resetn | Ulufale | 1 | Toe fa'alelalolagi |
| user_led_g | Tuuina atu | 2 | Fa'aaliga LED lanu meamata |
| HDMI FMC Daughter Card Pins ile FMC Port B | |||
| fmcb_gbtclk_m2c_p_0 | Ulufale | 1 | Uati HDMI RX TMDS |
| fmcb_dp_m2c_p | Ulufale | 3 | HDMI RX mūmū, lanu meamata, ma le lanumoana alavai fa'amatalaga
• Su'esu'ega pepa tama teine Bitec 11 — [0]: RX TMDS Alaala 1 (Munumea) — [1]: RX TMDS Alaala 2 (Mula) — [2]: RX TMDS Alaala 0 (Laumanu) |
| fmcb_dp_c2m_p | Tuuina atu | 4 | HDMI TX uati, mumu, lanu meamata, ma le lanumoana alavai faʻamatalaga
• Su'esu'ega pepa tama teine Bitec 11 — [0]: TX TMDS Alaala 2 (Mula) — [1]: TX TMDS Alaala 1 (Munumea) — [2]: TX TMDS Alaala 0 (Laumanu) — [3]: Alaala Uati TX TMDS |
| fmcb_la_rx_p_9 | Ulufale | 1 | HDMI RX +5V mana iloa |
| fmcb_la_rx_p_8 | Ulufale | 1 | HDMI RX so'o vevela iloa |
| fmcb_la_rx_n_8 | Ulufale | 1 | HDMI RX I2C SDA mo DDC ma SCDC |
| fmcb_la_tx_p_10 | Ulufale | 1 | HDMI RX I2C SCL mo DDC ma SCDC |
| fmcb_la_tx_p_12 | Ulufale | 1 | HDMI TX pa'u vevela iloa |
| fmcb_la_tx_n_12 | Ulufale | 1 | HDMI I2C SDA mo DDC ma SCDC |
| fmcb_la_rx_p_10 | Ulufale | 1 | HDMI I2C SCL mo DDC ma SCDC |
| fmcb_la_tx_p_11 | Ulufale | 1 | HDMI I2C SDA mo redriver pulea |
| fmcb_la_rx_n_9 | Ulufale | 1 | HDMI I2C SCL mo le puleaina o le redriver |
Fuafuaga uati
O lo'o ta'ua i lalo le fa'ailoga o le HDMI PHY Intel FPGA IP design exampLe:
- clk_fpga_b3_p o se 100 MHz fua fa'atatau uati mo le fa'agaioia o le fa'agaioiina o le NIOS ma galuega fa'atonutonu. Afai e sa'o le alaleo o lo'o tu'uina atu, e suitulaga le user_led_g[1] mo sekone ta'itasi.
- refclk_fmcb_p ose uati fa'asinoga fua faatatau mo le fa'atonuina o le eletise o le transceivers. E 625 MHz ona o le faaletonu ae e mafai ona o soo se taimi.
- fmcb_gbtclk_m2c_p_0 o le uati TMDS mo HDMI RX. O lenei uati e faʻaaogaina foi e ave ai le HDMI TX transceivers. Afai o le alaleo e tu'uina atu o le 148.5 MHz, o le user_led_g[0] e sui mo sekone ta'itasi.
Seti Meafaigaluega
Le HDMI PHY Intel FPGA IP design exampO le HDMI 2.0b e mafai ma fa'atino se fa'ata'ita'iga fa'asolosolo mo se fa'ata'ita'iga ata vitio HDMI.
Ina ia faʻataʻitaʻiina le suʻega meafaigaluega, faʻafesoʻotaʻi se masini e mafai ona faʻaogaina le HDMI e pei o se kata faʻataʻitaʻiga ma le HDMI faʻafesoʻotaʻi i le HDMI RX fesoʻotaʻiga i luga o le Bitec HDMI 2.0 daughter card, lea e faʻafeiloaʻi ai faʻamatalaga i le transceiver RX poloka ma HDMI RX.
- O le su'ega HDMI e fa'aliliuina le uafu i totonu o se ata vitio masani ma auina atu i le uati toe fa'aleleia.
- O le HDMI RX autu e fa'aliliuina le vitio, ausilali, ma fa'amatalaga leo e toe fa'afo'i i tua e ala i le AXI4-stream interface i le HDMI TX core.
- O le HDMI source port o le FMC daughter card e fa'asalalauina le ata i se mata'itu.
- Oomi le cpu_resetn fa'amau tasi e fai ai le toe setiina o le faiga.
Fa'aaliga: Afai e te manaʻo e faʻaoga se isi Intel FPGA atinaʻe laupapa, e tatau ona e suia le faʻaogaina o masini ma le pine. O le transceiver analog setting e tofotofoina mo le Intel Arria 10 FPGA development kit ma Bitec HDMI 2.0 daughter card. E mafai ona e suia tulaga mo lau lava laupapa.
Tala'aga Toe Iloiloga o Fa'amaumauga mo le HDMI PHY Intel
FPGA IP Design Example User Guide
| Fa'amatalaga Fa'amaumauga | Intel Quartus Prime Version | IP Version | Suiga |
| 2022.07.20 | 22.2 | 1.0.0 | Fa'asalalauga muamua. |
Pepa / Punaoa
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intel HDMI PHY FPGA IP Design Example [pdf] Taiala mo Tagata Fa'aoga HDMI PHY FPGA IP Design Example, HDMI PHY, FPGA IP Design Example, HDMI PHY IP Design Example, FPGA IP Design Example, IP Design Example, 732781 |
