Intel HDMI PHY FPGA IP Design Example Bukana ea Mosebelisi
HDMI PHY Design Example Tataiso ea ho Qala ka Potlako bakeng sa Lisebelisoa tsa Intel® Arria® 10
Moetso oa HDMI PHY Intel® FPGA IP example bakeng sa lisebelisoa tsa Intel Arria® 10 e na le moralo oa ho fetisa oa HDMI 2.0 RX-TX o tšehetsang ho bokella le ho hlahloba hardware.
Ha o hlahisa ex designample, mohlophisi oa parameter o iketsetsa faele ea files bohlokoa ho etsisa, ho bokella, le ho leka moralo ho hardware.
Setšoantšo sa 1. Mehato ea Ntšetso-pele
Lintlha Tse Amanang
HDMI PHY Intel FPGA IP User Guide
Ho Hlahisa Moralo
Sebelisa HDMI PHY Intel FPGA IP parameter editor ho Intel Quartus® Prime software ho hlahisa moqapi oa khale.amples.
Setšoantšo sa 2. Ho Hlahisa Phallo ea Moqapi
- Theha morero o lebisitseng lelapa la sesebelisoa sa Intel Arria 10 ebe u khetha sesebelisoa se lakatsehang.
- Ho IP Catalog, fumana le ho tobetsa habeli Interface Protocols ➤ Audio & Video ➤ HDMI TX PHY Intel FPGA IP (kapa HDMI RX PHY Intel FPGA IP). Ho hlaha fensetere e ncha ea IP Variant kapa New IP Variation.
- Hlalosa lebitso la boemo bo holimo bakeng sa IP ea hau ea tloaelo. Mohlophisi oa paramethara o boloka litlhophiso tsa phapang ea IP ho a file e bitsoang .ip kapa .qsys.
- Tobetsa OK. Mohlophisi oa parameter oa hlaha.
Intel Corporation. Litokelo tsohle li sirelelitsoe. Intel, logo ea Intel, le matšoao a mang a Intel ke matšoao a khoebo a Intel
Mokhatlo kapa litšehetso tsa eona. Intel e tiisa ts'ebetso ea FPGA ea eona le lihlahisoa tsa semiconductor ho latela litlhaloso tsa hajoale ho latela waranti e tloaelehileng ea Intel, empa e na le tokelo ea ho etsa liphetoho ho lihlahisoa le lits'ebeletso life kapa life ka nako efe kapa efe ntle le tsebiso. Intel ha e nke boikarabello kapa boikarabello bo hlahang ka lebaka la kopo kapa ts'ebeliso ea tlhahisoleseling efe kapa efe, sehlahisoa, kapa ts'ebeletso e hlalositsoeng mona ntle le ha ho lumellane ka ho hlaka ka lengolo ke Intel. Bareki ba Intel ba eletsoa ho fumana mofuta oa morao-rao oa litlhaloso tsa sesebelisoa pele ba itšetleha ka tlhahisoleseling efe kapa efe e phatlalalitsoeng le pele ba beha litaelo tsa lihlahisoa kapa lits'ebeletso.
Mabitso a mang le mabitso a mang a ka nkoa e le thepa ea ba bang. - Ka Moqapi Exampho tab, khetha Arria 10 HDMI RX-TX Retransmit.
- Khetha Simulation ho hlahisa testbench, 'me u khethe Synthesis ho hlahisa moralo oa hardware example.
U tlameha ho khetha bonyane e 'ngoe ea likhetho tsena ho hlahisa sebopeho sa example files.
Haeba u khetha ka bobeli, nako ea tlhahiso e telele. - Bakeng sa Hlahisa File Fomata, khetha Verilog kapa VHDL.
- Bakeng sa Target Development Kit, khetha Intel Arria 10 GX FPGA Development
Kit. Haeba u khetha ntshetsopele Kit, ka nako eo shebiloeng sesebediswa fetoha ho bapisa sesebediswa ka boto shebiloeng. Bakeng sa Intel Arria 10 GX FPGA Development Kit, sesebelisoa sa kamehla ke 10AX115S2F4I1SG. - Tobetsa Hlahisa Example Design.
Ho Kopanya le ho Lekola Moralo
Ho bokella le ho etsa tlhahlobo ea pontšo ho hardware example design, latela mehato ena:
- Netefatsa hore hardware example tlhahiso ea moralo e felile.
- Qala software ea Intel Quartus Prime 'me u bule file ea .qpf file: /quartus/a10_hdmi2_demo.qpf
- Tobetsa Ho sebetsa ➤ Qala ho Kopanya.
- Ka mor'a ho bokella ka katleho, a .sof file e hlahiswa ka quartus/ output_files directory.
- Hokela Bitec HDMI 2.0 FMC Morali oa Card Rev 11 boema-kepeng ba FMC B (J2).
- Hokela TX (P1) ea karete ea morali ea Bitec FMC mohloling oa video o kantle.
- Hokela RX (P2) ea karete ea morali ea Bitec FMC ho sinki ea kantle ea video kapa tlhahlobo ea video.
- Netefatsa hore li-switches tsohle tse botong ea ntlafatso li maemong a kamehla.
- Lokisa sesebelisoa sa Intel Arria 10 se khethiloeng ka har'a boto ea nts'etsopele u sebelisa tlhahiso ea .sof file (Lisebelisoa ➤ Moetsi oa Lenaneo).
- Mohlahlobi o lokela ho bonts'a video e hlahisitsoeng mohloling. Ho Kopanya le ho Lekola Moralo
Lintlha Tse Amanang
Intel Arria 10 FPGA Development Kit User Guide
HDMI PHY Intel FPGA IP Design Example Li-Parameters
Letlapa la 1. HDMI PHY Intel FPGA IP Design Example Parameters bakeng sa Intel Arria 10
Lisebelisoa
Likhetho tsena li fumaneha bakeng sa lisebelisoa tsa Intel Arria 10 feela.
| Paramethara | Boleng | Tlhaloso |
| Moqapi o Fumanehang Example | ||
| Kgetha Moralo | Arria 10 HDMI RX-TX Retransmit | Khetha mohlala oa moraloample tla hlahisoa. |
| Moqapi Example Files | ||
| Ketsiso | Bulehile, Tima | Bulela khetho ena ho etsa se hlokahalang files bakeng sa ketsiso testbench. |
| Synthesis | Bulehile, Tima | Bulela khetho ena ho etsa se hlokahalang files bakeng sa pokello ea Intel Quartus Prime le pontšo ea hardware. |
| HDL Format e entsoeng | ||
| Hlahisa File Sebopeho | Verilog, VHDL | Khetha mofuta oo u o ratang oa HDL bakeng sa sebopeho se hlahisitsoeng sa example filebeha.
Hlokomela: Khetho ena e khetha feela sebopeho sa IP ea boemo bo holimo e hlahisitsoeng files. Tse ling kaofela files (mohlala, mohlalaample testbenches le boemo bo holimo files bakeng sa pontšo ea hardware) li ka sebopeho sa Verilog HDL. |
| Setsi sa Nts'etsopele se reriloeng | ||
| Khetha Boto | No Development Kit, | Khetha boto bakeng sa moralo o lebisitsoeng oa mohlalaample. |
| Arria 10 GX FPGA Development Kit,
Custom Development Kit |
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|
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| Sesebediswa se reriloeng | ||
| Fetola Sesebediswa se Lebeletsweng | Bulehile, Tima | Bulela khetho ena 'me u khethe mofuta o ratoang oa sesebelisoa bakeng sa lisebelisoa tsa ntlafatso. |
HDMI 2.0 PHY Design Example
Moetso oa HDMI PHY Intel FPGA IP example e bonts'a mohlala o le mong oa HDMI o ts'oanang oa loopback o nang le liteishene tse tharo tsa RX le liteishene tse 'ne tsa TX, tse sebetsang ka litefiso tsa data ho fihla ho 6 Gbps.
Moetso o hlahisitsoeng oa HDMI PHY Intel FPGA IP example e tšoana le ea moralo exampe hlahisitsoe ka HDMI Intel FPGA IP core. Leha ho le joalo, moralo ona example sebelisa TX PHY, RX PHY, le PHY arbiter e ncha sebakeng sa RTL e tloaelehileng ho HDMI Intel FPGA IP core design ex.ample.
Setšoantšo sa 3. HDMI 2.0 PHY Design Example
| Mojule | Tlhaloso |
| RX PHY | RX PHY e khutlisa data ea serial HDMI 'me e romele sena ho HDMI RX core ka sebopeho se ts'oanang libakeng tsa oache tse hlakotsoeng (rx_clk[2:0]). Lintlha li entsoe ka video |
| Mojule | Tlhaloso |
| data e tla hlahisoa ka video ea AXI4-stream. RX PHY e boetse e romella vid_clk le ls_clk matšoao ho HDMI RX core ka PHY interface. | |
| HDMI TX Core | Koko ea HDMI TX e amohela data ea video ea AXI4-stream ebe e e kenyetsa sena ho data ea sebopeho sa HDMI e bapileng. Moko oa HDMI TX o romella data ena ho TX PHY. |
| HDMI RX Core | IP e amohela data ea serial ho tsoa ho RX PHY mme e etsa ho tsamaisana ha data, deskew ea seteishene, TMDS decoding, decoding data decoding, video decoding, audio data decoding, le descrambling. |
| TX PHY | E amohela le ho hlophisa data e bapileng ho tsoa ho konokono ea HDMI TX le lihlahisoa tsa HDMI TMDS. TX PHY e hlahisa tx_clk bakeng sa konokono ea HDMI TX. TX PHY e boetse e hlahisa vid_clk le ls_clk mme e romela matšoao ana ho HDMI TX core ka PHY interface. |
| IOPLL | E hlahisa 300 MHz AXI serial stream clock bakeng sa sebopeho sa AXI4- stream. |
| Monghali oa I2C | Ho lokisa likarolo tse fapaneng tsa PCB. |
Litlhoko tsa Hardware le Software
Intel e sebelisa lisebelisoa tse latelang le software ho leka moralo oa example.
Lisebelisoa
- Intel Arria 10 GX FPGA Development Kit
- Mohloli oa HDMI (Yuniti ea processor ea Graphics (GPU)
- HDMI Sink (Monitor)
- Bitec HDMI FMC 2.0 karete ea morali (Revision 11)
- Lithapo tsa HDMI
Software
- Intel Quartus Prime Pro Edition (bakeng sa tlhahlobo ea lisebelisoa)
- ModelSim* - Khatiso ea Intel FPGA, ModelSim - Intel FPGA Starter Edition, NCSim,
Riviera-PRO*, VCS* (Verilog HDL feela)/VCS MX, kapa Xcelium* Parallel simulator
Sebopeho sa Directory
Li-directory li na le tse hlahisitsoeng file bakeng sa sebopeho sa HDMI Intel FPGA IP example.
Setšoantšo sa 4. Sebopeho sa Directory bakeng sa Moqapi Example
Phallo ea Tatelano ea Reconfiguration
Setšoantšo sa 5. Phallo ea Tatelano ea Mekhoa e mengata ea Reconfiguration
Palo e bonts'a phallo ea tatellano ea li-reconfiguration tse ngata tsa molaoli ha a amohela phallo ea data e kentsoeng le maqhubu a oache ea litšupiso, kapa ha transceiver e notletsoe.
Lipontšo tsa Interface
Litafole li thathamisa matšoao a HDMI PHY Intel FPGA IP moralo example.
Lethathamo la 3. Lipontšo tsa boemo bo holimo
| Letshwao | Tataiso | Bophara | Tlhaloso |
| Letšoao la Oscillator ka botong | |||
| clk_fpga_b3_p | Kenyeletso | 1 | 100 MHz oache ea mahala e sebetsang bakeng sa oache ea mantlha ea litšupiso |
| refclk_fmcb_p | Kenyeletso | 1 | Oache e tsitsitseng ea litšupiso bakeng sa ho lekanya matla a transceiver. Ke 625 MHz ka ho sa feleng empa e ka ba ea maqhubu afe kapa afe |
| Likonopo tsa Push ea Basebelisi le li-LED | |||
| cpu_resetn | Kenyeletso | 1 | Ho seta bocha lefatšeng ka bophara |
| user_led_g | Sephetho | 2 | Pontšo ea LED e tala |
| HDMI FMC Morali oa Card Pins ho FMC Port B | |||
| fmcb_gbtclk_m2c_p_0 | Kenyeletso | 1 | Oache ea HDMI RX TMDS |
| fmcb_dp_m2c_p | Kenyeletso | 3 | HDMI RX likanale tsa data tse khubelu, tse tala, le tse putsoa
• Phetoho ea karete ea morali ea Bitec 11 — [0]: RX TMDS Channel 1 (Tala) — [1]: RX TMDS Channel 2 (Khubelu) — [2]: RX TMDS Channel 0 (Putsoa) |
| fmcb_dp_c2m_p | Sephetho | 4 | Oache ea HDMI TX, liteishene tsa data tse khubelu, tse tala le tse putsoa
• Phetoho ea karete ea morali ea Bitec 11 — [0]: TX TMDS Channel 2 (Khubelu) — [1]: TX TMDS Channel 1 (Tala) — [2]: TX TMDS Channel 0 (Putsoa) — [3]: TX TMDS Clock Channel |
| fmcb_la_rx_p_9 | Kenyeletso | 1 | Ho lemoha matla a HDMI RX +5V |
| fmcb_la_rx_p_8 | Kenyeletso | 1 | Sesebelisoa sa plug se chesang sa HDMI RX |
| fmcb_la_rx_n_8 | Kenyeletso | 1 | HDMI RX I2C SDA bakeng sa DDC le SCDC |
| fmcb_la_tx_p_10 | Kenyeletso | 1 | HDMI RX I2C SCL bakeng sa DDC le SCDC |
| fmcb_la_tx_p_12 | Kenyeletso | 1 | HDMI TX hot plug detect |
| fmcb_la_tx_n_12 | Kenyeletso | 1 | HDMI I2C SDA bakeng sa DDC le SCDC |
| fmcb_la_rx_p_10 | Kenyeletso | 1 | HDMI I2C SCL bakeng sa DDC le SCDC |
| fmcb_la_tx_p_11 | Kenyeletso | 1 | HDMI I2C SDA bakeng sa taolo ea ho khanna |
| fmcb_la_rx_n_9 | Kenyeletso | 1 | HDMI I2C SCL bakeng sa taolo ea ho khanna |
Sekema sa ho Tlisa
Se latelang ke leano la clocking la HDMI PHY Intel FPGA IP design exampLe:
- clk_fpga_b3_p ke oache e tsitsitseng ea 100 MHz bakeng sa ho tsamaisa processor ea NIOS le mesebetsi ea taolo. Haeba maqhubu a fanoeng a nepahetse, user_led_g[1] oa fetola motsotsoana o mong le o mong.
- refclk_fmcb_p ke oache e tsitsitseng ea litšupiso bakeng sa ho lekanya matla a li-transceivers. Ke 625 MHz ka ho sa feleng empa e ka ba ea maqhubu afe kapa afe.
- fmcb_gbtclk_m2c_p_0 ke oache ea TMDS ea HDMI RX. Oache ena e boetse e sebelisoa ho khanna li-transceivers tsa HDMI TX. Haeba maqhubu a fanoeng e le 148.5 MHz, user_led_g[0] o tla fetola motsotsoana o mong le o mong.
Ho hlophisoa ha Hardware
Moetso oa HDMI PHY Intel FPGA IP exampe na le HDMI 2.0b e nang le bokhoni 'me e etsa pontšo ea loop-through bakeng sa molapo o tloaelehileng oa video oa HDMI.
Ho etsa tlhahlobo ea hardware, hokela sesebelisoa se lumelletsoeng ke HDMI joalo ka karete ea litšoantšo e nang le sebopeho sa HDMI ho sehokelo sa HDMI RX se kareteng ea morali ea Bitec HDMI 2.0, e tsamaisang data ho block ea transceiver RX le HDMI RX.
- Sink ea HDMI e khetholla boema-kepe hore e be molatsoana o tloaelehileng oa video ebe o e romella setsing sa ho khutlisa oache.
- Mokotla oa HDMI RX o khetholla data ea video, e thusang, le ea molumo hore e khutlisetsoe morao ka AXI4-stream interface ho HDMI TX core.
- Boema-kepe ba mohloli oa HDMI oa karete ea morali oa FMC e fetisetsa setšoantšo ho sebali.
- Tobetsa konopo ea cpu_resetn hang ho etsa reset ea sistimi.
Hlokomela: Haeba u batla ho sebelisa boto e 'ngoe ea ntlafatso ea Intel FPGA, u tlameha ho fetola likabelo tsa sesebelisoa le likabelo tsa phini. Setlhophiso sa analog ea transceiver se lekoa bakeng sa lisebelisoa tsa nts'etsopele tsa Intel Arria 10 FPGA le karete ea morali ea Bitec HDMI 2.0. U ka fetola li-setting tsa boto ea hau.
Nalane ea Phetoho ea Tokomane bakeng sa HDMI PHY Intel
FPGA IP Design Example Bukana ea Mosebelisi
| Tokomane Version | Intel Quartus Prime Version | IP Version | Liphetoho |
| 2022.07.20 | 22.2 | 1.0.0 | Tokollo ea pele. |
Litokomane / Lisebelisoa
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Intel HDMI PHY FPGA IP Design Example [pdf] Bukana ea Mosebelisi HDMI PHY FPGA IP Design Example, HDMI PHY, FPGA IP Design Example, HDMI PHY IP Design Example, FPGA IP Design Example, IP Design Example, 732781 |
