Intel HDMI PHY FPGA IP Design Example Umhlahlandlela Womsebenzisi

I-HDMI PHY Design Example Quick Start Guide yamadivayisi e-Intel® Arria® 10

I-HDMI PHY Intel® FPGA IP design exampI-le yamadivayisi we-Intel Arria® 10 ihlanganisa idizayini yokudlulisa kabusha i-HDMI 2.0 RX-TX esekela ukuhlanganiswa nokuhlolwa kwehadiwe.
Uma udala i-ex designample, umhleli wepharamitha udala ngokuzenzakalelayo i filekudingekile ukulingisa, ukuhlanganisa, nokuhlola idizayini kuhadiwe.

Umfanekiso 1. Izinyathelo Zokuthuthukiswa

Ulwazi Oluhlobene
I-HDMI PHY Intel FPGA IP User Guide

Ikhiqiza Umklamo

Sebenzisa isihleli sepharamitha ye-HDMI PHY Intel FPGA IP kusofthiwe ye-Intel Quartus® Prime ukuze ukhiqize i-ex yokuklamaampLes.

Umfanekiso 2. Ukukhiqiza Ukugeleza Komklamo

1. Dala iphrojekthi eqondise umndeni wedivayisi ye-Intel Arria 10 bese ukhetha idivayisi oyifunayo.
2. Kukhathalogi ye-IP, thola futhi uchofoze kabili I-Interface Protocols ➤ Umsindo Nevidiyo ➤ HDMI TX PHY Intel FPGA IP (noma i-HDMI RX PHY Intel FPGA IP). Iwindi elisha le-IP Variant noma iwindi elisha lokushintshashintsha kwe-IP liyavela.
3. Cacisa igama lezinga eliphezulu lokuhluka kwakho kwe-IP yangokwezifiso. Umhleli wepharamitha ugcina izilungiselelo zokuhlukahluka kwe-IP ku-a file okuthiwa .ip noma .qsys.
4. Chofoza okuthi KULUNGILE. Umhleli wepharamitha uyavela.
   Inkampani ye-Intel Wonke Amalungelo Agodliwe. I-Intel, ilogo ye-Intel, nezinye izimpawu ze-Intel yizimpawu zokuthengisa ze-Intel
   Inkampani noma izinkampani ezingaphansi kwayo. I-Intel iqinisekisa ukusebenza kwe-FPGA yayo kanye nemikhiqizo yesemiconductor ekucacisweni kwamanje ngokuvumelana newaranti evamile ye-Intel, kodwa igodla ilungelo lokwenza izinguquko kunoma imiphi imikhiqizo namasevisi nganoma yisiphi isikhathi ngaphandle kwesaziso. I-Intel ayithathi mthwalo noma isikweletu esivele ngenxa yesicelo noma ukusetshenziswa kwanoma yiluphi ulwazi, umkhiqizo, noma isevisi echazwe lapha ngaphandle kwalapho okuvunyelwene ngakho ngokubhaliwe yi-Intel. Amakhasimende e-Intel ayelulekwa ukuthi athole inguqulo yakamuva yokucaciswa kwedivayisi ngaphambi kokuthembela kunoma yiluphi ulwazi olushicilelwe nangaphambi kokufaka ama-oda emikhiqizo noma amasevisi.
   Amanye amagama namabhrendi angafunwa njengempahla yabanye.
5. Ku-Design Exampkuthebhu, khetha i-Arria 10 HDMI RX-TX Retransmit.
6. Khetha Ukulingisa ukuze ukhiqize ibhentshi lokuhlola, bese ukhetha i-Synthesis ukuze ukhiqize i-ex ye-hardware designample.
   Kufanele ukhethe okungenani eyodwa yalezi zinketho ukuze ukhiqize i-ex yokuklamaample files.
   Uma ukhetha kokubili, isikhathi sokukhiqiza siba side.
7. Okokukhiqiza File Fometha, khetha i-Verilog noma i-VHDL.
8. Ngekhithi Yokuthuthukiswa Kwethagethi, khetha i-Intel Arria 10 GX FPGA Development
   Ikhithi. Uma ukhetha ikhithi yokuthuthukisa, idivayisi eqondiwe iyashintsha ukuze ifane nedivayisi esebhodini eliqondiwe. Nge-Intel Arria 10 GX FPGA Development Kit, idivayisi ezenzakalelayo yi-10AX115S2F4I1SG.
9. Chofoza okuthi Khiqiza Isibample Design.

Ukuhlanganisa Nokuhlola Idizayini

Ukuhlanganisa nokusebenzisa ukuhlolwa kokubonisa ku-hardware example design, landela lezi zinyathelo:

1. Qinisekisa i-hardware exampi-design generation iqedile.
2. Yethula isoftware ye-Intel Quartus Prime bese uvula ifayela le- .qpf file: /quartus/a10_hdmi2_demo.qpf
3. Chofoza Ukucubungula ➤ Qala Ukuhlanganisa.
4. Ngemva kokuhlanganiswa ngempumelelo, i-.sof file kukhiqizwa ku-quartus/ okukhiphayo_files lwemibhalo.
5. Xhuma i-Bitec HDMI 2.0 FMC Ikhadi Lendodakazi Rev 11 embotsheni ye-FMC engaphakathi kwebhodi B (J2).
6. Xhuma i-TX (P1) yekhadi lendodakazi le-Bitec FMC emthonjeni wamavidiyo wangaphandle.
7. Xhuma i-RX (P2) yekhadi lendodakazi le-Bitec FMC kusinki wangaphandle wevidiyo noma isihlaziyi sevidiyo.
8. Qinisekisa ukuthi wonke amaswishi ebhodini lokuthuthukisa asesimweni sokuzenzakalelayo.
9. Lungiselela idivayisi ye-Intel Arria 10 ekhethiwe ebhodini lokuthuthukisa usebenzisa i-.sof ekhiqiziwe file (Amathuluzi ➤ Umklami).
10. Umhlaziyi kufanele abonise ividiyo ekhiqizwe emthonjeni. Ukuhlanganisa Nokuhlola Idizayini

Ulwazi Oluhlobene
I-Intel Arria 10 FPGA Development Kit User Guide

I-HDMI PHY Intel FPGA IP Design Example Amapharamitha

Ithebula 1. HDMI PHY Intel FPGA IP Design Example Amapharamitha we-Intel Arria 10
Amadivayisi

Lezi zinketho zitholakala kumadivayisi we-Intel Arria 10 kuphela.

Ipharamitha	Inani	Incazelo
Idizayini Etholakalayo Example
Khetha i-Design	I-Arria 10 HDMI RX-TX Retransmit	Khetha i-ex designample ezokwenziwa.

I-Design Example Files
Ukulingisa	Khanyisa cisha	Vula le nketho ukuze ukhiqize okudingekayo files okwebhentshi lokulinganisa lokulingisa.
I-synthesis	Khanyisa cisha	Vula le nketho ukuze ukhiqize okudingekayo files yokuhlanganiswa kwe-Intel Quartus Prime kanye nokuboniswa kwehadiwe.

Kwenziwe Ifomethi ye-HDL
Khiqiza File Ifomethi	I-Verilog, i-VHDL	Khetha ifomethi oyithandayo ye-HDL ye-ex yedizayini ekhiqiziweample filesetha. Qaphela: Le nketho inquma kuphela ifomethi yeleveli ephezulu ye-IP ekhiqiziwe files. Konke okunye files (isbample testbenches kanye nezinga eliphezulu files yokuboniswa kwezingxenyekazi zekhompyutha) zikufomethi ye-Verilog HDL.

Ikhithi Yokuthuthukisa Okuqondisiwe
Khetha Ibhodi	Ayikho Ikhithi Yokuthuthukisa,	Khetha ibhodi ye-ex yedizayini eqondisiweample.
	I-Arria 10 GX FPGA Development Kit, Ikhithi Yokuthuthukisa Ngokwezifiso	Ayikho Ikhithi Yokuthuthukisa: Le nketho ayifaki zonke izici zehadiwe ye-ex yedizayiniample. I-IP core isetha yonke imisebenzi yephinikhodi kumaphinikhodi abonakalayo. I-Arria 10 GX FPGA Development Kit: Le nketho ikhetha ngokuzenzakalelayo idivayisi eqondiwe yephrojekthi ukuze ifane nedivayisi ekule khithi yokuthuthukisa. Ungashintsha idivayisi eqondiwe usebenzisa i Shintsha Idivayisi Eqondisiwe ipharamitha uma ukubuyekezwa kwebhodi lakho kunokwehlukile kwedivayisi. I-IP core isetha yonke imisebenzi yephinikhodi ngokuya ngekhithi yokuthuthukisa.
		Ikhithi Yokuthuthukisa Ngokwezifiso: Le nketho ivumela i-ex yedizayiniample izohlolwa kukhithi yokuthuthukisa yenkampani yangaphandle nge-Intel FPGA. Ungase udinge ukusetha imisebenzi yephinikhodi uwedwa.

Idivayisi eqondiwe
Shintsha Idivayisi Eqondisiwe	Khanyisa cisha	Vula le nketho bese ukhetha ukwahluka kwedivayisi okuncamelayo kwekhithi yokuthuthukisa.

I-HDMI 2.0 PHY Design Example

I-HDMI PHY Intel FPGA IP design exampI-le ibonisa i-loopback eyodwa ye-HDMI ehambisanayo ehlanganisa iziteshi ezintathu ze-RX neziteshi ezine ze-TX, ezisebenza ngamanani edatha afika ku-6 Gbps.

Idizayini ekhiqiziwe ye-HDMI PHY Intel FPGA IP exampi-le iyafana ne-design exampikhiqizwa ku-HDMI Intel FPGA IP core. Nokho, lo mklamo exampu-le usebenzisa i-TX PHY, RX PHY, ne-PHY arbiter entsha esikhundleni se-RTL yangokwezifiso ku-HDMI Intel FPGA IP core design ex.ample.

Umfanekiso 3. HDMI 2.0 PHY Design Example

Imojuli	Incazelo
I-RX PHY	I-RX PHY ibuyisela idatha ye-HDMI yochungechunge futhi ithumele lokhu kumongo we-HDMI RX ngefomethi efanayo ezizindeni zewashi ezitholiwe (rx_clk[2:0]). Idatha iqoshwe kuvidiyo

Imojuli	Incazelo
	idatha ezokhishwa ngevidiyo yokusakaza ye-AXI4. I-RX PHY iphinde ithumele amasiginali e-vid_clk kanye ne-ls_clk kumongo we-HDMI RX ngesixhumi esibonakalayo se-PHY.
I-HDMI TX Core	I-HDMI TX core ithola idatha yevidiyo esakazwa yi-AXI4 futhi ibhala lokhu kudatha ehambisanayo yefomethi ye-HDMI. I-HDMI TX core ithumela le datha ku-TX PHY.
I-HDMI RX Core	I-IP ithola idatha ye-serial evela ku-RX PHY futhi yenza ukuqondanisa kwedatha, i-channel deskew, ukuqoshwa kwe-TMDS, ukuqoshwa kwedatha eyinsiza, ukuqoshwa kwedatha yevidiyo, ukuqoshwa kwedatha yomsindo, nokuhlehlisa.
TX PHY	Ithola futhi ihlele idatha ehambisanayo evela kumongo we-HDMI TX kanye nokuphumayo kokusakaza kwe-HDMI TMDS. I-TX PHY ikhiqiza i-tx_clk ye-HDMI TX core. I-TX PHY iphinda ikhiqize i-vid_clk ne-ls_clk futhi ithumele lawa masignali kumongo we-HDMI TX ngesixhumi esibonakalayo se-PHY.
I-IOPLL	Ikhiqiza iwashi lokusakaza elingu-300 MHz AXI le-AXI4- isixhumi esibonakalayo sokusakaza.
I-I2C Master	Ukuze ulungiselele izingxenye ezihlukahlukene ze-PCB.

Izingxenyekazi zekhompuyutha nezidingo zeSoftware

I-Intel isebenzisa izingxenyekazi zekhompuyutha ezilandelayo nesofthiwe ukuhlola i-ex yedizayiniample.

Izingxenyekazi zekhompuyutha

• I-Intel Arria 10 GX FPGA Development Kit
• Umthombo we-HDMI (Iyunithi Yephrosesa Yezithombe (GPU)
• I-HDMI Sink (Monitor)
• Ikhadi lendodakazi le-Bitec HDMI FMC 2.0 (Isibuyekezo 11)
• Izintambo ze-HDMI

Isofthiwe

• I-Intel Quartus Prime Pro Edition (yokuhlola ihadiwe)
• I-ModelSim* – Intel FPGA Edition, ModelSim – Intel FPGA Starter Edition, NCSim,
  I-Riviera-PRO*, i-VCS* (i-Verilog HDL kuphela)/VCS MX, noma i-Xcelium* i-Parallel simulator

Ukwakheka Kwemibhalo

Izikhombisi ziqukethe okukhiqiziwe file ye-HDMI Intel FPGA IP design example.

Umfanekiso 4. Ukwakheka Kwemibhalo Yomklamo Example

Ukugeleza Kokulandelana Kokuhlela Kabusha

Umfanekiso 5. Ukugeleza Kokulandelana Kokuhlela Kabusha kwamazinga amaningi 

Isibalo sibonisa ukugeleza kokulandelana kokuhlelwa kabusha kwezilinganiso eziningi kwesilawuli lapho sithola ukusakaza kwedatha yokokufaka kanye nemvamisa yewashi lesithenjwa, noma uma i-transceiver ivuliwe.

Izimpawu Zokuxhumana

Amathebula aklelisa amasiginali we-HDMI PHY Intel FPGA IP design example.

Ithebula 3. Izimpawu Zezinga eliphezulu

Isiginali	Isiqondiso	Ububanzi	Incazelo
Isiginali ye-Oscillator esebhodini
clk_fpga_b3_p	Okokufaka	1	100 MHz iwashi eligijima lamahhala lewashi eliyinkomba eliyinhloko
refclk_fmcb_p	Okokufaka	1	Iwashi lereferensi yesilinganiso esingaguquki sokulinganisa amandla e-transceiver. Ingu-625 MHz ngokuzenzakalelayo kodwa ingaba yanoma iyiphi imvamisa

Izinkinobho Zokusunduza Zomsebenzisi nama-LED
cpu_resetn	Okokufaka	1	Ukusetha kabusha umhlaba
umsebenzisi_led_g	Okukhiphayo	2	Isibonisi se-LED eluhlaza

Izikhonkwane zekhadi lendodakazi le-HDMI le-FMC ku-FMC Port B
fmcb_gbtclk_m2c_p_0	Okokufaka	1	Iwashi le-HDMI RX TMDS
fmcb_dp_m2c_p	Okokufaka	3	Iziteshi zedatha ze-HDMI RX ezibomvu, eziluhlaza, neziluhlaza okwesibhakabhaka • Ukubuyekezwa kwekhadi lendodakazi ye-Bitec 11 — [0]: Isiteshi 1 se-RX TMDS (Siluhlaza) — [1]: Isiteshi 2 se-RX TMDS (Bomvu) — [2]: RX TMDS Channel 0 (Blue)
fmcb_dp_c2m_p	Okukhiphayo	4	Iwashi le-HDMI TX, amashaneli edatha abomvu, aluhlaza, naluhlaza okwesibhakabhaka • Ukubuyekezwa kwekhadi lendodakazi ye-Bitec 11 — [0]: Isiteshi 2 se-TX TMDS (Bomvu) — [1]: Isiteshi 1 se-TX TMDS (Siluhlaza) — [2]: TX TMDS Channel 0 (Blue) — [3]: Isiteshi sewashi se-TX TMDS
fmcb_la_rx_p_9	Okokufaka	1	Ukutholwa kwamandla kwe-HDMI RX +5V
fmcb_la_rx_p_8	Okokufaka	1	Ukutholwa kwepulagi eshisayo ye-HDMI RX
fmcb_la_rx_n_8	Okokufaka	1	I-HDMI RX I2C SDA ye-DDC ne-SCDC
fmcb_la_tx_p_10	Okokufaka	1	I-HDMI RX I2C SCL ye-DDC ne-SCDC
fmcb_la_tx_p_12	Okokufaka	1	Ukutholwa kwepulaki eshisayo ye-HDMI TX
fmcb_la_tx_n_12	Okokufaka	1	I-HDMI I2C SDA ye-DDC ne-SCDC
fmcb_la_rx_p_10	Okokufaka	1	I-HDMI I2C SCL ye-DDC ne-SCDC
fmcb_la_tx_p_11	Okokufaka	1	I-HDMI I2C SDA yokulawula umshayeli kabusha
fmcb_la_rx_n_9	Okokufaka	1	I-HDMI I2C SCL yokulawula umshayeli kabusha

Uhlelo Lokuvala

Okulandelayo uhlelo lwewashi lomklamo we-HDMI PHY Intel FPGA IP example:

• clk_fpga_b3_p iwashi lezinga eligxilile elingu-100 MHz lokuqhuba iphrosesa ye-NIOS nemisebenzi yokulawula. Uma i-frequency enikeziwe ilungile, umsebenzisi_led_g[1] uyashintsha isekhondi ngalinye.
• I-refclk_fmcb_p iwashi lereferensi lenani eligxilile lokulinganisa amandla ama-transceivers. Ingu-625 MHz ngokuzenzakalelayo kodwa ingaba yanoma iyiphi imvamisa.
• I-fmcb_gbtclk_m2c_p_0 iwashi le-TMDS le-HDMI RX. Leli washi lisetshenziselwa ukushayela ama-transceivers e-HDMI TX. Uma imvamisa enikeziwe ingu-148.5 MHz, umsebenzisi_led_g[0] uyashintsha isekhondi ngalinye.

Ukusethwa kwe-Hardware

I-HDMI PHY Intel FPGA IP design exampI-le iyakwazi i-HDMI 2.0b futhi yenza umboniso we-loop-through wokusakaza okujwayelekile kwevidiyo ye-HDMI.

Ukuze uqalise ukuhlolwa kwezingxenyekazi zekhompuyutha, xhuma idivayisi enikwe amandla i-HDMI njengekhadi lemifanekiso eline-HDMI isixhumi esixhumi se-HDMI RX ekhadini lendodakazi le-Bitec HDMI 2.0, elihambisa idatha kubhulokhi ye-transceiver RX kanye ne-HDMI RX.

1. Usinki we-HDMI uhlukanisa imbobo ibe ukusakaza kwevidiyo okuvamile futhi uyithumele kumongo wokutakula wewashi.
2. I-HDMI RX core inquma ividiyo, isilekeleli, nedatha yomsindo ezobuyiselwa emuva ngesixhumi esibonakalayo se-AXI4-stream ukuya kumongo we-HDMI TX.
3. Imbobo yomthombo ye-HDMI yekhadi lendodakazi ye-FMC idlulisela isithombe kusiqaphi.
4. Cindezela inkinobho ye-cpu_resetn kanye ukuze wenze ukusetha kabusha isistimu.
   Qaphela: Uma ufuna ukusebenzisa elinye ibhodi lokuthuthukisa i-Intel FPGA, kufanele uguqule imisebenzi ezonikezwa idivayisi kanye nezabelo zamaphinikhodi. Isilungiselelo se-analog ye-transceiver sihlolelwa ikhithi yokuthuthukisa ye-Intel Arria 10 FPGA kanye nekhadi lendodakazi le-Bitec HDMI 2.0. Ungashintsha izilungiselelo zebhodi lakho.

Umlando Wokubuyekezwa Kwedokhumenti we-HDMI PHY Intel
I-FPGA IP Design Example Umhlahlandlela Womsebenzisi

Inguqulo Yedokhumenti	Inguqulo ye-Intel Quartus Prime	Inguqulo ye-IP	Izinguquko
2022.07.20	22.2	1.0.0	Ukukhishwa kokuqala.

Amadokhumenti / Izinsiza

Intel HDMI PHY FPGA IP Design Example [pdf] Umhlahlandlela Womsebenzisi I-HDMI PHY FPGA IP Design Example, HDMI PHY, FPGA IP Design Example, HDMI PHY IP Design Example, FPGA IP Design Example, IP Design Exampibe, 732781

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