FPGA IP
Imepụta Example ntuziaka onye ọrụ
F-Tile 25G Ethernet Intel®
Emelitere maka Intel® Quartus®
Prime Design Suite: 22.3
Ụdị IP: 1.0.0

Ntuziaka mmalite ngwa ngwa

F-tile 25G Ethernet Intel FPGA IP maka ngwaọrụ Intel Agilex ™ na-enye ikike nke imepụta ihe nrụpụta.amples maka nhazi ahọpụtara.
Ọgụgụ 1. Imepụta Example ojiji

Ọdịdị ndekọ

Ọgụgụ 2. 25G Ethernet Intel FPGA IP Design Exampn'akwụkwọ ndekọ aha Structure

• The ịme anwansị files (testbench maka ịme anwansị naanị) dị naample_dir>/ example_testbench.
• Ihe nchikota-naanị imewe example dị naample_dir>/ compilation_test_design.
• Nhazi ngwaike na ule files (ichepụta example in hardware) dị naample_dir>/hardware_test_design.

Isiokwu 1. Akwụkwọ ndekọ na File Nkọwa

File Aha	Nkọwa
eth_ex_25g.qpf	Intel Quartus® Prime oru ngo file.
eth_ex_25g.qsf	Ntọala ọrụ Intel Quartus Prime file.
eth_ex_25g.sdc	Synopsys imewe mmachi file. Ị nwere ike idetuo ma gbanwee nke a file maka imewe 25GbE Intel FPGA IP nke gị.
eth_ex_25g.v	Verilog HDL imewe nke kachasị eluample file. Nhazi otu ọwa na-eji Verilog file.
nkịtị/	Nhazi ngwaike example nkwado files.
hwtest/main.tcl	Isi file maka ịnweta Sistemu Console.

Na-emepụta ihe osise Example

Onyonyo 4. Exampma chepụta Tab na F-tile 25G Ethernet Intel FPGA IP Parameter Editor

Soro usoro ndị a ka ịmepụta ngwaike imewe example na testbench:

1. Na Intel Quartus Prime Pro Edition, pịa File ➤ Ọkachamara Project ọhụrụ iji mepụta ọrụ Quartus Prime ọhụrụ, ma ọ bụ File ➤ Mepee Project ka imepe ọrụ Quartus Prime dị. Ọkachamara na-akpali gị ezipụta ngwaọrụ.
2. Na katalọgụ IP, chọta ma họrọ 25G Ethernet Intel FPGA IP maka Agilex. Window mgbanwe IP ọhụrụ na-egosi.
3. Ezipụta aha ọkwa dị elu maka ụdị IP gị wee pịa OK. Onye ndezi paramita na-agbakwụnye .ip file na oru ngo nke ugbu a na-akpaghị aka. Ọ bụrụ na a kpaliri gị iji aka tinye .ip file na oru ngo, pịa Project ➤ Tinye / Wepụ Files na Project ịgbakwunye ihe file.
4. N'ime sọftụwia Intel Quartus Prime Pro Edition, ị ga-ahọrọ ngwaọrụ Intel Agilex akọwapụtara na mpaghara ngwaọrụ, ma ọ bụ debe ngwaọrụ ndabara nke sọftụwia Quartus Prime tụpụtara.
   Mara: Nhazi ngwaike example overwrites nhọrọ na ngwaọrụ na iche osisi. Ị na-akọwapụta bọọdụ ebumnuche site na menu nke imewe exampnhọrọ na Example Design tab.
5. Pịa OK. Ihe ndezi paramita na-egosi.
6. Na taabụ IP, ezipụta paramita maka mgbanwe isi IP gị.
7. Na Example Kere tab, maka Example Design Files, họrọ nhọrọ Simulation iji mepụta testbench, wee họrọ nhọrọ Synthesis iji mepụta ngwaike imewe ex.ample. Naanị Verilog HDL files na-emepụta.
   Mara: Isi VHDL IP na-arụ ọrụ adịghị. Ezipụta Verilog HDL naanị, maka nhazi IP isi gị example.
8. Maka ngwa mmepe Target, họrọ Agilex I-usoro Transceiver-SoC Dev Kit
9. Pịa n'ịwa Example Design bọtịnụ. Họrọ Example Imepụta windo ndekọ na-egosi.
10. Ọ bụrụ na-ịchọrọ ị gbanwee imewe exampụzọ ndekọ aha ma ọ bụ aha sitere na ndabara egosiri (alt_e25_f_0_example_design), chọgharịa n'ụzọ ọhụrụ wee pịnye ihe ọhụrụ ahụ exampaha ndekọ aha (ample_dir>).
11. Pịa OK.

1.2.1. Imepụta Example Parameters
Tebụl 2. Parameters na Example Design Tab

Oke	Nkọwa
Example Design	Ọ dị example designs maka IP paramita ntọala. Naanị otu ọwa exampakwadoro imewe maka IP a.
Example Design Files	Nke files iji mepụta maka usoro mmepe dị iche iche. • Simulation — na-emepụta ihe dị mkpa files maka simulating exampimewe. • Synthesis-na-emepụta njikọ files. Jiri ihe ndị a files iji chịkọta imewe ahụ na sọftụwia Intel Quartus Prime Pro maka nnwale ngwaike yana nyocha oge kwụ ọtọ.
Mepụta File Usoro	Ụdị nke RTL files maka ịme anwansị — Verilog.
Họrọ bọọdụ	Ngwaike akwadoro maka mmejuputa nhazi. Mgbe ịhọrọ bọọdụ mmepe Intel FPGA, jiri ngwaọrụ AGIB027R31B1E2VRO dị ka ngwaọrụ ebumnuche maka imewe ex.ample ọgbọ. Agilex I-usoro Transceiver-SoC Dev Kit: Nhọrọ a na-enye gị ohere ịnwale imewe bụbuample na ngwa mmepe Intel FPGA IP ahọpụtara. Nhọrọ a na-ahọpụta ngwa ngwa Target nke AGIB027R31B1E2VRO. Ọ bụrụ na gị osisi revision nwere dị iche iche ngwaọrụ ọkwa, ị nwere ike ịgbanwe lekwasịrị ngwaọrụ. Ọ dịghị: Nhọrọ a na-ewepu akụkụ ngwaike maka imewe example.

1.3. Na-emepụta Tile Files

Ọgbọ Nkwado-Logic bụ usoro nrụpụta tupu eji emepụta tile metụtara files chọrọ maka ịme anwansị na ngwaike imewe. A chọrọ ọgbọ tile maka mmadụ niile
F-tile dabere imewe simulations. Ị ga-emecha nzọụkwụ a tupu ịme anwansị.

1. Mgbe iwu ozugbo, gaa na folda compilation_test_design dị na mbụ gịample imewe: cd /nchịkọta_test_design.
2. Gbaa iwu a: quartus_tlg alt_eth_25g

1.4. Ịmepụta F-tile 25G Ethernet Intel FPGA IP Design 
Exampna Testbench
Ị nwere ike chịkọta ma megharịa atụmatụ ahụ site na ịmegharị edemede simulation site na ngwa ngwa.

1. Na iwu ozugbo, gbanwee testbench simulating na-arụ ọrụ ndekọ: cdample_dir>/ex_25g/sim.
2. Gbaa simulation IP ntọala:ip-setup-simulation -quartusproject=../../compilation_test_design/alt_eth_25g.qpf

Tebụl 3. Nzọụkwụ iji mee ka Testbench

Simulator	Ntuziaka
VCS*	N'ahịrị iwu, pịnye sh run_vcs.sh
QuestaSim*	N'ahịrị iwu, pịnye vsim -do run_vsim.do -logfile vsim.log Ọ bụrụ na ịchọrọ ịme simulate na-ebuliteghị QuestaSim GUI, pịnye vsim -c -do run_vsim.do -logfile vsim.log
Cadence -Xcelium*	N'ahịrị iwu, pịnye sh run_xcelium.sh

Simulation na-aga nke ọma na-ejedebe na ozi a:
Agafela ịme anwansị. ma ọ bụ Testbench zuru ezu.
Mgbe emechara nke ọma, ị nwere ike nyochaa nsonaazụ ya.
1.5. Ịchịkọta na Hazie Nhazi Exampna Hardware
25G Ethernet Intel FPGA IP core parameter editọ na-enye gị ohere ịchịkọta na hazie imewe ex.ample na ngwa mmepe ebumnuche.

Iji chịkọta na hazie imewe exampna hardware, soro usoro ndị a:

1. Mepee sọftụwia Intel Quartus Prime Pro Edition wee họrọ Nhazi ➤ Malite Nchịkọta iji chịkọta nhazi ahụ.
2. Mgbe ịmepụtara ihe SRAM file .sof, soro usoro ndị a iji hazie ngwaike imewe exampna ngwaọrụ Intel Agilex:
   a. Na Ngwaọrụ menu, pịa Programmer.
   b. Na Programmer, pịa Hardware Mbido.
   c. Họrọ ngwaọrụ mmemme.
   d. Họrọ ma tinye bọọdụ Intel Agilex na nnọkọ Intel Quartus Prime Pro Edition gị.
   e. Gbaa mbọ hụ na edobere ọnọdụ na JTAG.
   f. Họrọ ngwaọrụ Intel Agilex wee pịa Tinye Ngwaọrụ. Onye mmemme gosipụtara
   eserese ngọngọ nke njikọ dị n'etiti ngwaọrụ dị na bọọdụ gị.
   g. N'ahịrị na .sof gị, lelee igbe maka .sof.
   h. Lelee igbe dị na kọlụm Mmemme/Hazie.
   i. Pịa Malite.

1.6. Na-anwale F-tile 25G Ethernet Intel FPGA IP Hardware Design Example
Mgbe ị chịkọtara F-tile 25G Ethernet Intel FPGA IP core design exampma hazie ya na ngwaọrụ Intel Agilex gị, ị nwere ike iji njikwa sistemụ iji hazie isi IP.
Ka ịgbanwuo Console Sistemu wee nwalee nhazi ngwaike example, soro usoro ndị a:

1. Na ngwanrọ Intel Quartus Prime Pro Edition, họrọ Ngwaọrụ ➤ Sistemu
   Ngwa nbipu ➤ Sistemụ njikwa iji malite njikwa sistemụ.
2. Na pane Tcl Console, pịnye cd hwtest iji gbanwee ndekọ ka ọ bụrụ / hardware_test_design/hwtest.
3. Pịnye isi iyi main.tcl ka imepe njikọ na JTAG nna ukwu.

Soro usoro ule na ngalaba Nleba ngwaike nke imewe example wee hụ rịzọlt ule na Sistemụ Console.

F-tile 25G Ethernet Design Exampmaka ngwaọrụ Intel Agilex

F-tile 25G Ethernet imewe example gosipụtara ngwọta Ethernet maka ngwaọrụ Intel Agilex na-eji 25G Ethernet Intel FPGA IP isi.
Mepụta imewe example site na ExampLe Design tab nke 25G Ethernet Intel FPGA IP parameter nchịkọta akụkọ. Ị nwekwara ike ịhọrọ ịmepụta imewe ya na ma ọ bụ na-enweghị
njirimara Reed-Solomon Forward Error Correction (RS-FEC).
2.1. Atụmatụ

• Na-akwado otu ọwa Ethernet na-arụ ọrụ na 25G.
• Na-emepụta imewe example na njirimara RS-FEC.
• Na-enye testbench na script simulation.
• Na-ewepụta ntụaka F-Tile ozugbo na sistemụ PLL na-emechi Intel FPGA IP dabere na nhazi IP.

2.2. Achọrọ ngwaike na ngwanrọ
Intel na-eji ngwaike na ngwanrọ ndị a iji nwalee imewe exampn'ime sistemụ Linux:

• Intel Quartus Prime Pro Edition software.
• Siemens* EDA QuestaSim, Synopsys* VCS, na Cadence Xcelium simulator.
• Intel Agilex I-usoro Transceiver-SoC Development Kit (AGIB027R31B1E2VRO) maka nnwale ngwaike.

2.3. Nkọwa ọrụ
F-tile 25G Ethernet imewe example mejupụtara MAC+ PCS+PMA isi variant. Eserese ngọngọ ndị a na-egosi akụrụngwa imewe yana akara ọkwa dị elu nke Mac+ PCS+PMA variant dị na F-tile 25G Ethernet design ex.ample.
Onyonyo 5. Eserese ngọngọ—F-tile 25G Ethernet Design Example (MAC+PCS+PMA Core Variant)

2.3.1. Ngwa imewe
Tebụl 4. Ngwa imewe

Akụkụ	Nkọwa
F-tile 25G Ethernet Intel FPGA IP	Ihe mejupụtara MAC, PCS, na Transceiver PHY, yana nhazi ndị a: • Core VariantIhe: MAC+PCS+PMA • Kwado njikwa ọsọ: Nhọrọ • Kwado ọgbọ mmejọ njikọ: Nhọrọ • Kwado mmalite passthrough: Nhọrọ • Kwado nchịkọta ọnụ ọgụgụ: Nhọrọ • Kwado ọnụọgụgụ ọnụ ọgụgụ MAC: Nhọrọ • Ugboro elekere ntụaka: 156.25 Maka imewe exampN'iji njirimara RS-FEC, a na-ahazi ihe mgbakwunye ndị a: • Kwado RS-FEC: Nhọrọ
Ntuziaka F-Tile na Sistemu PLL na-emechi Intel FPGA IP	Ntuziaka F-Tile na Sistemu PLL na-emechi ntọala nchịkọta akụkọ paramita Intel FPGA IP kwekọrọ n'ihe achọrọ nke F-tile 25G Ethernet Intel FPGA IP. Ọ bụrụ na ị mepụta imewe example iji Mepụta Example Design bọtịnụ dị na nchịkọta akụkọ paramita IP, IP na-apụta ozugbo. Ọ bụrụ na ị mepụtara onwe gị imewe exampYa mere, ị ga-eji aka tinye IP a ozugbo wee jikọọ ọdụ ụgbọ mmiri I/O niile. Maka ozi gbasara IP a, rụtụ aka F-Tile Architecture na PMA na FEC Direct PHY IP ntuziaka onye ọrụ.
Echiche ndị ahịa	Ihe mejupụtara: • Onye na-emepụta okporo ụzọ, nke na-emepụta ngwugwu gbawara agbawa na 25G Ethernet Intel FPGA IP core maka nnyefe. • Nyochaa okporo ụzọ, nke na-enyocha ngwugwu gbawara agbawa na-abịa site na 25G Ethernet Intel FPGA IP core.
Isi mmalite na Nyocha	Isi mmalite na mgbama nyocha, gụnyere mgbama ntinye nrụpụta sistemụ, nke ị nwere ike iji maka nbipu.

Ozi metụtara
F-Tile Architecture na PMA na FEC Direct PHY IP ntuziaka onye ọrụ

ịme anwansị

The testbench na-eziga okporo ụzọ site na IP isi, na-emega ahụ n'akụkụ na-enweta akụkụ nke IP isi.
2.4.1. Testbench
Ọgụgụ 6. Mgbochi eserese nke F-tile 25G Ethernet Intel FPGA IP Design Example Simulation Testbench

Tebụl 5. Ngwa Testbench

Akụkụ	Nkọwa
Ngwaọrụ n'okpuru ule (DUT)	25G Ethernet Intel FPGA IP isi.
Ihe ngwugwu Ethernet na ihe nleba anya	• Onye na-emepụta ngwugwu na-ewepụta okpokolo agba ma bufee na DUT. • Packet Monitor na-enyocha okporo ụzọ data TX na RX ma gosipụta okpokolo agba na njikwa simulator.
Ntuziaka F-Tile na Sistemu PLL na-emechi Intel FPGA IP	Na-emepụta transceiver na sistemu elekere PLL.

2.4.2. Imepụta ihe ngosi Exampna akụrụngwa
Tebụl 6. F-tile 25G Ethernet Design Exampna Testbench File Nkọwa

File Aha	Nkọwa
Testbench na Simulation Files
basic_avl_tb_top.v	testbench dị elu file. Testbench na-ewepụta DUT, na-arụ nhazi nke ebe nchekwa Avalon® na akụrụngwa imewe yana mgbagha ndị ahịa, na-eziga ma nata ngwugwu gaa ma ọ bụ site na 25G Ethernet Intel FPGA IP.
Ederede Testbench
gara n'ihu…

File Aha	Nkọwa
run_vsim.do	Ederede ModelSim ka ọ na-agba testbench.
ọsọ_vcs.sh	Edemede Synopsys VCS iji mee testbench.
run_xcelium.sh	Edemede Cadence Xcelium iji mee testbench.

2.4.3. Nyocha ikpe
Ikpe ule simulation na-eme omume ndị a:

1. Na-ebute F-tile 25G Ethernet Intel FPGA IP na F-Tile Reference na Sistemu PLL na-emechi Intel FPGA IP.
2. Na-eche elekere RX na akara ọkwa PHY ka ọ dozie.
3. Na-ebipụta ọkwa PHY.
4. Na-eziga ma nata data iri bara uru.
5. Na-enyocha nsonaazụ ya. Testbench na-aga nke ọma na-egosiputa "Testbench zuru ezu."

Ndị na-esonụ sample mmepụta na-egosi ọsọ ule simulation na-aga nke ọma:

Nchịkọta

Soro usoro na Ịchịkọta na Ịhazi Nhazi Example na Hardware iji chịkọta na hazie imewe example na ngwaike ahọpụtara.
Ị nwere ike ịkọpụta ojiji akụrụngwa yana Fmax site na iji nchịkọta naanị ihe bụbuample. Ị nwere ike chịkọta nhazi gị site na iji iwu mmalite nchịkọta na
Nhazi menu na ngwa Intel Quartus Prime Pro Edition. Nchịkọta na-aga nke ọma na-ebute nchịkọta akụkọ mkpokọta.
Maka ozi ndị ọzọ, rụtụ aka na Nhazi Nhazi na ntuziaka onye ọrụ Intel Quartus Prime Pro Edition.
Ozi metụtara

• Ịchịkọta na Hazie Nhazi Example na Hardware na ibe 7
• Nchikota imewe na ntuziaka onye ọrụ Intel Quartus Prime Pro Edition

2.6. Nnwale ngwaike
Na ngwaike imewe exampYa mere, ị nwere ike mmemme nke IP isi na esịtidem serial loopback mode na n'ịwa okporo ụzọ na-ebufe n'akụkụ na loops azụ site na-anata n'akụkụ.
Soro usoro na njikọ ozi metụtara enyere iji nwalee imewe example na ngwaike ahọpụtara.
Ozi metụtara
Na-anwale F-tile 25G Ethernet Intel FPGA IP Hardware Design Example na ibe 8
2.6.1. Usoro ule
Soro usoro ndị a iji nwalee imewe exampna hardware:

1. Tupu ị na-agba ọsọ ngwaike ule nke a imewe examplee, ị ghaghị ịtọgharịa sistemụ ahụ:
   a. Pịa Ngwaọrụ ➤ In-System Sources & Probes Editor tool for the default Source and Probe GUI.
   b. Gbanwee mgbaama nrụpụta sistemụ (Isi Iyi[3:0]) site na 7 ruo 8 ka itinye nrụgharị ahụ wee weghachi mgbama nrụpụta sistemụ azụ na 7 iji hapụ sistemụ ahụ na steeti nrụpụta.
   c. Nyochaa akara ngosi nyocha wee hụ na ọkwa ahụ ziri ezi.
2. Na njikwa sistemụ, gaa na folda hwtest wee mee iwu: isi iyi main.tcl ka ịhọrọ J.TAG nna ukwu. Site na ndabara, nke mbụ JTAG nna ukwu na JTAG agbụ a na-ahọrọ. Ka ịhọrọ JTAG nna ukwu maka ngwaọrụ Intel Agilex, mee iwu a: set_jtag <number of appropriate JTAG nna ukwu>. Ọpụample: set_jtag 1.
3. Gbaa iwu ndị a na njikwa sistemụ ka ịmalite ule loopback serial:

Tebụl 7. Ụkpụrụ Iwu

Oke	Nkọwa	Example ojiji
chkphy_ọnọdụ	Na-egosiputa ugboro elekere yana ọkwa mkpọchi PHY.	% chkphy_status 0 # Lelee ọkwa njikọ 0
chkmac_stats	Na-egosiputa ụkpụrụ dị na ọnụọgụ ọnụ ọgụgụ MAC.	% chkmac_stats 0 # Na-enyocha akara ọnụ ọgụgụ mac nke njikọ 0
kpochapụ_ihe niile_stats	Na-ehichapụ ọnụ ọgụgụ ọnụọgụ IP isi.	% clear_all_stats 0 # Na-ekpochapụ ọnụ ọgụgụ ọnụọgụ njikọ 0
mmalite_gen	Na-amalite generator nke ngwugwu.	% start_gen 0 # Malite ọgbọ ngwugwu na njikọ 0
nkwụsị_gen	Kwụsị generator nke ngwugwu.	% stop_gen 0 # Kwụsị ọgbọ ngwugwu na njikọ 0
loop_na	Na-agbanye n'ime usoro loopback.	% loop_on 0 # Gbanwuo loopback nke ime na njikọ 0
loop_off	Na-agbanyụ azụ azụ azụ serial dị n'ime.	% loop_off 0 # Gbanyụọ loopback nke ime na njikọ 0
reg_agụ	Na-eweghachite uru ndekọ aha IP isi na .	% reg_read 0x402 # Gụọ IP CSR ndekọ na adreesị 402 nke njikọ 0
reg_write	Na-ede gaa na ndekọ isi IP na adreesị .	% reg_write 0x401 0x1 # Dee 0x1 na IP CSR ndekọ ọkọ na adreesị 401 nke njikọ 0

a. Pịnye loop_on ka ịgbanwuo usoro loopback nke ime.
b. Pịnye chkphy_status ka ịlele ọkwa PHY. Ọnọdụ TXCLK, RXCLK na RX kwesịrị inwe otu ụkpụrụ egosiri n'okpuru maka njikọ kwụsiri ike:

c. Pịnye clear_all_stats iji kpochapụ ndekọ ọnụ ọgụgụ TX na RX.
d. Pịnye start_gen ịmalite ọgbọ ngwugwu.
e. Ụdị stop_gen iji kwụsị ọgbọ ngwugwu.
f. Pịnye chkmac_stats ịgụta ọnụ ọgụgụ TX na RX. Gbaa mbọ hụ na:
i. Okpokoro ngwungwu ebutere dabara na okpokolo agba enwetara.
ii. Enweghị fremu mperi anabatara.
g. Pịnye loop_off ka gbanyụọ esịtidem serial loopback.
Onyonyo 7. Sample Mmepụta Nnwale—TX na RX Statistics Counters

Akụkọ ngbanwe akwụkwọ maka F-tile 25G Ethernet FPGA IP Design Example ntuziaka onye ọrụ

Ụdị akwụkwọ	Intel Quartus Prime Version	Ụdị IP	Mgbanwe
2022.10.14	22.3	1.0.0	Ntọhapụ mbụ.

Ụlọ ọrụ Intel. Ikike niile echekwabara. Intel, akara Intel, na akara Intel ndị ọzọ bụ ụghalaahịa nke Intel Corporation ma ọ bụ ndị enyemaka ya. Intel nyere ikike ịrụ ọrụ nke FPGA na ngwaahịa semiconductor na nkọwapụta ugbu a dịka akwụkwọ ikike ọkọlọtọ Intel siri dị, mana nwere ikike ịme mgbanwe na ngwaahịa na ọrụ ọ bụla n'oge ọ bụla na-enweghị ọkwa. Intel anaghị ewere ọrụ ọ bụla ma ọ bụ ụgwọ sitere na ngwa ma ọ bụ iji ozi ọ bụla, ngwaahịa ma ọ bụ ọrụ akọwara n'ime ebe a belụsọ dị ka Intel kwetara na ederede. A dụrụ ndị ahịa Intel ọdụ ka ha nweta ụdị nkọwa ngwaọrụ kachasị ọhụrụ tupu ha adabere na ozi ọ bụla ebipụtara yana tupu ịnye iwu maka ngwaahịa ma ọ bụ ọrụ. * Enwere ike ịzọrọ aha na akara ndị ọzọ dị ka ihe onwunwe nke ndị ọzọ.
ISO
9001:2015
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Version nke Ntanetị
Zipu nzaghachi
Nọmba ederede: 750200
Ụdị: 2022.10.14

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intel F-Tile 25G Ethernet FPGA IP Design Example [pdf] Ntuziaka onye ọrụ F-Tile 25G Ethernet FPGA IP Design Example, F-Tile 25G, F-Tile 25G Ethernet FPGA, FPGA IP Design Ex.ample, IP Design Exampnke, 750200

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