intel HDMI PHY FPGA IP Design Example User Itọsọna
HDMI PHY Apẹrẹ Example Quick Bẹrẹ Itọsọna fun Intel® Arria® 10 awọn ẹrọ
HDMI PHY Intel® FPGA IP apẹrẹample fun Intel Arria® 10 awọn ẹrọ ẹya kan HDMI 2.0 RX-TX retransmit oniru ti o ṣe atilẹyin akopo ati hardware igbeyewo.
Nigba ti o ba se ina kan oniru example, paramita olootu laifọwọyi ṣẹda awọn files pataki lati ṣe simulate, ṣajọ, ati idanwo apẹrẹ ni hardware.
Nọmba 1. Awọn Igbesẹ Idagbasoke
Alaye ti o jọmọ
HDMI PHY Intel FPGA IP Itọsọna olumulo
Ti o npese awọn Design
Lo olootu paramita IP HDMI PHY PHY Intel FPGA ninu sọfitiwia Intel Quartus® Prime lati ṣe ipilẹṣẹ apẹrẹ tẹlẹamples.
olusin 2. Ti o npese awọn Design sisan
- Ṣẹda ise agbese kan ìfọkànsí Intel Arria 10 ẹrọ ebi ati ki o yan awọn ti o fẹ ẹrọ.
- Ninu Katalogi IP, wa ati tẹ Awọn Ilana Atọka Ilọpo meji ➤ Audio & Fidio ➤ HDMI TX PHY Intel FPGA IP (tabi HDMI RX PHY Intel FPGA IP). Iyatọ IP Tuntun tabi Ferese Iyipada IP Tuntun yoo han.
- Pato orukọ ipele-oke fun iyatọ IP aṣa rẹ. Olootu paramita n fipamọ awọn eto iyatọ IP ni a file ti a npè ni .ip tabi .qsys.
- Tẹ O DARA. Olootu paramita yoo han.
Intel Corporation. Gbogbo awọn ẹtọ wa ni ipamọ. Intel, aami Intel, ati awọn aami Intel miiran jẹ aami-iṣowo ti Intel
Ajọ tabi awọn ẹka rẹ. Intel ṣe atilẹyin iṣẹ ṣiṣe ti FPGA rẹ ati awọn ọja semikondokito si awọn pato lọwọlọwọ ni ibamu pẹlu atilẹyin ọja boṣewa Intel, ṣugbọn ni ẹtọ lati ṣe awọn ayipada si eyikeyi awọn ọja ati iṣẹ nigbakugba laisi akiyesi. Intel ko gba ojuse tabi layabiliti ti o dide lati inu ohun elo tabi lilo eyikeyi alaye, ọja, tabi iṣẹ ti a ṣalaye ninu rẹ ayafi bi a ti gba ni kikun si kikọ nipasẹ Intel. A gba awọn alabara Intel nimọran lati gba ẹya tuntun ti awọn pato ẹrọ ṣaaju gbigbekele eyikeyi alaye ti a tẹjade ati ṣaaju gbigbe awọn aṣẹ fun awọn ọja tabi awọn iṣẹ.
Awọn orukọ miiran ati awọn ami iyasọtọ le jẹ ẹtọ bi ohun-ini ti awọn miiran. - Lori apẹrẹ Example taabu, yan Arria 10 HDMI RX-TX Retransmit.
- Yan Simulation lati se ina testbench, ki o si yan Synthesis lati se ina awọn hardware oniru example.
O gbọdọ yan o kere ju ọkan ninu awọn aṣayan wọnyi lati ṣe ipilẹṣẹ apẹrẹ tẹlẹample files.
Ti o ba yan awọn mejeeji, akoko iran naa gun. - Fun ipilẹṣẹ File Ọna kika, yan Verilog tabi VHDL.
- Fun Apo Idagbasoke Àkọlé, yan Intel Arria 10 GX FPGA Development
Kit. Ti o ba yan a idagbasoke kit, ki o si awọn afojusun ẹrọ ayipada lati baramu awọn ẹrọ lori afojusun ọkọ. Fun Apo Idagbasoke Intel Arria 10 GX FPGA, ẹrọ aifọwọyi jẹ 10AX115S2F4I1SG. - Tẹ ina Example Design.
Iṣakojọpọ ati Idanwo Oniru naa
Lati ṣajọ ati ṣiṣe idanwo ifihan lori hardware exampFun apẹrẹ, tẹle awọn igbesẹ wọnyi:
- Rii daju hardware example oniru iran jẹ pari.
- Lọlẹ Intel Quartus Prime software ki o si ṣi awọn .qpf file: /quartus/a10_hdmi2_demo.qpf
- Tẹ Ṣiṣeto ➤ Bẹrẹ Iṣakojọpọ.
- Lẹhin akojọpọ aṣeyọri, a .sof file ti wa ni ipilẹṣẹ ni kuotisi/jade_files liana.
- So Bitec HDMI 2.0 FMC Ọmọbinrin Kaadi Rev 11 si ori-ọkọ FMC ibudo B (J2).
- So TX (P1) ti kaadi ọmọbinrin Bitec FMC si orisun fidio ita.
- So RX (P2) ti kaadi ọmọbinrin Bitec FMC si ifọwọ fidio ita tabi oluyẹwo fidio.
- Rii daju pe gbogbo awọn iyipada lori igbimọ idagbasoke wa ni ipo aiyipada.
- Tunto awọn ti a ti yan Intel Arria 10 ẹrọ lori idagbasoke ọkọ lilo awọn ti ipilẹṣẹ .sof file (Awọn irinṣẹ ➤ Oluṣeto).
- Oluyanju yẹ ki o ṣafihan fidio ti ipilẹṣẹ lati orisun. Iṣakojọpọ ati Idanwo Oniru naa
Alaye ti o jọmọ
Intel Arria 10 FPGA Development Apo olumulo Itọsọna
HDMI PHY Intel FPGA IP Design Example Parameters
Table 1. HDMI PHY Intel FPGA IP Design Eksample Awọn paramita fun Intel Arria 10
Awọn ẹrọ
Awọn aṣayan wọnyi wa fun awọn ẹrọ Intel Arria 10 nikan.
| Paramita | Iye | Apejuwe |
| Apẹrẹ ti o wa Example | ||
| Yan Oniru | Arria 10 HDMI RX-TX Retransmit | Yan apẹrẹ example lati wa ni ipilẹṣẹ. |
| Apẹrẹ Example Files | ||
| Afọwọṣe | Tan, paa | Tan aṣayan yii lati ṣe ina pataki files fun testbench kikopa. |
| Akopọ | Tan, paa | Tan aṣayan yii lati ṣe ina pataki files fun Intel Quartus Prime akopo ati hardware ifihan. |
| Ti ipilẹṣẹ HDL kika | ||
| Ṣẹda File Ọna kika | Verilog, VHDL | Yan ọna kika HDL ti o fẹ fun apẹrẹ ti ipilẹṣẹ example fileṣeto.
Akiyesi: Aṣayan yii nikan pinnu ọna kika fun ipilẹṣẹ IP ipele oke files. Gbogbo miiran files (fun apẹẹrẹ, Example testbenches ati oke ipele files fun ifihan ohun elo) wa ni ọna kika Verilog HDL. |
| Àkọlé Development Kit | ||
| Yan Board | Ko si Apo Idagbasoke, | Yan igbimọ fun apẹrẹ ìfọkànsí example. |
| Arria 10 GX Apo Idagbasoke FPGA,
Aṣa Development Apo |
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| Àkọlé Device | ||
| Yi Àkọlé Device | Tan, paa | Tan aṣayan yii ki o yan iyatọ ẹrọ ti o fẹ fun ohun elo idagbasoke. |
HDMI 2.0 PHY Design Example
HDMI PHY Intel FPGA IP apẹrẹ example ṣe afihan ọkan HDMI apẹẹrẹ parallel loopback ti o ni awọn ikanni RX mẹta ati awọn ikanni TX mẹrin, ti n ṣiṣẹ ni awọn oṣuwọn data to 6 Gbps.
Awọn ti ipilẹṣẹ HDMI PHY Intel FPGA IP oniru example jẹ kanna bi apẹrẹ example ti ipilẹṣẹ ni HDMI Intel FPGA IP mojuto. Sibẹsibẹ, apẹrẹ yii example lo TX PHY tuntun, RX PHY, ati arbiter PHY dipo aṣa aṣa aṣa ni HDMI Intel FPGA IP core design example.
olusin 3. HDMI 2.0 PHY Design Example
| Modulu | Apejuwe |
| RX PHY | RX PHY gba data HDMI ni tẹlentẹle ati fi eyi ranṣẹ si mojuto HDMI RX ni ọna ti o jọra lori awọn agbegbe aago ti o gba pada (rx_clk[2:0]). Awọn data ti wa ni decoded sinu fidio |
| Modulu | Apejuwe |
| data lati wa ni o wu nipasẹ AXI4-fidio. RX PHY naa tun nfiranṣẹ awọn ifihan agbara vid_clk ati ls_clk si HDMI RX core nipasẹ wiwo PHY. | |
| HDMI TX mojuto | HDMI TX mojuto gba data fidio ṣiṣan AXI4 ati ṣe koodu eyi sinu data afiwe ọna kika HDMI. HDMI TX mojuto fi data yii ranṣẹ si TX PHY. |
| HDMI RX mojuto | IP naa gba data ni tẹlentẹle lati RX PHY ati ṣe titete data, deskew ikanni, iyipada TMDS, iyipada data iranlọwọ, iyipada data fidio, iyipada data ohun, ati sisọnu. |
| TX PHY | Ngba ati serializes data afiwe lati HDMI TX mojuto ati awọn ọnajade HDMI TMDS ṣiṣan. TX PHY ṣe agbejade tx_clk fun mojuto HDMI TX. TX PHY naa tun ṣe ipilẹṣẹ vid_clk ati ls_clk ati firanṣẹ awọn ifihan agbara wọnyi si HDMI TX mojuto nipasẹ wiwo PHY. |
| IOPLL | Ṣe ina 300 MHz AXI ni tẹlentẹle ṣiṣan aago fun wiwo ṣiṣan AXI4. |
| I2C Titunto | Lati tunto awọn orisirisi PCB irinše. |
Hardware ati Software Awọn ibeere
Intel nlo awọn wọnyi hardware ati software lati se idanwo awọn oniru example.
Hardware
- Intel Arria 10 GX FPGA Development Apo
- Orisun HDMI (Ẹka Processor Eya aworan (GPU)
- HDMI rì (Atẹle)
- Bitec HDMI kaadi ọmọbinrin FMC 2.0 (Atunyẹwo 11)
- HDMI kebulu
Software
- Intel Quartus Prime Pro Edition (fun idanwo ohun elo)
- AwoṣeSim* – Intel FPGA Edition, ModelSim – Intel FPGA Starter Edition, NCSim,
Riviera-PRO*, VCS* (Verilog HDL nikan)/VCS MX, tabi Xcelium* Simulator parallel
Ilana Ilana
Awọn ilana ni awọn ti ipilẹṣẹ file fun HDMI Intel FPGA IP oniru example.
olusin 4. Ilana Itọsọna fun Oniru Example
Reconfiguration Ọkọọkan Sisan
olusin 5. Olona-oṣuwọn Reconfiguration Ọkọọkan Sisan
Nọmba naa ṣe afihan ṣiṣan isọdọtun iwọn-ọpọlọpọ ti oluṣakoso nigbati o gba ṣiṣan data titẹ sii ati igbohunsafẹfẹ aago itọkasi, tabi nigbati transceiver ti wa ni ṣiṣi silẹ.
Awọn ifihan agbara wiwo
Awọn tabili ṣe atokọ awọn ifihan agbara fun HDMI PHY Intel FPGA IP apẹrẹ example.
Table 3. Top-Level awọn ifihan agbara
| Ifihan agbara | Itọsọna | Ìbú | Apejuwe |
| Lori-ọkọ Oscillator Signal | |||
| clk_fpga_b3_p | Iṣawọle | 1 | 100 MHz free nṣiṣẹ aago fun mojuto itọkasi aago |
| refclk_fmcb_p | Iṣawọle | 1 | Aago itọkasi oṣuwọn ti o wa titi fun isọdọtun agbara-soke ti transceiver. O jẹ 625 MHz nipasẹ aiyipada ṣugbọn o le jẹ ti igbohunsafẹfẹ eyikeyi |
| Awọn bọtini Titari olumulo ati Awọn LED | |||
| cpu_resetn | Iṣawọle | 1 | Atunto agbaye |
| olumulo_led_g | Abajade | 2 | Green LED àpapọ |
| Awọn pinni Kaadi Ọmọbinrin HDMI FMC lori Port B | |||
| fmcb_gbtclk_m2c_p_0 | Iṣawọle | 1 | HDMI RX TMDS aago |
| fmcb_dp_m2c_p | Iṣawọle | 3 | HDMI RX pupa, alawọ ewe, ati awọn ikanni data bulu
• Bitec ọmọbinrin kaadi àtúnyẹwò 11 - [0]: ikanni RX TMDS 1 (Awọ ewe) - [1]: ikanni RX TMDS 2 (pupa) - [2]: RX TMDS ikanni 0 (bulu) |
| fmcb_dp_c2m_p | Abajade | 4 | Aago HDMI TX, pupa, alawọ ewe, ati awọn ikanni data bulu
• Bitec ọmọbinrin kaadi àtúnyẹwò 11 - [0]: ikanni TX TMDS 2 (pupa) - [1]: TX TMDS ikanni 1 (Awọ ewe) - [2]: TX TMDS ikanni 0 (bulu) - [3]: TX TMDS aago ikanni |
| fmcb_la_rx_p_9 | Iṣawọle | 1 | HDMI RX + 5V agbara iwari |
| fmcb_la_rx_p_8 | Iṣawọle | 1 | HDMI RX gbona plug iwari |
| fmcb_la_rx_n_8 | Iṣawọle | 1 | HDMI RX I2C SDA fun DDC ati SCDC |
| fmcb_la_tx_p_10 | Iṣawọle | 1 | HDMI RX I2C SCL fun DDC ati SCDC |
| fmcb_la_tx_p_12 | Iṣawọle | 1 | HDMI TX gbona plug iwari |
| fmcb_la_tx_n_12 | Iṣawọle | 1 | HDMI I2C SDA fun DDC ati SCDC |
| fmcb_la_rx_p_10 | Iṣawọle | 1 | HDMI I2C SCL fun DDC ati SCDC |
| fmcb_la_tx_p_11 | Iṣawọle | 1 | HDMI I2C SDA fun iṣakoso atunṣe |
| fmcb_la_rx_n_9 | Iṣawọle | 1 | HDMI I2C SCL fun iṣakoso atunṣe |
Eto aago
Atẹle ni ero aago ti HDMI PHY Intel FPGA IP apẹrẹ example:
- clk_fpga_b3_p jẹ aago oṣuwọn 100 MHz ti o wa titi fun ṣiṣe ẹrọ isise NIOS ati awọn iṣẹ iṣakoso. Ti igbohunsafẹfẹ ti a pese ba tọ, olumulo_led_g[1] yoo yipada fun iṣẹju-aaya kọọkan.
- refclk_fmcb_p jẹ aago itọkasi oṣuwọn ti o wa titi fun isọdọtun agbara ti awọn transceivers. O jẹ 625 MHz nipasẹ aiyipada ṣugbọn o le jẹ ti igbohunsafẹfẹ eyikeyi.
- fmcb_gbtclk_m2c_p_0 jẹ aago TMDS fun HDMI RX. Aago yii tun lo lati wakọ awọn transceivers HDMI TX. Ti igbohunsafẹfẹ ti a pese ba jẹ 148.5 MHz, olumulo_led_g [0] yoo yipada fun iṣẹju-aaya kọọkan.
Hardware Oṣo
HDMI PHY Intel FPGA IP apẹrẹ example jẹ HDMI 2.0b lagbara ati ki o ṣe ifihan lupu-nipasẹ ifihan fun boṣewa HDMI fidio ṣiṣan.
Lati ṣiṣẹ idanwo ohun elo, so ohun elo HDMI ti o ṣiṣẹ gẹgẹbi kaadi eya aworan pẹlu wiwo HDMI si asopọ HDMI RX lori kaadi ọmọbinrin Bitec HDMI 2.0, eyiti o da data naa si bulọki RX transceiver ati HDMI RX.
- Awọn ifọwọ HDMI ṣe ipinnu ibudo naa sinu ṣiṣan fidio boṣewa ati firanṣẹ si mojuto imularada aago.
- HDMI RX mojuto ṣe ipinnu fidio, oluranlọwọ, ati data ohun lati wa ni yipo pada nipasẹ wiwo ṣiṣan AXI4 si ipilẹ HDMI TX.
- Ibudo orisun HDMI ti kaadi ọmọbinrin FMC n gbe aworan naa si atẹle kan.
- Tẹ bọtini cpu_resetn ni ẹẹkan lati ṣe atunto eto.
Akiyesi: Ti o ba fẹ lo igbimọ idagbasoke Intel FPGA miiran, o gbọdọ yi awọn iṣẹ iyansilẹ ẹrọ ati awọn iṣẹ iyansilẹ pin. Eto afọwọṣe transceiver ti ni idanwo fun ohun elo idagbasoke Intel Arria 10 FPGA ati kaadi ọmọbinrin Bitec HDMI 2.0. O le ṣe atunṣe awọn eto fun igbimọ tirẹ.
Itan Atunyẹwo iwe fun HDMI PHY Intel
FPGA IP Design Example User Itọsọna
| Ẹya Iwe aṣẹ | Intel Quartus NOMBA Version | Ẹya IP | Awọn iyipada |
| 2022.07.20 | 22.2 | 1.0.0 | Itusilẹ akọkọ. |
Awọn iwe aṣẹ / Awọn orisun
 |
intel HDMI PHY FPGA IP Design Example [pdf] Itọsọna olumulo HDMI PHY FPGA IP Design Example, HDMI PHY, FPGA IP Design Example, HDMI PHY IP Design Example, FPGA IP Design Example, IP Design Example,732781 |
