intel Chip ID FPGA IP Cores

Kowane Intel® FPGA mai goyan bayan yana da keɓaɓɓen ID na guntu 64-bit. Chip ID Intel FPGA IP cores yana ba ku damar karanta wannan guntu ID don gano na'urar.

Bayanai masu alaƙa

• Gabatarwa zuwa Intel FPGA IP Cores
  • Yana ba da cikakken bayani game da duk na'urorin IP na Intel FPGA, gami da daidaitawa, haɓakawa, haɓakawa, da kwaikwaiyon bayanan IP.
• Ƙirƙirar Rubutun Saita Haɗaɗɗen Simulator
  • Ƙirƙirar rubutun kwaikwaiyo waɗanda baya buƙatar ɗaukakawar hannu don haɓaka software ko sigar IP.

Tallafin na'ura

IP Cores	Na'urori masu tallafi
Chip ID Intel Stratix® 10 FPGA IP core	Intel Stratix 10
Musamman Chip ID Intel Arria® 10 FPGA IP core	Intel Arria 10
Musamman Chip ID Intel Cyclone® 10 GX FPGA IP core	Intel Cyclone 10 GX
Na musamman Chip ID Intel MAX® 10 FPGA IP	Intel MAX 10
Musamman Chip ID Intel FPGA IP core	Stratix V Arria V Cyclone V

Bayanai masu alaƙa

• Na musamman Chip ID Intel MAX 10 FPGA IP Core

Chip ID Intel Stratix 10 FPGA IP Core

• Wannan sashe yana bayanin Chip ID Intel Stratix 10 FPGA IP core.

Bayanin Aiki

Siginar data_valid yana farawa ƙasa kaɗan a farkon yanayin inda ba a karanta bayanai daga na'urar. Bayan ciyar da bugun jini mai girma zuwa ƙasa zuwa tashar shigar da aka karanta, Chip ID Intel Stratix 10 FPGA IP yana karanta ID ɗin guntu na musamman. Bayan karantawa, ainihin IP ɗin yana tabbatar da siginar data_valid don nuna cewa ƙimar ID ɗin guntu na musamman a tashar fitarwa ta shirya don dawowa. Aikin yana maimaitawa kawai lokacin da ka sake saita ainihin IP. Tashar tashar fitarwa ta chip_id[63:0] tana riƙe da ƙimar guntu na musamman har sai kun sake saita na'urar ko sake saita ainihin IP.

Lura: Ba za ku iya kwaikwayi Chip ID IP core ba saboda IP core yana karɓar amsa akan bayanan ID guntu daga SDM. Don tabbatar da wannan cibiya ta IP, Intel yana ba da shawarar yin kimanta kayan aikin.

Tashoshi

Hoto na 1: Chip ID Intel Stratix 10 FPGA IP Core Ports

Tebur 2: Chip ID Intel Stratix 10 FPGA IP Core Ports Bayanin

Port	I/O	Girman (Bit)	Bayani
klkin	Shigarwa	1	Ciyar da siginar agogo zuwa toshe ID guntu. Matsakaicin mitar da aka goyan baya yayi daidai da agogon tsarin ku.
sake saiti	Shigarwa	1	Sake saitin aiki tare wanda ke sake saita ainihin IP. Don sake saita ainihin IP, tabbatar da siginar sake saiti babba don aƙalla zagayowar clkin 10.
data_inci	Fitowa	1	Yana nuna cewa keɓaɓɓen ID ɗin guntu yana shirye don dawowa. Idan siginar ta yi ƙasa, asalin IP ɗin yana cikin yanayin farko ko yana ci gaba don loda bayanai daga ID ɗin fuse. Bayan tushen IP ɗin ya tabbatar da siginar, bayanan suna shirye don dawowa a tashar fitarwa ta chip_id[63..0].
chip_id	Fitowa	64	Yana nuna keɓaɓɓen ID ɗin guntu bisa ga wurin ID ɗin fius ɗin sa. Bayanan yana aiki ne kawai bayan ainihin IP ɗin ya tabbatar da siginar data_valid. Ƙimar da ke sama tana sake saitawa zuwa 0. Chip_id [63:0] tashar fitarwa yana riƙe da ƙimar keɓaɓɓen ID ɗin guntu har sai kun sake saita na'urar ko sake saita ainihin IP.
karanta	Shigarwa	1	Ana amfani da siginar da aka karanta don karanta ƙimar ID daga na'urar. Duk lokacin da siginar ta canza ƙima daga 1 zuwa 0, tushen IP yana haifar da aikin ID na karantawa. Dole ne ku fitar da siginar zuwa 0 lokacin da ba a amfani da shi. Don fara aikin ID na karanta, fitar da siginar sama sama don aƙalla zagayowar agogo 3, sannan ja shi ƙasa. Cibiyar IP ta fara karanta ƙimar guntu ID.

Samun Chip ID Intel Stratix 10 FPGA IP ta hanyar Taɓa Siginar

Lokacin da kuka kunna siginar da aka karanta, Chip ID Intel Stratix 10 FPGA IP core yana fara karanta guntu ID daga na'urar Intel Stratix 10. Lokacin da guntu ID ya shirya, Chip ID Intel Stratix 10 FPGA IP core yana tabbatar da siginar data_inci kuma yana ƙare J.TAG shiga.

Lura: Bada izinin jinkiri daidai da tCD2UM bayan cikakken tsarin guntu kafin yunƙurin karanta ID ɗin guntu na musamman. Koma takardar bayanan na'urar don ƙimar tCD2UM.

Sake saita Chip ID Intel Stratix 10 FPGA IP Core

Don sake saita ainihin IP, dole ne ka tabbatar da siginar sake saiti don aƙalla zagayowar agogo goma.

Lura

1. Don na'urorin Intel Stratix 10, kar a sake saita ainihin IP har sai aƙalla tCD2UM bayan ƙaddamar da guntu cikakke. Koma takardar bayanan na'urar don ƙimar tCD2UM.
2. Don jagororin nan take na ainihin IP, dole ne ku koma zuwa sashin Sake saitin Sakewa na Intel Stratix 10 a cikin Jagorar Mai amfani na Kanfigareshan Intel Stratix 10.

Bayanai masu alaƙa

Intel Stratix 10 Jagorar Mai amfani Kanfigareshan

• Yana ba da ƙarin bayani game da Intel Stratix 10 Sake saitin Sakin IP.

Chip ID Intel FPGA IP Cores

Wannan sashe yana bayyana abubuwan da suka biyo baya na IP

• Musamman Chip ID Intel Arria 10 FPGA IP core
• Musamman Chip ID Intel Cyclone 10 GX FPGA IP core
• Musamman Chip ID Intel FPGA IP core

Bayanin Aiki

Siginar data_valid yana farawa ƙasa kaɗan a farkon yanayin inda ba a karanta bayanai daga na'urar. Bayan ciyar da siginar agogo zuwa tashar shigar da clkin, Chip ID Intel FPGA IP core yana karanta ID ɗin guntu na musamman. Bayan karantawa, ainihin IP ɗin yana tabbatar da siginar data_valid don nuna cewa ƙimar ID ɗin guntu na musamman a tashar fitarwa ta shirya don dawowa. Aikin yana maimaitawa kawai lokacin da ka sake saita ainihin IP. Tashar tashar fitarwa ta chip_id[63:0] tana riƙe da ƙimar guntu na musamman har sai kun sake saita na'urar ko sake saita ainihin IP.

Lura: Intel Chip ID IP core bashi da simulation model files. Don tabbatar da wannan cibiya ta IP, Intel yana ba da shawarar yin kimanta kayan aikin.

Hoto na 2: Chip ID Intel FPGA IP Core Ports

Tebur 3: Chip ID Intel FPGA IP Core Description

Port	I/O	Girman (Bit)	Bayani
klkin	Shigarwa	1	Ciyar da siginar agogo zuwa toshe ID guntu. Matsakaicin mitoci masu goyan baya sune kamar haka: • Don Intel Arria 10 da Intel Cyclone 10 GX: 30 MHz. • Don Intel MAX 10, Stratix V, Arria V da Cyclone V: 100 MHz.
sake saiti	Shigarwa	1	Sake saitin aiki tare wanda ke sake saita ainihin IP. Don sake saita ainihin IP, tabbatar da siginar sake saiti babba don aƙalla zagayowar clkin 10(1). Chip_id [63:0] tashar fitarwa yana riƙe da ƙimar keɓaɓɓen ID ɗin guntu har sai kun sake saita na'urar ko sake saita ainihin IP.
data_inci	Fitowa	1	Yana nuna cewa keɓaɓɓen ID ɗin guntu yana shirye don dawowa. Idan siginar ta yi ƙasa, asalin IP ɗin yana cikin yanayin farko ko yana ci gaba don loda bayanai daga ID ɗin fuse. Bayan tushen IP ɗin ya tabbatar da siginar, bayanan suna shirye don dawowa a tashar fitarwa ta chip_id[63..0].
chip_id	Fitowa	64	Yana nuna keɓaɓɓen ID ɗin guntu bisa ga wurin ID ɗin fius ɗin sa. Bayanan yana aiki ne kawai bayan ainihin IP ɗin ya tabbatar da siginar data_valid. Ƙimar da ke sama tana sake saitawa zuwa 0.

Samun Gano Na Musamman Chip ID Intel Arria 10 FPGA IP da Na Musamman Chip ID Intel Cyclone 10 GX FPGA IP ta Siginar Taɓa

Lura: Intel Arria 10 da Intel Cyclone 10 GX guntu ID ba su da samuwa idan kuna da wasu tsarin ko abubuwan IP masu shiga J.TAG lokaci guda. Don misaliample, Siginar Tap II Logic Analyzer, Transceiver Toolkit, in-system sigina ko bincike, da SmartVID Controller IP core.

Lokacin da kuka kunna siginar sake saiti, Babban ID ɗin Chip ID Intel Arria 10 FPGA IP da keɓaɓɓen ID na Intel Cyclone 10 GX FPGA IP suna fara karanta guntu ID daga na'urar Intel Arria 10 ko Intel Cyclone 10 GX. Lokacin da guntu ID ya shirya, Unique Chip ID Intel Arria 10 FPGA IP da Unique Chip ID Intel Cyclone 10 GX FPGA IP cores suna tabbatar da siginar data_daidaitacce kuma yana ƙare J.TAG shiga.

Lura: Bada izinin jinkiri daidai da tCD2UM bayan cikakken tsarin guntu kafin yunƙurin karanta ID ɗin guntu na musamman. Koma takardar bayanan na'urar don ƙimar tCD2UM.

Sake saita Chip ID Intel FPGA IP Core

Don sake saita ainihin IP, dole ne ka tabbatar da siginar sake saiti don aƙalla zagayowar agogo goma. Bayan kun saka siginar sake saiti, asalin IP ɗin yana sake karanta ID ɗin guntu na musamman daga toshe ID na fuse. Babban IP ɗin yana tabbatar da siginar data_valid bayan kammala aikin.

Lura: Don Intel Arria 10, Intel Cyclone 10 GX, Intel MAX 10, Stratix V, Arria V, da na'urorin Cyclone V, kar su sake saita ainihin IP har sai aƙalla tCD2UM bayan cikakken fara guntu. Koma takardar bayanan na'urar don ƙimar tCD2UM.

Chip ID Intel FPGA IP Cores Archives Jagorar Mai Amfani

Idan ba a jera sigar ainihin IP ba, jagorar mai amfani don sigar ainihin IP ta baya tana aiki.

IP Core Version	Jagorar Mai Amfani
18.1	Chip ID Intel FPGA IP Cores Jagorar Mai Amfani
18.0	Chip ID Intel FPGA IP Cores Jagorar Mai Amfani

Tarihin Bita na Takardu don Jagoran Mai Amfani na Chip ID Intel FPGA IP Cores

Sigar Takardu	Intel Quartus® Babban Sigar	Canje-canje
2022.09.26	20.3	An cire Mafi kyawun Ayyukan Gudanarwa mahada. An sabunta Bayanin Aiki a cikin Chip ID Intel Stratix 10 FPGA IP Core. An sabunta Bayanin Aiki a cikin Chip ID Intel FPGA IP Cores.
2020.10.05	20.3	An sabunta bayanin klkin da sake saiti a cikin Tebur: Chip ID Intel FPGA IP Core Description don haɗa bayanan Intel MAX 10. An sabunta ta Sake saita Chip ID Intel FPGA IP Core sashe don haɗa da goyan bayan na'urar Intel MAX 10.
2019.05.17	19.1	An sabunta ta Sake saita Chip ID Intel Stratix 10 FPGA IP Core batun don ƙara bayanin kula na biyu game da jagororin saɓo na ainihin IP.
2019.02.19	18.1	Ƙara tallafi don na'urorin Intel MAX 10 a cikin IP Cores da na'urori masu goyan baya tebur.
2018.12.24	18.1	Ya kara da Chip ID Intel FPGA IP Cores Archives Jagorar Mai Amfani sashe.  An sake fasalin daftarin aiki don samar da ƙarin cikakkun bayanai kan na'urori masu tallafi daban-daban.
2018.06.08	18.0	An sabunta bayanin tashar tashar da aka karanta. An sabunta bayanin sake saitin tashar jiragen ruwa.
2018.05.07	18.0	Ƙara tashar jiragen ruwa da aka karanta don Chip ID Intel Stratix 10 FPGA IP core.

 

Kwanan wata	Sigar	Canje-canje
Disamba 2017	2017.12.11	Sunan da aka sabunta daga Altera Unique Chip ID IP Core User Guide. Kara Tallafin na'ura sashe.  Haɗe da ƙarin bayani daga Altera Arria 10 Na Musamman Chip ID IP Jagorar Mai Amfani kuma Stratix 10 Na Musamman Chip ID IP Core User Guide. An sake sanyawa zuwa Intel. An sabunta Bayanin Aiki. An ƙara tallafin na'urar Intel Cyclone 10 GX.
Mayu 2016	2016.05.02	Cire daidaitaccen bayanin ainihin IP da ƙara hanyar haɗi zuwa littafin Jagora na Quartus Prime. Sabunta bayanin kula game da tallafin na'urar Arria 10.
Satumba, 2014	2014.09.02	• Sunan da aka sabunta don nuna sabon suna na "Altera Unique Chip ID" IP core.

Kwanan wata	Sigar	Canje-canje
Agusta, 2014	2014.08.18	Matakan daidaitawa da aka sabunta don editan siga na gado. Ƙara bayanin cewa wannan IP core baya goyan bayan ƙirar Arria 10.
Yuni, 2014	2014.06.30	Canjin bayanin Manajan Plug-In MegaWizard tare da Kasuwar IP. Ƙara daidaitattun bayanai game da haɓaka abubuwan haɗin IP. Ƙara daidaitattun shigarwa da bayanin lasisi. Cire bayanan matakin tallafin na'urar da ta gabata. Ana samun tallafin na'urar ainihin IP yanzu a cikin kasidar IP da editan siga.
Satumba, 2013	2013.09.20	An sabunta zuwa sake kalmar "Samun guntu ID na na'urar FPGA" zuwa "Samun takamaiman guntu ID na na'urar FPGA"
Mayu, 2013	1.0	Sakin farko.

Aika da martani

Takardu / Albarkatu

intel Chip ID FPGA IP Cores [pdf] Jagorar mai amfani Chip ID FPGA IP Cores, Chip ID, FPGA IP Cores, IP Cores

Magana

• Manual mai amfani