I-FPGA IP
I-Design Example Umhlahlandlela Womsebenzisi
I-F-Tile 25G Ethernet Intel®
Ibuyekezelwe i-Intel® Quartus®
I-Prime Design Suite: 22.3
Inguqulo ye-IP: 1.0.0

Quick Start Guide

I-F-tile 25G Ethernet Intel FPGA IP yamadivayisi we-Intel Agilex™ inikeza amandla okukhiqiza i-design ex.amples ekucushweni okukhethiwe.
Umfanekiso 1. Umklamo Example Ukusetshenziswa

Ukwakheka Kwemibhalo

Umfanekiso 2. 25G Ethernet Intel FPGA IP Design Example Ukwakheka Kwemibhalo

• Ukulingiswa files (i-testbench yokulingisa kuphela) itholakala kuample_dir>/example_testbench.
• I-ex yedizayini yokuhlanganisa kuphelaample itholakala kuample_dir>/ compilation_test_design.
• Ukucushwa kwezingxenyekazi zekhompuyutha nokuhlola files (umklamo example in hardware) zitholakala kuample_dir>/hardware_test_design.

Ithebula 1. Uhla lwemibhalo kanye File Izincazelo

File Amagama	Incazelo
ethi_ex_25g.qpf	Intel Quartus® Prime project file.
eth_ex_25g.qsf	Izilungiselelo zephrojekthi ye-Intel Quartus Prime file.
eth_ex_25g.sdc	I-Synopsys Design Constrants file. Ungakopisha futhi ulungise lokhu file ngomklamo wakho oyinhloko we-25GbE Intel FPGA IP.
eth_ex_25g.v	Idizayini yezinga eliphezulu ye-Verilog HDL example file. Umklamo wesiteshi esisodwa usebenzisa i-Verilog file.
okuvamile/	Idizayini yezingxenyekazi zekhompuyutha example support files.
hwtest/main.tcl	Okuyinhloko file ukuze ufinyelele Ikhonsoli Yesistimu.

Ukukhiqiza I-Design Example

Umfanekiso 4. Example-Design Tab ku-F-tile 25G Ethernet Intel FPGA IP Parameter Editor

Landela lezi zinyathelo ukuze ukhiqize i-ex ye-hardware designample kanye ne-testbench:

1. Ku-Intel Quartus Prime Pro Edition, chofoza File ➤ Iseluleki Sephrojekthi Esisha sokudala iphrojekthi entsha ye-Quartus Prime, noma File ➤ Vula Iphrojekthi ukuze uvule iphrojekthi ekhona ye-Quartus Prime. Iwizadi ikutshela ukuthi ucacise idivayisi.
2. Kukhathalogi ye-IP, thola bese ukhetha i-25G Ethernet Intel FPGA IP ye-Agilex. Iwindi le-New IP Variation liyavela.
3. Cacisa igama lezinga eliphezulu lokuhluka kwakho kwe-IP bese uchofoza okuthi KULUNGILE. Umhleli wepharamitha wengeza izinga eliphezulu elithi .ip file kuphrojekthi yamanje ngokuzenzakalela. Uma ucelwa ukuthi ungeze ngokwakho i-.ip file kuphrojekthi, chofoza Iphrojekthi ➤ Engeza/Susa Files kuphrojekthi yokwengeza i file.
4. Kusofthiwe ye-Intel Quartus Prime Pro Edition, kufanele ukhethe idivayisi ethile ye-Intel Agilex endaweni yeDivayisi, noma ugcine idivayisi ezenzakalelayo isofthiwe ye-Intel Quartus Prime ehlongozwayo.
   Qaphela: I-hardware design exampibhala phezu kwalokho okukhethiwe ngocingo ebhodini eliqondiwe. Ucacisa ibhodi eliqondiwe kusuka kumenyu ye-design example ongakhetha kukho Example Design ithebhu.
5. Chofoza okuthi KULUNGILE. Umhleli wepharamitha uyavela.
6. Kuthebhu ye-IP, cacisa imingcele yokuhluka kwakho okubalulekile kwe-IP.
7. Ku-Example Dizayini ithebhu, Example Design Files, khetha inketho yokulingisa ukuze ukhiqize ibhentshi lokuhlola, bese ukhetha inketho ye-Synthesis ukuze ukhiqize i-ex yedizayini yehadiwe.ample. Kuphela Verilog HDL files ziyakhiqizwa.
   Qaphela: I-VHDL IP core esebenzayo ayitholakali. Cacisa i-Verilog HDL kuphela, ye-IP core design ex yakhoample.
8. Ngekhithi Yokuthuthukiswa Kwethagethi, khetha i-Agilex I-series Transceiver-SoC Dev Kit
9. Chofoza okuthi Khiqiza i-Exampinkinobho ethi Design. Khetha ExampIwindi le-Design Directory liyavela.
10. Uma ufisa ukuguqula i-design example mkhombandlela noma igama elivela kokumisiwe okubonisiwe (alt_e25_f_0_example_design), phequlula endleleni entsha bese uthayipha umklamo omusha exampigama lenkomba (ample_dir>).
11. Chofoza okuthi KULUNGILE.

1.2.1. Umklamo Example Amapharamitha
Ithebula 2. Amapharamitha ku-ExampIthebhu Yokuklama

Ipharamitha	Incazelo
Example Design	Isib esitholakalayoampidizayina izilungiselelo zepharamitha ye-IP. Ex wesiteshi esisodwa kuphelaample design isekelwe kule IP.
Example Design Files	I files ukukhiqizela isigaba sentuthuko esihlukene. • Ukulingisa—kukhiqiza okudingekayo files yokulingisa i-exampumklamo. • I-synthesis—ikhiqiza ukuhlanganisa files. Sebenzisa lezi files ukuhlanganisa umklamo kusofthiwe ye-Intel Quartus Prime Pro Edition yokuhlolwa kwezingxenyekazi zekhompuyutha nokwenza ukuhlaziya isikhathi esimile.
Khiqiza File Ifomethi	Ifomethi ye-RTL files yokulingisa—Verilog.
Khetha Ibhodi	Izingxenyekazi zekhompuyutha ezisekelwayo zokuqaliswa komklamo. Uma ukhetha ibhodi lokuthuthukisa le-Intel FPGA, sebenzisa idivayisi i-AGIB027R31B1E2VRO njengeDivayisi Eliqondiwe ku-design ex.ample generation. I-Agilex I-series Transceiver-SoC Dev Kit: Le nketho ikuvumela ukuthi uhlole i-design example kukhithi yokuthuthukisa ye-Intel FPGA IP ekhethiwe. Le nketho ikhetha ngokuzenzakalelayo Idivayisi Eqondiwe ye-AGIB027R31B1E2VRO. Uma ukubuyekezwa kwebhodi lakho kunebanga elihlukile ledivayisi, ungashintsha idivayisi eqondiwe. Lutho: Le nketho ayifaki izici zehadiwe ye-ex yedizayiniample.

1.3. Ikhiqiza Ithayela Files

I-Support-Logic Generation isinyathelo sokuhlanganiswa kwangaphambili esisetshenziselwa ukukhiqiza okuhlobene namathayili files edingekayo ekulingiseni kanye nokwakhiwa kwehadiwe. Ukwakhiwa kwethayela kuyadingeka kubo bonke
Ukulingisa kwedizayini okususelwe ku-F-tile. Kufanele uqedele lesi sinyathelo ngaphambi kokulingisa.

1. Emyalweni womyalo, zulazula uye kufolda ye-commilation_test_design ku-ex yakhoample design: cd /compilation_test_design.
2. Qalisa umyalo olandelayo: quartus_tlg alt_eth_25g

1.4. Kulingisa i-F-tile 25G Ethernet Intel FPGA IP Design 
Example Testbench
Ungakwazi ukuhlanganisa futhi ulingise umklamo ngokusebenzisa iskripthi sokulingisa kusukela kumyalo womyalo.

1. Emyalweni womyalo, shintsha inkomba yokusebenza ye-testbench: cdample_dir>/ex_25g/sim.
2. Qalisa ukulingisa ukusethwa kwe-IP:ip-setup-simulation -quartusproject=../../compilation_test_design/alt_eth_25g.qpf

Ithebula 3. Izinyathelo Zokulingisa I-Testbench

Isifanisi	Iziyalezo
VCS*	Emugqeni womyalo, thayipha okuthi sh run_vcs.sh
QuestaSim*	Emgqeni womyalo, thayipha i-vsim -do run_vsim.do -logfile vsim.log Uma ukhetha ukulingisa ngaphandle kokuletha i-QuestaSim GUI, thayipha i-vsim -c -do run_vsim.do -logfile vsim.log
I-cadence -Xcelium*	Emugqeni womyalo, thayipha okuthi sh run_xcelium.sh

Ukulingisa okuyimpumelelo kugcina ngomlayezo olandelayo:
Ukulingisa Kuphasisiwe. noma i-Testbench iqedile.
Ngemva kokuphothula ngempumelelo, ungakwazi ukuhlaziya imiphumela.
1.5. Ukuhlanganisa kanye nokulungiselela i-Design Exampku-Hardware
I-25G Ethernet Intel FPGA IP core parameter editor ikuvumela ukuthi uhlanganise futhi ulungiselele i-design ex.ampekhithi yokuthuthukisa eqondiwe.

Ukuhlanganisa nokumisa i-ex designampku-hardware, landela lezi zinyathelo:

1. Yethula isofthiwe ye-Intel Quartus Prime Pro Edition bese ukhetha Ukucubungula ➤ Qala Ukuhlanganisa ukuze uhlanganise umklamo.
2. Ngemva kokwenza into ye-SRAM file .sof, landela lezi zinyathelo ukuze uhlele i-hardware design example kudivayisi ye-Intel Agilex:
   a. Kumenyu yamathuluzi, chofoza uMhleli.
   b. Ku-Programmer, chofoza Ukusethwa Kwezingxenyekazi zekhompuyutha.
   c. Khetha idivayisi yokuhlela.
   d. Khetha bese wengeza ibhodi le-Intel Agilex kuseshini yakho ye-Intel Quartus Prime Pro Edition.
   e. Qinisekisa ukuthi Imodi isethwe ku-JTAG.
   f. Khetha idivayisi ye-Intel Agilex bese uchofoza Engeza idivayisi. I-Programmer ibonisa
   umdwebo webhulokhi wokuxhumana phakathi kwamadivayisi ebhodini lakho.
   g. Emgqeni ne-.sof yakho, hlola ibhokisi le-.sof.
   h. Thikha ibhokisi kokuthi Uhlelo/Lungisa ikholomu.
   i. Chofoza Qala.

1.6. Ihlola i-F-tile 25G Ethernet Intel FPGA IP Hardware Design Example
Ngemva kokuhlanganisa i-F-tile 25G Ethernet Intel FPGA IP core design example futhi uyilungiselele kudivayisi yakho ye-Intel Agilex, ungasebenzisa Ikhonsoli Yesistimu ukuhlela umongo we-IP.
Ukuze uvule ikhonsoli Yesistimu futhi uhlole idizayini yezingxenyekazi zekhompuyutha example, landela lezi zinyathelo:

1. Kuhlelo lwe-Intel Quartus Prime Pro Edition, khetha Amathuluzi ➤ Uhlelo
   Amathuluzi Okulungisa Amaphutha ➤ Ikhonsoli Yesistimu ukuze uqalise ikhonsoli yesistimu.
2. Kufasitelana le-Tcl Console, thayipha i-cd hwtest ukuze uguqule uhla lwemibhalo lube / hardware_test_design/hwtest.
3. Thayipha umthombo main.tcl ukuze uvule uxhumano ku-JTAG inkosi.

Landela inqubo yokuhlola engxenyeni yokuhlola izingxenyekazi zekhompuyutha ye-ex yomklamoample bese ubheka imiphumela yokuhlola kukhonsoli Yesistimu.

I-F-tile 25G Ethernet Design Example ye-Intel Agilex Amadivayisi

I-F-tile 25G Ethernet design exampI-le ikhombisa isisombululo se-Ethernet samadivayisi we-Intel Agilex esebenzisa i-25G Ethernet Intel FPGA IP core.
Khiqiza i-ex designample kusuka ku-Example Design ithebhu yomhleli wepharamitha ye-25G Ethernet Intel FPGA IP. Ungaphinda ukhethe ukwenza umklamo usebenzisa noma ngaphandle
isici se-Reed-Solomon Forward Error Correction (RS-FEC).
2.1. Izici

• Isekela isiteshi se-Ethernet esisodwa esisebenza ku-25G.
• Ikhiqiza i-design example ngesici se-RS-FEC.
• Ihlinzeka nge-testbench nesikripthi sokulingisa.
• Iqinisekisa ireferensi ye-F-Tile kanye namawashi esistimu ye-PLL Intel FPGA IP ngokusekelwe ekucushweni kwe-IP.

2.2. Izingxenyekazi zekhompuyutha nezidingo zeSoftware
I-Intel isebenzisa izingxenyekazi zekhompuyutha ezilandelayo nesofthiwe ukuhlola i-ex yedizayiniampkusistimu ye-Linux:

• Isoftware ye-Intel Quartus Prime Pro Edition.
• Siemens* EDA QuestaSim, Synopsys* VCS, kanye nesifanisi se-Cadence Xcelium.
• I-Intel Agilex I-series Transceiver-SoC Development Kit (AGIB027R31B1E2VRO) yokuhlola ihadiwe.

2.3. Incazelo Esebenzayo
I-F-tile 25G Ethernet design exampi-le iqukethe okuhlukile okuyinhloko kwe-MAC+PCS+PMA. Imidwebo elandelayo yebhulokhi ibonisa izingxenye zedizayini namasiginali wezinga eliphezulu wokuhluka okuyinhloko kwe-MAC+PCS+PMA ku-F-tile 25G Ethernet design example.
Umfanekiso 5. Block Diagram—F-tile 25G Ethernet Design Example (MAC+PCS+PMA Core Variant)

2.3.1. Izingxenye Zokuklama
Ithebula 4. Izingxenye Zokuklama

Isakhi	Incazelo
I-F-tile 25G Ethernet Intel FPGA IP	Iqukethe i-MAC, PCS, kanye ne-Transceiver PHY, ngokucushwa okulandelayo: • Okuhlukile Okubalulekile: I-MAC+PCS+PMA • Nika amandla ukulawula ukugeleza: Ongakukhetha • Nika amandla ukukhiqizwa kwephutha kwesixhumanisi: Ongakukhetha • Nika amandla ukudlula kwesendlalelo: Ongakukhetha • Nika amandla ukuqoqwa kwezibalo: Ongakukhetha • Nika amandla izibalo zokubala ze-MAC: Ongakukhetha • Imvamisa yewashi lesithenjwa: 156.25 Okokuklama example ngesici se-RS-FEC, ipharamitha eyengeziwe elandelayo iyalungiswa: • Nika amandla i-RS-FEC: Ongakukhetha
Ireferensi ye-F-Tile kanye ne-System PLL Amawashi e-Intel FPGA IP	I-F-Tile Reference kanye ne-System PLL Amawashi izilungiselelo zomhleli wepharamitha ye-Intel FPGA IP zihambisana nezimfuneko ze-F-tile 25G Ethernet Intel FPGA IP. Uma ukhiqiza i-ex designampusebenzisa Khiqiza Isibample Design inkinobho kusihleli sepharamitha ye-IP, i-IP isho ngokuzenzakalelayo. Uma udala owakho umklamo example, kufanele uqinisekise ngokuzenzela le IP futhi uxhume wonke amachweba we-I/O. Ukuze uthole ulwazi mayelana nale IP, bheka I-F-Tile Architecture kanye ne-PMA kanye ne-FEC Direct PHY IP User Guide.
I-logic yeklayenti	Kuqukethe: • Ijeneretha yethrafikhi, ekhiqiza amaphakethe aqhumile kuya kumongo we-25G Ethernet Intel FPGA IP ukuze adluliselwe. • Imonitha yethrafikhi, eqapha amaphakethe aqhumile avela kumongo we-25G Ethernet Intel FPGA IP.
Umthombo kanye ne-Probe	Umthombo namasignali ophenyo, okuhlanganisa isignali yokufaka yokusetha kabusha isistimu, ongayisebenzisela ukulungisa iphutha.

Ulwazi Oluhlobene
I-F-Tile Architecture kanye ne-PMA kanye ne-FEC Direct PHY IP User Guide

Ukulingisa

I-testbench ithumela ithrafikhi nge-IP core, isebenzisa uhlangothi lokudlulisa futhi yamukele uhlangothi lwe-IP core.
2.4.1. I-Testbench
Umfanekiso 6. Vimba Umdwebo we-F-tile 25G Ethernet Intel FPGA IP Design Exampfuthi Simulation Testbench

Ithebula 5. Izingxenye ze-Testbench

Isakhi	Incazelo
Idivayisi ingaphansi kokuhlolwa (DUT)	I-25G Ethernet Intel FPGA IP core.
I-Ethernet Packet Generator ne-Packet Monitor	• Ijeneretha yephakethe ikhiqiza amafreyimu bese idlulisela e-DUT. • I-Packet Monitor iqapha izindlela zedatha ze-TX ne-RX futhi ibonise amafreyimu kukhonsoli yesilingisi.
Ireferensi ye-F-Tile kanye ne-System PLL Amawashi e-Intel FPGA IP	Ikhiqiza amawashi ereferensi e-transceiver nesistimu ye-PLL.

2.4.2. Ukulingisa Idizayini Isibample Components
Ithebula 6. F-tile 25G Ethernet Design Example Testbench File Izincazelo

File Igama	Incazelo
Testbench futhi Simulation Files
basic_avl_tb_top.v	I-testbench yezinga eliphezulu file. I-testbench iqinisa i-DUT, yenza ukucushwa kwe-Avalon® okufakwe kumephu yenkumbulo ezingxenyeni zedizayini kanye nengqondo yeklayenti, futhi ithumela futhi yamukele iphakethe ukuya noma ukusuka ku-25G Ethernet Intel FPGA IP.
Izikripthi ze-Testbench
waqhubeka...

File Igama	Incazelo
run_vsim.do	Isikripthi se-ModelSim sokuqalisa ibhentshi le-test.
run_vcs.sh	Iskripthi se-Synopsy VCS sokuqalisa ibhentshi lokuhlola.
run_xcelium.sh	Iskripthi se-cadence Xcelium sokuqalisa ibhentshi lokuhlola.

2.4.3. Ikesi Lokuhlola
Ikesi lokuhlola lokulingisa lenza izenzo ezilandelayo:

1. Iqinisekisa i-F-tile 25G Ethernet Intel FPGA IP kanye nereferensi ye-F-Tile kanye namawashi esistimu ye-PLL Intel FPGA IP.
2. Ilinda iwashi le-RX kanye nesignali yesimo se-PHY ukuze kulungiswe.
3. Iphrinta isimo se-PHY.
4. Ithumela futhi yamukele idatha eyi-10 evumelekile.
5. Ihlaziya imiphumela. Ibhentshi le-testbench eliphumelelayo libonisa "I-Testbench iqedile.".

Okulandelayo sampokukhiphayo kubonisa ukuqaliswa kokuhlolwa kokulingisa okuyimpumelelo:

Ukuhlanganisa

Landela inqubo ekuhlanganiseni nasekulungiseni i-Design Example in Hardware ukuze ahlanganise futhi alungiselele i-ex yokuklamaample ku-hardware ekhethiwe.
Ungakwazi ukulinganisa ukusetshenziswa kwensiza kanye ne-Fmax usebenzisa i-ex yedizayini yokuhlanganisa kuphelaample. Ungakwazi ukuhlanganisa umklamo wakho usebenzisa umyalo Wokuhlanganisa Wokuqala ku-
Icubungula imenyu kusofthiwe ye-Intel Quartus Prime Pro Edition. Ukuhlanganiswa okuyimpumelelo kudala isifinyezo sombiko wokuhlanganisa.
Ukuze uthole ulwazi olwengeziwe, bheka I-Design Compilation ku-Intel Quartus Prime Pro Edition User Guide.
Ulwazi Oluhlobene

• Ukuhlanganisa kanye nokulungiselela i-Design Example ku-Hardware ekhasini 7
• Ukuhlanganiswa Kwedizayini Ku-Intel Quartus Prime Pro Edition Umhlahlandlela Womsebenzisi

2.6. Hardware Testing
Kumklamo wehadiwe example, ungakwazi ukuhlela i-IP core kumodi yangaphakathi ye-serial loopback futhi ukhiqize ithrafikhi kuhlangothi lokudlulisa olujikela emuva ngohlangothi lokwamukela.
Landela inqubo ekusixhumanisi solwazi esihlobene esinikeziwe ukuze uhlole i-ex designample ku-hardware ekhethiwe.
Ulwazi Oluhlobene
Ihlola i-F-tile 25G Ethernet Intel FPGA IP Hardware Design Example ekhasini 8
Inqubo Yokuhlola
Landela lezi zinyathelo ukuze uhlole i-ex designampku-hardware:

1. Ngaphambi kokuthi uqalise ukuhlolwa kwezingxenyekazi zekhompuyutha zalo mklamo example, kufanele usethe kabusha isistimu:
   a. Chofoza Amathuluzi ➤ Imithombo Engaphakathi Kwesistimu & Ithuluzi Lokuhlela Lokuhlola Lomthombo ozenzakalelayo kanye ne-Probe GUI.
   b. Guqula isignali yokusetha kabusha isistimu (Umthombo[3:0]) ukusuka ku-7 ukuya ku-8 ukuze usebenzise ukusetha kabusha futhi ubuyisele isignali yokusetha kabusha isistimu ku-7 ukuze ukhulule isistimu kusukela kusimo sokusetha kabusha.
   c. Gada amasignali e-Probe futhi uqinisekise ukuthi isimo sivumelekile.
2. Kukhonsoli yesistimu, zulazulela kufolda ye-hwtest bese ugijima umyalo: umthombo main.tcl ukuze ukhethe i-JTAG inkosi. Ngokuzenzakalelayo, u-JTAG master ku-JTAG chain ikhethiwe. Ukuze ukhethe JTAG master kumadivayisi we-Intel Agilex, sebenzisa lo myalo: set_jtag <number of appropriate JTAG inkosi>. Example: setha_jtag 1.
3. Qalisa imiyalo elandelayo kukhonsoli yesistimu ukuze uqale ukuhlolwa kwe-serial loopback:

Ithebula 7. Amapharamitha womyalo

Ipharamitha	Incazelo	Example Ukusetshenziswa
chkphy_isimo	Ibonisa amaza wewashi nesimo sokukhiya se-PHY.	% chkphy_status 0 # Hlola isimo sesixhumanisi 0
chkmac_stats	Ibonisa amanani kuzibali zezibalo ze-MAC.	% chkmac_stats 0 # Ihlola izibalo ze-mac zesixhumanisi 0
sula_zonke_izibalo	Isula izibali zezibalo ezibalulekile ze-IP.	% clear_all_stats 0 # Isula izibalo zokubala zesixhumanisi 0
qala_gen	Iqala ijeneretha yephakethe.	% start_gen 0 # Qala ukukhiqiza iphakethe kusixhumanisi 0
stop_gen	Imisa ijeneretha yephakethe.	% stop_gen 0 # Misa ukukhiqizwa kwephakethe kusixhumanisi 0
vula_kuvuliwe	Ivula i-loopback ye-serial yangaphakathi.	% loop_on 0 # Vula i-loopback yangaphakathi kusixhumanisi esingu-0
luphu_cisha	Ivala i-loopback ye-serial yangaphakathi.	% loop_off 0 # Vala i-loop yangaphakathi kusixhumanisi esingu-0
reg_funda	Ibuyisela inani lerejista eyinhloko ye-IP kokuthi .	% reg_read 0x402 # Funda irejista ye-IP CSR ekhelini elingu-402 lesixhumanisi 0
bhala_bhala	Uyabhala kurejista ye-IP eyinhloko ekhelini .	% reg_write 0x401 0x1 # Bhala 0x1 ku-IP CSR irejista yokubhala ekhelini elingu-401 lesixhumanisi 0

a. Thayipha iluphu_on ukuze uvule imodi ye-serial loopback yangaphakathi.
b. Thayipha chkphy_status ukuhlola isimo se-PHY. Isimo se-TXCLK, i-RXCLK, ne-RX kufanele sibe namanani afanayo aboniswe ngezansi ukuze uthole isixhumanisi esizinzile:

c. Thayipha clear_all_stats ukususa amarejista ezibalo e-TX kanye ne-RX.
d. Thayipha start_gen ukuqala ukukhiqiza iphakethe.
e. Thayipha stop_gen ukumisa ukukhiqizwa kwephakethe.
f. Thayipha chkmac_stats ukufunda izibalo zokubala ze-TX ne-RX. Qiniseka ukuthi:
i. Amafreyimu ephakethe adlulisiwe afana namafreyimu ephakethe atholiwe.
ii. Abekho ozimele bephutha abatholiwe.
g. Thayipha i-loop_off ukuvala i-loopback ye-serial yangaphakathi.
Umfanekiso 7. Sample Test Output—TX kanye ne-RX Statistics Counters

Umlando Wokubuyekeza Idokhumenti we-F-tile 25G Ethernet FPGA IP Design Example Umhlahlandlela Womsebenzisi

Inguqulo Yedokhumenti	Inguqulo ye-Intel Quartus Prime	Inguqulo ye-IP	Izinguquko
2022.10.14	22.3	1.0.0	Ukukhishwa kokuqala.

Inkampani ye-Intel Wonke Amalungelo Agodliwe. I-Intel, ilogo ye-Intel, nezinye izimpawu ze-Intel yizimpawu zokuthengisa ze-Intel Corporation noma izinkampani ezingaphansi kwayo. I-Intel iqinisekisa ukusebenza kwe-FPGA yayo kanye nemikhiqizo yesemiconductor ekucacisweni kwamanje ngokuvumelana newaranti evamile ye-Intel, kodwa igodla ilungelo lokwenza izinguquko kunoma imiphi imikhiqizo namasevisi nganoma yisiphi isikhathi ngaphandle kwesaziso. I-Intel ayithathi mthwalo noma isikweletu esivele ngenxa yesicelo noma ukusetshenziswa kwanoma yiluphi ulwazi, umkhiqizo, noma isevisi echazwe lapha ngaphandle kwalapho okuvunyelwene ngakho ngokubhaliwe yi-Intel. Amakhasimende e-Intel ayelulekwa ukuthi athole inguqulo yakamuva yokucaciswa kwedivayisi ngaphambi kokuthembela kunoma yiluphi ulwazi olushicilelwe nangaphambi kokufaka ama-oda emikhiqizo noma amasevisi. *Amanye amagama namabhrendi angafunwa njengempahla yabanye.
ISO
9001:2015
Ibhalisiwe

I-Online Version
Thumela Impendulo
Inombolo yepholisi: 750200
Inguqulo: 2022.10.14

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intel F-Tile 25G Ethernet FPGA IP Design Example [pdf] Umhlahlandlela Womsebenzisi I-F-Tile 25G Ethernet FPGA IP Design Example, F-Tile 25G, F-Tile 25G Ethernet FPGA, FPGA IP Design Example, IP Design Exampibe, 750200

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