FPGA IP
Design Example User Guide
F-Tile 25G Ethernet Intel®
Fa'afou mo Intel® Quartus®
Prime Design Suite: 22.3
IP Version: 1.0.0
Taiala vave amata
O le F-tile 25G Ethernet Intel FPGA IP mo masini Intel Agilex ™ e maua ai le gafatia e gaosia ai le mamanuamples mo fetuunaiga filifilia.
Ata 1. Fuafuaga Example Fa'aaogaina
Fa'atonuga Fa'atonu
Ata 2. 25G Ethernet Intel FPGA IP Design Example Fa'atonuga Fa'atonu
- Le fa'ata'ita'iga files (testbench mo na o faʻataʻitaʻiga) o loʻo i totonuample_dir>/example_testbench.
- O le tu'ufa'atasi-na'o le mamanu example o loʻo i totonuample_dir>/ compilation_test_design.
- Le faʻatulagaina o meafaigaluega ma suʻega files (le mamanu example in hardware) o loʻo i totonuample_dir>/hardware_test_design.
Laulau 1. Fa'atonuga ma File Fa'amatalaga
| File Igoa | Fa'amatalaga |
| eth_ex_25g.qpf | Poloketi Intel Quartus® Prime file. |
| eth_ex_25g.qsf | Fa'atonuga ole poloketi Intel Quartus Prime file. |
| eth_ex_25g.sdc | Synopsys Design Constraints file. E mafai ona e kopiina ma suia lenei mea file mo lau lava 25GbE Intel FPGA IP mamanu autu. |
| eth_ex_25g.v | Tulaga maualuga Verilog HDL mamanu example file. E fa'aogaina e le mamanu alavai e tasi le Verilog file. |
| masani/ | Fuafuaga meafaigaluega example lagolago files. |
| hwtest/main.tcl | Autu file mo le mauaina o le System Console. |
Fausiaina o le Design Example
Ata 4. Example Design Tab i le F-tile 25G Ethernet Intel FPGA IP Parameter Editor
Mulimuli i laasaga nei e fa'atupuina ai le fa'atulagaina o meafaigaluega e iaiample ma le testbench:
- I le Intel Quartus Prime Pro Edition, kiliki File ➤ New Project Wizard e fatu ai se poloketi fou a Quartus Prime, poʻo File ➤ Tatala Poloketi e tatala ai se poloketi Quartus Prime. E fa'atonu oe e le wizard e fa'ailoa se masini.
- I le IP Catalog, su'e ma filifili 25G Ethernet Intel FPGA IP mo Agilex. Ua aliali mai le fa'amalama New IP Variation.
- Fa'ailoa se igoa pito i luga mo lau fesuiaiga IP ma kiliki le OK. E fa'aopoopo e le fa'atonu fa'amaufa'ailoga le pito i luga .ip file i le galuega o lo'o iai otometi. Afai e uunaia oe e faaopoopo ma le lima le .ip file i le poloketi, kiliki Project ➤ Add/ Remove Files i Poloketi e fa'aopoopo le file.
- I le polokalama Intel Quartus Prime Pro Edition, e tatau ona e filifilia se masini Intel Agilex faapitoa i le fanua Device, pe taofi le masini le lelei o loʻo faʻatulagaina e le Intel Quartus Prime software.
Fa'aaliga: Le mamanu meafaigaluega example overwrites le filifiliga ma le masini i luga o le laupapa sini. E te faʻamaoti le laupapa faʻamoemoe mai le lisi o mamanu example filifiliga i le Example Design tab. - Kiliki OK. E aliali mai le fa'atonu fa'amaufa'ailoga.
- I luga o le IP tab, faʻamaonia le faʻasologa mo lau fesuiaiga autu IP.
- I le Example Design tab, mo Example Lisiina Files, filifili le filifiliga Fa'ata'ita'iga e fa'atupu ai le su'ega, ma filifili le filifiliga Fa'aopoopo e fa'atupuina ai le fa'asologa o meafaigaluegaample. Na'o Verilog HDL files ua gaosia.
Fa'aaliga: E le'o maua se VHDL IP core. Fa'ailoa na'o Verilog HDL, mo lau fa'asologa autu o le IPample. - Mo Atina'e Atina'e Pusa, filifili le Agilex I-series Transceiver-SoC Dev Kit
- Kiliki le Generate Example fa'amau Fa'ailoga. Le Filifili Example fa'amalama o le Design Directory e aliali mai.
- Afai e te mana'o e sui le mamanu example ala lisi po'o le igoa mai fa'aletonu ua fa'aalia (alt_e25_f_0_example_design), suʻesuʻe i le ala fou ma faʻaoga le mamanu fou example igoa fa'atonu (ample_dir>).
- Kiliki OK.
1.2.1. Fuafuaga Example Parameter
Laulau 2. Parameter i le Example Design Tab
| Parameter | Fa'amatalaga |
| Example Lisiina | Avanoa example mamanu mo le faatulagaga IP parameter. Na'o le tasi-alaala example mamanu e lagolagoina mo lenei IP. |
| Example Lisiina Files | O le files e fa'atupuina mo le atina'e eseese. • Fa'ata'ita'iga—fausia mea e mana'omia files mo fa'ata'ita'i le exampmamanu. • Fa'atasi—fausia le fa'atupuina files. Fa'aoga mea nei files e tu'ufa'atasia le mamanu i le Intel Quartus Prime Pro Edition software mo su'ega meafaigaluega ma fa'atino su'esu'ega taimi fa'ata'atia. |
| Fa'atupu File Fa'asologa | Le faatulagaga o le RTL files mo fa'ata'ita'iga—Verilog. |
| Filifili le Komiti Faatino | Meafaigaluega lagolago mo le faʻatinoina o mamanu. A e filifilia se Intel FPGA atinaʻe laupapa, faʻaaoga le masini AGIB027R31B1E2VRO e fai ma Faʻatonuga Faʻatonu mo le mamanu muamuaample tupulaga. Agilex I-series Transceiver-SoC Dev Kit: O lenei filifiliga e mafai ai ona e suʻeina le mamanu example i luga ole pusa atina'e Intel FPGA IP ua filifilia. O lenei filifiliga e otometi lava ona filifilia le Mea Fa'atatau ole AGIB027R31B1E2VRO. Afai o lau iloiloga laupapa ei ai se vasega masini eseese, e mafai ona e suia le masini sini. Leai: O lenei filifiliga e le aofia ai vaega meafaigaluega mo le mamanu example. |
1.3. Fausia Tile Files
O le Lagolago-Logic Generation o se la'asaga muamua-fa'asologa e fa'aaoga e fa'atupu ai fa'ameamea files mana'omia mo fa'ata'ita'iga ma le fa'atulagaina o meafaigaluega. E manaʻomia le gaosiga o tile mo tagata uma
Fa'ata'ita'iga mamanu fa'avae F-tile. E tatau ona e faʻamaeʻaina lenei laasaga aʻo leʻi faia le faʻataʻitaʻiga.
- I le faʻatonuga vave, faʻafeiloaʻi i le compilation_test_design folder i lau example mamanu: cd /compilation_test_design.
- Faʻatonu le poloaiga lenei: quartus_tlg alt_eth_25g
1.4. Fa'ata'ita'iina le F-tile 25G Ethernet Intel FPGA IP Design
Example Testbench
E mafai ona e faʻapipiʻi ma faʻataʻitaʻiina le mamanu e ala i le faʻaogaina o se faʻasologa faʻasologa mai le faʻatonuga faʻatonu.
- I le faʻatonuga vave, sui le suʻega suʻega faʻataʻitaʻiga galue directory: cdample_dir>/ex_25g/sim.
- Faʻataʻitaʻi le faʻataʻitaʻiga o le seti IP: ip-setup-simulation -quartusproject=../../compilation_test_design/alt_eth_25g.qpf
Laulau 3. Laasaga e Fa'ata'ita'i ai le Testbench
| Simulator | Faatonuga |
| VCS* | I le laina faʻatonu, faʻaoga sh run_vcs.sh |
| QuestaSim* | I le laina o le poloaiga, fa'aoga vsim -do run_vsim.do -logfile vsim.log Afai e te manaʻo e faʻataʻitaʻi e aunoa ma le aumaia o le QuestaSim GUI, faʻaoga vsim -c -do run_vsim.do -logfile vsim.log |
| Cadence -Xcelium* | I le laina faʻatonu, faʻaoga sh run_xcelium.sh |
O se fa'ata'ita'iga manuia e fa'ai'u i le fe'au lea:
Fa'atusa na pasia. po'o le Testbench ua mae'a.
A mae'a manuia, e mafai ona e su'esu'eina iuga.
1.5. Tu'ufa'atasia ma Fa'atulaga le Fa'ata'ita'iga Example i Meafaigaluega
O le 25G Ethernet Intel FPGA IP fa'atonu fa'asologa autu e mafai ai e oe ona tu'ufa'atasia ma fa'atulaga le mamanu example i luga o se pusa atinae sini.
Le tuufaatasia ma fetuutuunai se mamanu exampi luga o meafaigaluega, mulimuli i laasaga nei:
- Tatala le polokalama Intel Quartus Prime Pro Edition ma filifili Processing ➤ Start Compilation e tuufaatasia ai le mamanu.
- A maeʻa ona e fatuina se mea SRAM file .sof, mulimuli i laasaga nei e faʻapolokalame le mamanu meafaigaluega exampi luga ole masini Intel Agilex:
a. I luga o le Meafaigaluega lisi, kiliki Programmer.
e. I le Polokalama, kiliki Hardware Setup.
i. Filifili se masini polokalame.
o. Filifili ma faaopoopo le Intel Agilex laupapa i lau Intel Quartus Prime Pro Edition sauniga.
u. Ia mautinoa ua setiina le Faiga i le JTAG.
f. Filifili le masini Intel Agilex ma kiliki le Add Device. Ua fa'aalia e le Polokalama
se ata poloka o fesoʻotaʻiga i le va o masini i luga o lau laupapa.
g. I le laina ma lau .sof, siaki le pusa mo le .sof.
h. Siaki le pusa i le koluma Polokalama/Configure.
i. Kiliki Amata.
1.6. Su'ega ole F-tile 25G Ethernet Intel FPGA IP Hardware Design Example
A uma ona e tuufaatasia le F-tile 25G Ethernet Intel FPGA IP mamanu autu exampma faʻapipiʻi i luga o lau masini Intel Agilex, e mafai ona e faʻaogaina le System Console e faʻapipiʻi ai le IP core.
Ia ki le System Console ma fa'ata'ita'i le mamanu o meafaigaluega fa'aample, mulimuli i laasaga nei:
- I le polokalama Intel Quartus Prime Pro Edition, filifili Tools ➤ System
Debugging Tools ➤ System Console e fa'alauiloa ai le fa'amafanafanaga. - I le Tcl Console pane, ta'i le cd hwtest e sui ai le lisi i / hardware_test_design/hwtest.
- Tu'i puna main.tcl e tatala ai se feso'ota'iga i le JTAG matai.
Mulimuli i le fa'ata'ita'iga o su'ega i le vaega o Su'ega Meafaigaluega o le mamanu fa'atusaample ma mata'ituina iuga o su'ega i le System Console.
F-tile 25G Ethernet Design Example mo Intel Agilex Devices
Le F-tile 25G Ethernet mamanu exampLe fa'aalia se fofo Ethernet mo masini Intel Agilex fa'aaoga le 25G Ethernet Intel FPGA IP autu.
Fausia le mamanu example mai le Example Design tab o le 25G Ethernet Intel FPGA IP editor parameter. E mafai foi ona e filifili e gaosia le mamanu ma pe leai foi
o le Reed-Solomon Forward Error Correction (RS-FEC).
2.1. Vaega
- Lagolagoina le laina Ethernet tasi o loʻo galue ile 25G.
- Fausia mamanu example fa'atasi ai ma le fa'aaliga RS-FEC.
- Tuuina atu suʻega suʻega ma faʻataʻitaʻiga tusitusiga.
- Fa'atonu F-Tile Reference ma System PLL Clock Intel FPGA IP fa'avae ile fa'atulagaina o IP.
2.2. Meafaigaluega ma Polokalama Manaoga
E fa'aogaina e Intel meafaigaluega ma polokalama fa'akomepiuta nei e su'e ai le mamanu example i se faiga Linux:
- Polokalama Intel Quartus Prime Pro Edition.
- Siemens* EDA QuestaSim, Synopsys* VCS, ma Cadence Xcelium simulator.
- Intel Agilex I-series Transceiver-SoC Development Kit (AGIB027R31B1E2VRO) mo su'ega meafaigaluega.
2.3. Fa'amatalaga Fa'atino
Le F-tile 25G Ethernet mamanu exampe aofia ai MAC + PCS + PMA autu eseese. O ata poloka nei o loʻo faʻaalia ai vaega mamanu ma faʻailoga pito i luga o le MAC + PCS + PMA faʻasologa autu i le F-tile 25G Ethernet design example.
Ata 5. Ata poloka—F-tile 25G Ethernet Design Example (MAC+PCS+PMA Core Variant)
2.3.1. Fuafuaga Vaega
Laulau 4. Fuafuaga Vaega
| Vaega | Fa'amatalaga |
| F-tile 25G Ethernet Intel FPGA IP | E aofia ai MAC, PCS, ma Transceiver PHY, faʻatasi ai ma le faʻatulagaga nei: • Eseese Autu: MAC+PCS+PMA • Fa'amalo le pulea o le tafe: Filifili • Fa'aagaaga feso'ota'iga fa'aletonu: Filifili • Fa'ataga le fa'atomuaga passthrough: Filifili • Fa'aagaaga le aoina o fuainumera: Filifili • Fa'amalo fa'amaumauga fa'amaumauga a le MAC: Filifili • Fa'asinoga uati taimi: 156.25 Mo le mamanu exampfa'atasi ai ma le fa'aaliga RS-FEC, o lo'o fa'atulagaina le fa'aopoopo fa'aopoopo nei: • Fa'aagaoi le RS-FEC: Filifili |
| F-Tile Reference ma System PLL Uati Intel FPGA IP | O le F-Tile Reference ma le System PLL Clocks Intel FPGA IP fa'atonu fa'atonu fa'atonu e fetaui ma mana'oga o le F-tile 25G Ethernet Intel FPGA IP. Afai e te gaosia le mamanu example faaaogaina Fausia Example Lisiina fa'amau i le fa'atonu fa'amaufa'ailoga IP, otometi ona fa'atosina le IP. Afai e te fatuina lau lava mamanu exampO lea, e tatau ona e fa'aogaina ma le lima lenei IP ma fa'afeso'ota'i uma I/O ports. Mo faʻamatalaga e uiga i lenei IP, tagai ile F-Tile Architecture ma PMA ma FEC Direct PHY IP User Guide. |
| Fa'atatau ole tagata fa'atau | E aofia ai: • Ta'avale ta'avale, lea e fa'atupuina pepa pa'u i le 25G Ethernet Intel FPGA IP core mo fa'asalalauga. • Mata'itū ta'avale, lea e mata'ituina ai pusa pa'u e sau mai le 25G Ethernet Intel FPGA IP core. |
| Puna ma Su'esu'ega | Fa'ailoga puna ma su'esu'ega, e aofia ai fa'ailoga fa'aoga fa'aoga, lea e mafai ona e fa'aogaina mo le fa'apipi'iina. |
Fa'amatalaga Fa'atatau
F-Tile Architecture ma PMA ma FEC Direct PHY IP User Guide
Fa'ata'oto
O le testbench e tuʻuina atu fefaʻatauaiga e ala i le IP core, faʻaogaina le itu faʻasalalau ma maua le itu o le IP core.
2.4.1. Su'ega Su'ega
Ata 6. Fa'ailoga poloka o le F-tile 25G Ethernet Intel FPGA IP Design Example Simulation Testbench
Laulau 5. Vaega Su'esu'e
| Vaega | Fa'amatalaga |
| Meafaigaluega o lo'o su'eina (DUT) | Le 25G Ethernet Intel FPGA IP autu. |
| Ethernet Packet Generator ma Packet Monitor | • E fa'atupuina fa'avaa ma tu'u atu i le DUT. • Mataituina le Packet Monitors TX ma RX datapaths ma faʻaalia faʻavaa i le faʻamafanafanaga simulator. |
| F-Tile Reference ma System PLL Uati Intel FPGA IP | Fausia le transceiver ma faiga PLL fa'asino uati. |
2.4.2. Fa'atusa Fa'ata'ita'iga Example Vaega
Laulau 6. F-tile 25G Ethernet Design Example Testbench File Fa'amatalaga
| File Igoa | Fa'amatalaga |
| Testbench ma Simulation Files | |
| faavae_avl_tb_top.v | Tulaga maualuga su'ega file. O le su'ega su'esu'e e fa'atino vave le DUT, fa'atino Avalon® fa'afanua fa'amaufa'ailoga i luga o vaega mamanu ma manatu o tagata fa'atau, ma lafo ma maua le pepa i po'o mai le 25G Ethernet Intel FPGA IP. |
| Testbench Scripts | |
| faaauau… | |
| File Igoa | Fa'amatalaga |
| run_vsim.do | O le ModelSim script e faʻatautaia le suʻega suʻega. |
| run_vcs.sh | Le Synopsys VCS script e faʻatautaia le suʻega suʻega. |
| run_xcelium.sh | Le tusi Cadence Xcelium e faʻatautaia le suʻega suʻega. |
2.4.3. Su'ega Su'ega
O le fa'ata'ita'iga fa'ata'ita'iga fa'ata'ita'iga e fa'atino gaioiga nei:
- Fa'atupuina F-tile 25G Ethernet Intel FPGA IP ma F-Tile Reference ma System PLL Uati Intel FPGA IP.
- Fa'atali mo le uati RX ma le fa'ailoga tulaga PHY e fa'amautu.
- Lolomi tulaga PHY.
- Auina ma maua 10 faʻamatalaga aoga.
- Iloilo taunuuga. O le su'ega manuia o lo'o fa'aalia ai le "Fa'auma le su'ega.".
O sampO le fa'aaliga o lo'o fa'aalia ai le manuia o le su'ega fa'ata'ita'iga:
Tuufaatasiga
Mulimuli i le faʻagasologa i le Tuʻufaʻatasia ma le Faʻatulagaina o le Design Example i Meafaigaluega e tuufaatasia ma configure le mamanu example i meafaigaluega ua filifilia.
E mafai ona e fa'atatauina le fa'aogaina o puna'oa ma le Fmax i le fa'aogaina o le fa'atulagaina-na'o le fa'ata'ita'igaample. E mafai ona e tu'ufa'atasia lau mamanu e fa'aaoga ai le fa'atonuga Amata Compilation i le
Fa'asologa o lisi i le polokalama Intel Quartus Prime Pro Edition. O se tuufaatasiga manuia e maua ai le aotelega o lipoti tuufaatasia.
Mo nisi fa'amatalaga, tagai ile Design Compilation ile Intel Quartus Prime Pro Edition User Guide.
Fa'amatalaga Fa'atatau
- Tu'ufa'atasia ma Fa'atulaga le Fa'ata'ita'iga Example i Meafaigaluega i le itulau 7
- Fuafuaga Tu'ufa'atasi I le Intel Quartus Prime Pro Edition Ta'iala mo Tagata Fa'aoga
2.6. Su'ega Meafaigaluega
I le mamanu meafaigaluega example, e mafai ona e fa'apolokalameina le IP autu i totonu o le fa'asologa fa'asolosolo fa'asolo i totonu ma fa'atupuina feoaiga i luga o le itu fa'asalalau lea e fa'asolo i tua i le itu e maua.
Mulimuli i le fa'agasologa ile feso'ota'iga fa'amatalaga tu'ufa'atasia e fa'ata'ita'i ai le fa'ata'ita'igaample i meafaigaluega ua filifilia.
Fa'amatalaga Fa'atatau
Su'ega ole F-tile 25G Ethernet Intel FPGA IP Hardware Design Exampi le itulau e 8
2.6.1. Taualumaga o Suʻega
Mulimuli i laasaga nei e su'e ai le mamanu exampi meafaigaluega:
- Ae e te le'i faia le su'ega meafaigaluega mo lenei mamanu example, e tatau ona e toe setiina le faiga:
a. Kiliki Meafaigaluega ➤ In-System Sources & Probes Editor tool mo le faaletonu Puna ma le GUI Su'esu'e.
e. Kiliki le faʻailoga toe setiina o le system (Source[3:0]) mai le 7 i le 8 e faʻaoga ai le toe setiina ma toe faʻafoʻi le faʻailoga toe faʻaleleia i le 7 e faʻasaʻo ai le faiga mai le tulaga toe faʻaleleia.
i. Mataʻituina faailoilo Suʻesuʻe ma faʻamautinoa e aoga le tulaga. - I totonu o le faʻamafanafanaga, faʻafeiloaʻi i le faila hwtest ma faʻatautaia le poloaiga: source main.tcl e filifili ai se JTAG matai. Ona o le faaletonu, o le muamua JTAG matai i luga o le JTAG filifili filifili. Ina ia filifilia le JTAG matai mo masini Intel Agilex, faʻatautaia lenei poloaiga: set_jtag <number of appropriate JTAG matai>. Example: seti_jtag 1.
- Fa'ata'ita'i tulafono nei i le fa'amafanafanaga e amata ai le su'ega fa'asolosolo fa'asolosolo:
Laulau 7. Fa'atonu Fa'atonu
| Parameter | Fa'amatalaga | Example Fa'aaogaina |
| chkphy_status | Fa'aali atu alaleo o le uati ma le tulaga loka PHY. | % chkphy_status 0 # Siaki le tulaga o le so'oga 0 |
| chkmac_stats | Fa'aali atu tau i fa'amaumauga fa'amaumauga a le MAC. | % chkmac_stats 0 # Siaki fa'amaumauga mac statistics o feso'ota'iga 0 |
| clear_all_stats | Fa'amama fa'amaumauga autu o fuainumera IP. | % clear_all_stats 0 # Fa'amama fa'amaumauga fa'amaumauga o feso'ota'iga 0 |
| amata_gen | Amata le fa'aputu fa'aputu. | % start_gen 0 # Amata le fa'atupuina o pusa ile so'oga 0 |
| taofi_gen | Taofi le gaosiga o pusa. | % stop_gen 0 # Taofi le gaosiga o pusa i luga ole so'oga 0 |
| loop_on | Fa'aola fa'asolo i tua fa'asologa i totonu. | %. |
| tapuni_off | Tape le fa'asologa fa'asologa i totonu. | % loop_off 0 # Tape le fa'aoga i tua ile so'oga 0 |
| reg_read | Fa'afo'i le tau o le resitala autu o le IP ile . | % reg_read 0x402 # Faitau le resitala IP CSR ile tuatusi 402 ole sootaga 0 |
| reg_tusi | Tusitala i le tusi resitala autu IP ile tuatusi . | % reg_write 0x401 0x1 # Tusi le 0x1 i le IP CSR scratch register ile tuatusi 401 ole so'oga 0 |
a. Type loop_on e fa'aola le fa'aoga fa'asologa fa'asologa i totonu.
e. Tusa chkphy_status e siaki le tulaga o le PHY. O le TXCLK, RXCLK, ma le RX tulaga e tatau ona tutusa le tau o loʻo faʻaalia i lalo mo se soʻotaga mautu:
i. Fa'aigoa clear_all_stats e fa'amama TX ma RX statistics registers.
o. Tu'aiga start_gen e amata ai le gaosiga o pusa.
u. Ituaiga stop_gen e taofi le gaosiga o pusa.
f. Tusa chkmac_stats e faitau le TX ma RX fuainumera fuainumera. Ia mautinoa e:
i. O fa'avaa pepa fa'asalalau e fetaui ma fa'avaa pepa na maua.
ii. E leai ni fa'avaa sese e maua.
g. Tu'aiga loop_off e tape le fa'asologa fa'asologa i totonu.
Ata 7. Sample Fuafuaga o Su'ega—TX ma RX Fa'amaumauga Fa'amaumauga
 |
 |
Tala Fa'asolopito o Fa'amatalaga mo F-tile 25G Ethernet FPGA IP Design Example User Guide
| Fa'amatalaga Fa'amaumauga | Intel Quartus Prime Version | IP Version | Suiga |
| 2022.10.14 | 22.3 | 1.0.0 | Fa'asalalauga muamua. |
Intel Corporation. Ua taofia aia tatau uma. Intel, le Intel logo, ma isi fa'ailoga Intel o fa'ailoga fa'ailoga a le Intel Corporation po'o ona lala. E fa'amaonia e Intel le fa'atinoina o ana oloa FPGA ma semiconductor i fa'amatalaga o lo'o iai nei e tusa ai ma le fa'atonuga masani a Intel, ae fa'asaoina le aia tatau e fai ai suiga i so'o se oloa ma auaunaga i so'o se taimi e aunoa ma se fa'aaliga. E leai se tiute po'o se noataga e afua mai i le talosaga po'o le fa'aogaina o so'o se fa'amatalaga, oloa, po'o se auaunaga o lo'o fa'amatalaina i i'i se'i vagana ua malilie i ai i se faiga tusitusia e Intel. Ua fautuaina tagata fa'atau Intel ina ia maua le fa'amatalaga lata mai o fa'amatalaga masini a'o le'i fa'alagolago i so'o se fa'amatalaga fa'asalalau ma a'o le'i tu'uina atu oka mo oloa po'o tautua. *O isi igoa ma fa'ailoga e mafai ona ta'ua o se meatotino a isi.
ISO
9001:2015
Resitala
Faʻasinomaga Faʻainitaneti
Lauina Manatu
ID: 750200
Fa'aliliuga: 2022.10.14
Pepa / Punaoa
 |
intel F-Tile 25G Ethernet FPGA IP Design Example [pdf] Taiala mo Tagata Fa'aoga F-Tile 25G Ethernet FPGA IP Design Example, F-Tile 25G, F-Tile 25G Ethernet FPGA, FPGA IP Design Example, IP Design Example, 750200 |
