Xilinx AXI4-Kuyerera Yakabatanidzwa Logic Analyzer Guide

Iyo Yakabatanidzwa Logic Analyzer (ILA) ine AXI4-Stream Interface musimboti ndeye customizable logic analyzer IP inogona kushandiswa kutarisa masaini emukati uye kupindirana kwedhizaini. Iyo ILA musimboti inosanganisira akawanda epamberi maficha emazuva ano logic analyzer, kusanganisira boolean trigger equations uye edge shanduko inokonzeresa. Iyo musimboti inopawo interface debugging uye yekutarisa kugona pamwe neprotocol yekutarisa memory-mapped AXI uye AXI4-Stream. Nekuti iyo ILA musimboti inopindirana kune dhizaini iri kutariswa, zvese zvipingaidzo zvewachi zvinoiswa padhizaini yako zvinoiswawo kune zvikamu zveILA musimboti. Kugadzirisa zvinopindirana mukati medhizaini, ILA IP inoda kuwedzerwa kune dhizaini dhizaini muVivado® IP musanganisi. Saizvozvo, AXI4/AXI4-Stream protocol yekutarisa sarudzo inogona kugoneswa ILA IP mune IP yekubatanidza. Kutyorwa kweProtocol kunogona kuratidzwa mune waveform viewer yeVivado logic analyzer.

Features

Mushandisi-inosarudzwa nhamba yeprobe ports uye probe wide.

Mushandisi-anosarudzwa ekuchengetedza zvibodzwa senge block RAM uye UltraRAM
Multiple probe ports inogona kusanganiswa kuita imwechete trigger mamiriro.

Mushandisi-inosarudzwa AXI inotsvedza kugadzirisa AXI inopindirana mudhizaini.
Configurable sarudzo dzeAXI interfaces dzinosanganisira interface mhando uye trace sample deep.

Data uye trigger pfuma nokuda probes.
Nhamba yekuenzanisa uye hupamhi kune imwe neimwe probe uye imwe neimwe ports mukati meinterfaces.

Input/output cross-triggering interfaces.
Configurable pipelining yekupinza probes.

AXI4-MM uye AXI4-Stream protocol kutarisa.

Kuti uwane rumwe ruzivo nezve ILA musimboti, ona Vivado Dhizaini Suite Mushandisi Yekushandisa: Kuronga uye Kugadzirisa (UG908).

IP Chokwadi

LogiCORE™ IP Chokwadi Tafura
Core Specifics
Inotsigirwa Mudziyo Mhuri1	Versal™ ACAP
Inotsigirwa User Interfaces	IEEE Chiyero 1149.1 - JTAG
Yakapihwa neCore
Design Files	RTL
Example Dhizaini	Verilog
Test Bench	Not Provided
Zvipingamupinyi File	Xilinx® Dhizaini Constraints (XDC)
Simulation Model	Not Provided
Inotsigirwa S/W Driver	N/A
Yakaedzwa Dhizaini Inoyerera2
Design Entry	Vivado® Dhizaini Suite
Simulation	Kune ma simulators anotsigirwa, ona iyo Xilinx Dhizaini Zvishandiso: Release Notes Guide.
Synthesis	Vivado Synthesis
Support
Yese Vivado IP Shandura Logs	Master Vivado IP Shandura Logs: 72775
Xilinx Tsigiro web peji
Notes: 1. Kuti uwane runyoro rwakakwana rwezvishandiso zvinotsigirwa, ona Vivado® IP catalog. 2. Nokuda kweshanduro dzinotsigirwa dzezvishandiso, ona Xilinx Dhizaini Zvishandiso: Release Notes Guide.

Overview

Kufambisa Zviri mukati neKugadzira Maitiro
Xilinx® zvinyorwa zvakarongeka zvakatenderedza seti yeyakajairwa dhizaini maitiro ekukubatsira iwe kuwana yakakodzera zvemukati basa rako razvino rekusimudzira. Gwaro iri rinobata zvinotevera maitiro ekugadzira:

Hardware, IP, uye Platform Development: Kugadzira iyo PL IP inovharira papuratifomu yehardware, kugadzira PL kernels, subsystem inoshanda simulation, uye kuongorora iyo Vivado® nguva, kushandisa zviwanikwa, uye kuvhara simba. Zvakare zvinosanganisira kugadzira iyo hardware chikuva chekubatanidza system. Misoro iri mugwaro rino inoshanda kune iyi dhizaini maitiro inosanganisira:
Port Rondedzero

Kuvhara uye Resets
Kugadzirisa uye Kugadzira iyo Core

Core Overview
Zviratidzo uye zvinopindirana muFPGA dhizaini yakabatana neILA probe uye slot yekupinda. Aya masaini uye maratidziro, akasungirirwa kune probe uye slot yekupinda zvakateerana, ndeye sampinotungamirwa nekumhanya kwekugadzira uye kuchengetwa uchishandisa pa-chip block RAM. Zviratidzo uye zvinopindirana muVersal ™ ACAP dhizaini yakabatana neILA probe uye slot yekupinda. Aya masaini akasungirirwa uye maratidziro ari sampinotungamirwa pakumhanya kwekugadzira uchishandisa iyo yakakosha wachi yekuisa uye yakachengetwa mu-chip block RAM ndangariro. The core parameters inotsanangura zvinotevera:

Nhamba yeprobes (kusvika pa512) uye probe hupamhi (1 kusvika 1024).

A akati wandei slots uye interface sarudzo.
Trace sample deep.

Dhata uye / kana kukonzeresa pfuma ye probes.
Nhamba yekuenzanisa kune imwe neimwe probe.

Kukurukurirana neILA musimboti kunoitwa uchishandisa muenzaniso weAXI Debug Hub inobatana neKudzora, Interface, uye Kugadzirisa System (CIPS) IP musimboti.

Mushure mekunge dhizaini yaiswa muVersal ACAP, shandisa Vivado® logic analyzer software kumisikidza chiitiko chinokonzeresa cheyero yeILA. Mushure mekunge trigger yaitika, sample buffer inozadzwa uye yakaiswa muVivado logic analyzer. Unogona view iyi data uchishandisa waveform hwindo. Iyo probe sample uye trigger mashandiro anoitwa munzvimbo inogoneka logic. Pa-chip block RAM kana UltraRAM ndangariro zvichibva pane yekuchengetera tarisiro yawakasarudza panguva yekugadzirisa iyo inochengeta iyo data kusvika yaiswa nesoftware. Hapana kupinza kwemushandisi kana kuburitsa kunodiwa kukonzeresa zviitiko, kutora data, kana kutaurirana neILA musimboti. ILA musimboti inokwanisa kutarisisa masaini-level masiginecha, inogona kuendesa transaction-level ruzivo senge yakasarudzika kutengeserana kweAXI4 interfaces.

ILA Probe Trigger Comparator
Imwe neimwe probe input yakabatana kune trigger comparator inokwanisa kuita mashandiro akasiyana. Panguva yekumhanya muenzanisi anogona kusetwa kuita = kana != kuenzanisa. Izvi zvinosanganisira kuenzanisa mazinga mapatani, akadai seX0XX101. Inosanganisirawo kuona kuchinjika kwakadai sekukwira kumucheto (R), kudonha kumucheto (F), kungave kumucheto (B), kana kusachinja (N). Mufananisi wekukonzeresa anogona kuita kuenzanisa kwakaoma, kusanganisira >, <, ≥, uye ≤.

ZVINOKOSHA! Muenzanisi wakaiswa panguva yekumhanya kuburikidza neVivado® logic analyzer.

Iyo Trigger Condition
Iyo trigger mamiriro ndiwo mhedzisiro yeBoolean "AND" kana "OR" kuverenga kweimwe neimwe yeILA probe trigger comparator mhinduro. Uchishandisa iyo Vivado® logic analyzer, iwe unosarudza kana "AND" kuongorora kukonzeresa vaenzanisi probes kana "OR" ivo. Iyo "AND" yekumisikidza inokonzeresa chiitiko kana ese eILA probe kuenzanisa agutsikana. Iyo "OR" yekumisikidza inokonzeresa chiitiko chinokonzeresa kana chero yeILA probe yekuenzanisa yagutsikana. Iyo trigger mamiriro ndiyo inokonzeresa chiitiko chinoshandiswa kune iyo ILA trace kuyerwa.

Applications

Iyo ILA musimboti wakagadzirwa kuti ushandiswe muchishandiso chinoda kusimbiswa kana kugadzirisa uchishandisa Vivado®. Iyi inotevera nhamba inoratidza CIPS IP musimboti inonyora uye inoverenga kubva kuAXI block RAM controller kuburikidza neAXI Network paChip (NoC). Iyo ILA musimboti yakabatana net interface pakati peAXI NoC neAXI block RAM controller yekutarisa iyo AXI4 transaction mune Hardware maneja.

Rezinesi uye Kuodha
Iyi Xilinx® LogiCORE™ IP module inopihwa pasina muripo wekuwedzera neXilinx Vivado® Dhizaini Suite pasi pemitemo yeXilinx End User License.
Cherechedza: Kuti uone kuti unoda rezinesi, tarisa iyo License column yeIP Catalog. Inosanganisirwa zvinoreva kuti rezinesi rinosanganisirwa neVivado® Design Suite; Kutenga zvinoreva kuti unofanirwa kutenga rezinesi kuti ushandise musimboti. Ruzivo nezve mamwe Xilinx® LogiCORE™ IP modules inowanikwa pane Xilinx Intellectual Property peji. Kuti uwane ruzivo nezve mitengo uye kuwanikwa kweimwe Xilinx LogiCORE IP modules uye maturusi, bata mumiriri wako wepanzvimbo weXilinx.

Chigadzirwa Specification

Port Rondedzero
Matafura anotevera anopa ruzivo nezve ILA ports uye paramita.
ILA Ports

Tafura 1: ILA Ports
Port Name	I/O	Tsanangudzo
clk	I	Dhizaini wachi inovhara zvese zvinokonzeresa uye kuchengetedza logic.
probe [ – 1:0]	I	Probe port input. Iyo probe port nhamba iri pakati pe0 kusvika 511. Iyo probe port hupamhi (inoratidzwa na ) iri pakati pe1 kusvika 1024. Iwe unofanirwa kuzivisa iyi chiteshi sevector. Kune 1-bit port, shandisa probe [0:0].
trig_out	O	Iyo trig_out port inogona kugadzirwa kubva kune trigger mamiriro kana kubva kunze trig_in port. Pane inomhanya nguva yekudzora kubva kuLogic Analyzer kushandura pakati pe trigger mamiriro uye trig_in kutyaira trig_out.
trig_in	I	Input trigger port inoshandiswa mu process based system ye Embedded Cross Trigger. Inogona kubatana kune imwe ILA kugadzira cascading Trigger.
slot_ _	I	Slot interface. Mhando ye interface inogadzirwa zvine simba zvichibva pane slot_ _ interface rudzi parameter. Iwo ega ega madoko mukati meiyo interfaces anowanikwa kuti atarise mune Hardware maneja.
trig_out_ack	I	Mvumo ye trig_out.
trig_in_ack	O	Kubvuma kuti trig_in.
reseten	I	ILA Input Type kana yaiswa ku 'Interface Monitor', chiteshi ichi chinofanirwa kunge chiri chiratidziro chakafanana cheseta zvakare chinopindirana kune dhizaini yedhizaini yakasungirirwa kune Slot_ _ ports yeILA musimboti.
S_AXIS	I/O	Optional port. Inoshandiswa kubatanidza nemaoko neAXI Debug Hub musimboti kana 'Enable AXI4- Stream Interface yeManul Connection kuAXI Debug Hub' yasarudzwa muAdvanced Options.
M_AXIS	I/O	Optional port. Inoshandiswa kubatanidza nemaoko neAXI Debug Hub core apo 'Enable AXI4- Kuyerera Interface yeManual Connection kuAXI Debug Hub' inosarudzwa mu 'Advanced Options'.

Tafura 1: ILA Ports (enderera)
Port Name	I/O	Tsanangudzo
aresetn	I	Optional port. Inoshandiswa kubatanidza nemaoko neAXI Debug Hub core apo 'Enable AXI4- Kuyerera Interface yeManual Connection kuAXI Debug Hub' inosarudzwa mu 'Advanced Options'. Chiteshi ichi chinofanira kuenderana nereset port yeAXI Debug Hub.
aclk	I	Optional port. Inoshandiswa kubatanidza nemaoko neAXI Debug Hub core apo 'Enable AXI4- Kuyerera Interface yeManual Connection kuAXI Debug Hub' inosarudzwa mu 'Advanced Options'. Chiteshi ichi chinofanira kuenderana newachi port yeAXI Debug Hub.

ILA Parameters

Tafura 2: ILA Parameters
Parameter	Zvinobvumirwa Values	Default Values	Tsanangudzo
Chikamu_Zita	Tambo ine A–Z, 0–9, uye _ (pasi pasi)	ila_0	Zita rechikamu chakasimbiswa.
C_NUM_OF_PROBES	1–512	1	Nhamba yeILA probe ports.
C_MEMORY_TYPE	0, 1	0	Chengetedzo chinangwa che data rakatorwa. 0 inoenderana nekuvhara RAM uye 1 inoenderana ne UltraRAM.
C_DATA_DEPTH	1,024, 2,048, 4,096, 8,192, 16,384, 32,768, 65,536, 131,072	1,024	Probe kuchengetedza buffer kudzika. Iyi nhamba inomiririra nhamba yepamusoro yesampizvo zvinogona kuchengetwa panguva yekumhanya kune yega yega yekuongorora.
C_PROBE _WIDTH	1–1024	1	Kufara kwechiteshi chekuongorora . Kupi ndiyo probe port ine kukosha kubva pa0 kusvika pa1,023.
C_TRIGOUT_EN	Chokwadi/Nhema	NHEMA	Inogonesa trig out kushanda. Ports trig_out uye trig_out_ack inoshandiswa.
C_TRIGIN_EN	Chokwadi/Nhema	NHEMA	Inogonesa trig mukushanda. Ports trig_in uye trig_in_ack inoshandiswa.
C_INPUT_PIPE_STAGES	0–6	0	Wedzera mamwe maflops kune probe ports. Imwe parameter inoshanda kune ese eprobe ports.
ALL_PROBE_SAME_MU	Chokwadi/Nhema	TRUE	Izvi zvinomanikidza zvakafanana kuenzanisa kukosha kwezvikamu (match units) kune ese maprobes.
C_PROBE _MU_CNT	1–16	1	Nhamba yeEnzanisa Kukosha (Match) mayunitsi paprobe. Izvi zvinoshanda chete kana ALL_PROBE_SAME_MU iri FALSE.
C_PROBE _TYPE	DATA uye TRIGGER, TRIGGER, DATA	DATA uye TRIGGER	Kusarudza probe yakasarudzwa yekutsanangura mamiriro ekutanga kana yechinangwa chekuchengetedza data kana zvese zviri zviviri.
C_ADV_TRIGGER	Chokwadi/Nhema	NHEMA	Inogonesa sarudzo yekusimudzira. Izvi zvinogonesa trigger state muchina uye iwe unogona kunyora yako wega trigger kutevedzana muVivado Logic Analyzer.

Tafura 2: ILA Parameters (enderera)
Parameter	Zvinobvumirwa Values	Default Values	Tsanangudzo
C_NUM_MONITOR_SLOTS	1-11	1	Nhamba yeInterface Slots.
Notes: 1. Nhamba yakawanda yekuenzanisa kukosha (match) zvikwata zvinogumira ku1,024. Kune yekutanga trigger (C_ADV_TRIGGER = FALSE), imwe neimwe probe ine imwe yekuenzanisa kukosha kweyuniti (semushanduro yekutanga). Asi kune yekutanga trigger sarudzo (C_ADV_TRIGGER = TRUE), izvi zvinoreva kuti maprobe ega ega anogona kuramba aine sarudzo yenhamba yekuenzanisa mayuniti kubva kune imwe kusvika ina. Asi ese anoenzanisa kukosha mayuniti haafanire kudarika kupfuura 1,024. Izvi zvinoreva, kana iwe uchida mana ekuenzanisa mayunitsi paprobe ipapo unotenderwa kushandisa 256 probes chete.

Kugadzira neCore

Ichi chikamu chinosanganisira nhungamiro uye rumwe ruzivo rwekufambisa kugadzira nepakati.

Kuvhara
Iyo clk yekupinda port ndiyo wachi inoshandiswa neILA musimboti kunyoresa maitiro ekuongorora. Kuti uwane mibairo yakanakisa, inofanirwa kunge iri chiratidzo chewachi imwechete inowirirana kune dhizaini yedhizaini iyo yakasungirirwa kune probe ports yeILA musimboti. Kana uchibatanidza nemaoko neAXI Debug Hub, iyo aclk siginecha inofanirwa kuenderana neAXI Debug Hub wachi yekuisa port.

Vanotsvaga
Paunoseta ILA Input Type kuInterface Monitor, reset port inofanirwa kunge yakafanana reset chiratidzo chinowirirana kune dhizaini dhizaini iyo interface yakanamatira
slot_ _ chiteshi cheiyo ILA musimboti. Kubatanidza nemaoko neAXI Debug Hub core, chiteshi chiripo chinofanira kuenderana nechiteshi chekugadzirisa che AXI Debug Hub core.

Dhizaini Inoyerera Matanho
Ichi chikamu chinotsanangura kugadzirisa uye kugadzira musimboti, kumanikidza musimboti, uye simulation, synthesis, uye kuita matanho akanangana neiyi IP musimboti. Rumwe ruzivo rwakadzama nezve yakajairwa Vivado® dhizaini inoyerera uye iyo IP musanganisi inogona kuwanikwa mune inotevera Vivado Design Suite mushandisi madhairekitori:

Vivado Dhizaini Suite Mushandisi Yekushandisa: Kugadzira IP Subsystems uchishandisa IP Integrator (UG994)
Vivado Dhizaini Suite Mushandisi Yekushandisa: Kugadzira neIP (UG896)
Vivado Dhizaini Suite Mushandisi Yekushandisa: Kutanga (UG910)
Vivado Dhizaini Suite Yemushandisi Yekushandisa: Logic Simulation (UG900)

Kugadzirisa uye Kugadzira iyo Core

Ichi chikamu chinosanganisira ruzivo rwekushandisa Xilinx® zvishandiso kugadzirisa uye kugadzira iyo yakakosha muVivado® Design Suite. Kana iwe uri kugadzirisa uye kugadzira iyo musimboti muVivado IP musanganisi, ona Vivado Dhizaini Suite Mushandisi Yekushandisa: Kugadzira IP Subsystems uchishandisa IP Integrator (UG994) yeruzivo rwakadzama. IP musanganisi anogona kuverengera otomatiki mamwe maitiro ekugadzirisa kana achisimbisa kana kugadzira dhizaini. Kuti uone kana hunhu huchichinja, ona tsananguro yeparameter muchitsauko chino. To view iyo parameter kukosha, mhanyisa iyo validate_bd_design command muTcl console. Iwe unogona kugadzirisa iyo IP kuti ishandiswe mudhizaini yako nekutsanangura kukosha kweakasiyana ma paramita ane chekuita neiyo IP core uchishandisa anotevera matanho:

Sarudza iyo IP kubva kuI IP catalog.
Tinya kaviri IP yakasarudzwa kana sarudza iyo Gadzirisa IP kuraira kubva paturusi bar kana kudzvanya-kurudyi menyu.

Kuti uwane rumwe ruzivo, ona Vivado Dhizaini Suite Mushandisi Yekushandisa: Kugadzira neIP (UG896) uye Vivado Dhizaini Suite Mushandisi Yekushandisa: Kutanga (UG910). Nhamba dziri muchitsauko chino mifananidzo yeVivado IDE. Mamiriro ari kuratidzwa pano anogona kusiyana neshanduro yazvino.

Kuti uwane iyo core, ita zvinotevera:

Vhura chirongwa nekusarudza File wobva wavhura Project kana kugadzira chirongwa chitsva nekusarudza File ipapo Chirongwa Chitsva muVivado.
Vhura iyo IP catalog uye famba kune chero ye taxonomies.

Tinya kaviri ILA kuunza iro repakati zita Vivado IDE.

General Options Panel
Iyi inotevera nhamba inoratidza iyo General Sarudzo tebhu muNative kuseta iyo inokutendera kuti utaure sarudzo:

Iyi inotevera nhamba inoratidza iyo General Sarudzo tebhu mune iyo AXI yekumisikidza iyo inokutendera kuti utaure sarudzo:

Zita rechikamu: Shandisa iyi ndima yemavara kupa rakasiyana module zita reiyo ILA musimboti.

ILA Input Type: Iyi sarudzo inotsanangura kuti ndeupi rudzi rwechiratidziro kana chiratidzo ILA chinofanira kunge chiri kugadzirisa. Parizvino, kukosha kweiyi parameter "Native Probes", "Interface Monitor" uye "Mixed."
Nhamba yeProbes: Shandisa iyi ndima yemavara kusarudza nhamba yeprobe ports pane iyo ILA musimboti. Rudzi rwakakodzera runoshandiswa muVivado® IDE ndeye 1 kusvika 64. Kana iwe uchida zvinopfuura 64 probe ports, unoda kushandisa Tcl command flow flow kuti uite ILA core.
Nhamba yeInterface Slots (inongowanikwa muInterface Monitor mhando uye Yakasanganiswa mhando): Iyi sarudzo inobvumidza iwe kusarudza nhamba yeAXI interface slots inoda kubatana neILA.

Nhamba imwechete yeVaenzanisi kune Yese Probe Ports: Huwandu hwevaenzanisi pane imwe probe inogona kugadzirwa pane ino panhi. Nhamba imwechete yekuenzanisa kune ese probes inogona kugoneswa nekusarudza.

Probe Port Panels
Iyi inotevera nhamba inoratidza iyo Probe Ports tebhu iyo inokutendera kuti utaure marongero:

Probe Port Panel: Hupamhi hweProbe Port yega yega inogona kugadzirwa muProbe Port Panels. Imwe neimwe Probe Port Panel ine madoko manomwe.
Probe Width: Hupamhi hweProbe Port yega yega inogona kutaurwa. Chiyero chakakodzera ndeche 1 kusvika 1024.
Nhamba Yevaenzanisi: Iyi sarudzo inogoneswa chete kana "Same Nhamba Yevaenzanisi kune Yese Probe Ports" sarudzo yakadzimwa. Muenzanisi weprobe yega yega mune renji 1 kusvika 16 inogona kusetwa.

Dhata uye/kana Trigger: Probe type yeprobe yega yega inogona kusetwa uchishandisa iyi sarudzo. Sarudzo dzinoshanda ndedzeDATA_uye_TRIGGER, DATA neTRIGGER.
Comparator Sarudzo: Mhando yekushanda kana kuenzanisa kune yega yega probe inogona kusetwa uchishandisa iyi sarudzo.

Interface Options
Iyi inotevera nhamba inoratidza iyo Interface Sarudzo tebhu kana Interface Monitor kana Musanganiswa mhando yasarudzirwa ILA mhando yekuisa:

Interface Type: Mutengesi, Raibhurari, Zita, uye Shanduro (VLNV) yeiyo interface kuti itariswe neILA musimboti.
AXI-MM ID Width: Inosarudza iyo ID hupamhi hweiyo AXI interface kana iyo slot_ interface mhando inogadziriswa seAXI-MM, kupi ndiyo nhamba ye slot.

AXI-MM Data Width: Inosarudza maparamita anoenderana neslot_Selects iyo Data upamhi hweiyo AXI interface kana slot_ interface mhando inogadziriswa seAXI-MM, kupi ndiyo nhamba ye slot.
AXI-MM Kero Width: Inosarudza iyo Kero hupamhi hweiyo AXI interface kana iyo slot_ interface mhando inogadziriswa seAXI-MM, kupi ndiyo nhamba ye slot.
Gonesa AXI-MM/Stream Protocol Checker: Inogonesa AXI4-MM kana AXI4-Stream protocol yekutarisa slot. apo slot_ interface mhando inogadziriswa seAXI-MM kana AXI4-Stream, kupi ndiyo nhamba ye slot.

Gonesa Transaction Tracking Counters: Inogonesa AXI4-MM transaction tracking kugona.
Nhamba Yekusarudzika Kuverenga Transaction: Inotsanangura huwandu hweisina Verenga kutengeserana paID paID. Hukoshi hunofanira kuenzana kana kuti hukuru kupfuura huwandu hwekusarirwa Verenga kutengeserana kwekubatanidza ikoko.
Nhamba Yezvakasaitwa Nyora Transaction: Inotsanangura nhamba yezvasara Nyora kutengeserana paID. Hukoshi hunofanira kuenzana kana kuti hukuru pane nhamba yezvasara Nyora kutengeserana kwekubatanidza ikoko.

Monitor APC Status masiginecha: Gonesa kutarisa kweiyo APC masiginecha eiyo slot apo slot_ interface mhando inogadziriswa seAXI-MM, kupi ndiyo nhamba ye slot.
Rongedza AXI yekuverenga kero chiteshi seData: Sarudza kuverenga kero chiteshi masiginecha ekuchengetedza data chinangwa cheslot apo slot_ interface mhando inogadziriswa seAXI-MM, kupi ndiyo nhamba ye slot.
Rongedza AXI yekuverenga kero chiteshi seTrigger: Sarudza verenga kero chiteshi masiginecha ekutsanangura chinokonzeresa mamiriro e slot. apo slot_ interface mhando inogadziriswa seAXI-MM, kupi ndiyo nhamba ye slot.

Gadzira AXI yekuverenga data chiteshi seData: Sarudza verenga data chiteshi masiginecha kuitira kuchengetedza data zvinangwa zve slot apo slot_ interface mhando inogadziriswa seAXI-MM, kupi ndiyo nhamba ye slot.
Rongedza AXI yekuverenga data chiteshi seTrigger: Sarudza verenga data chiteshi masiginecha ekutsanangura zvinokonzeresa mamiriro e slot. apo slot_ interface mhando inogadziriswa seAXI-MM, kupi ndiyo nhamba ye slot.
Gadzira AXI kunyora kero chiteshi seData: Sarudza nyora kero chiteshi masiginecha kuitira kuchengetedza data chinangwa cheslot apo slot_ interface mhando inogadziriswa seAXI-MM, kupi ndiyo nhamba ye slot.

Rongedza AXI yekunyora kero chiteshi seTrigger: Sarudza nyora kero chiteshi masiginecha ekutsanangura zvinokonzeresa mamiriro e slot. apo slot_ interface mhando inogadziriswa seAXI-MM, kupi ndiyo nhamba ye slot.
Gadzira AXI kunyora data chiteshi seData: Sarudza nyora dhata chiteshi masiginecha kuitira kuchengetedza data chinangwa cheslot apo slot_ interface mhando inogadziriswa seAXI-MM, kupi ndiyo nhamba ye slot.
Rongedza AXI kunyora dhata chiteshi seTrigger: Sarudza nyora dhata chiteshi masiginecha ekutsanangura chinokonzeresa mamiriro e slot. apo slot_ interface mhando inogadziriswa seAXI-MM, kupi ndiyo nhamba ye slot.

Gadzira AXI kunyora mhinduro chiteshi seData: Sarudza nyora mhinduro chiteshi masiginecha kuitira kuchengetedza data zvinangwa zve slot apo slot_ interface mhando inogadziriswa seAXI-MM, kupi ndiyo nhamba ye slot.
Rongedza AXI kunyora mhinduro chiteshi seTrigger: Sarudza nyora mhinduro chiteshi masiginecha ekutsanangura chinokonzeresa mamiriro e slot. apo slot_ interface mhando inogadziriswa seAXI-MM, kupi ndiyo nhamba ye slot.
AXI-Stream Tdata Width: Inosarudza iyo Tdata upamhi hweiyo AXI-Stream interface kana iyo slot_ interface mhando inogadziriswa seAXI-Stream, kupi ndiyo nhamba ye slot.

AXI-Stream TID Width: Inosarudza iyo TID upamhi hweiyo AXI-Stream interface kana iyo slot_ interface mhando inogadziriswa seAXI-Stream, kupi ndiyo nhamba ye slot.
AXI-Stream TUSER Width: Inosarudza iyo TUSER upamhi hweiyo AXI-Stream interface kana iyo slot_ interface mhando inogadziriswa seAXI-Stream, kupi ndiyo nhamba ye slot.
AXI-Stream TDEST Width: Inosarudza hupamhi hweTDEST hweAXI-Stream interface kana slot_ interface mhando inogadziriswa seAXI-Stream, kupi ndiyo nhamba ye slot.

Gadzirisa AXIS Signals seData: Sarudza AXI4-Stream masaini ekuchengetedza data chinangwa che slot
apo slot_ interface mhando inogadziriswa seAXI-Stream uko ndiyo nhamba ye slot.
Gadzirisa AXIS Signals seTrigger: Sarudza AXI4-Kuyerera masiginecha ekutsanangura chinokonzeresa mamiriro e slot. apo slot_ interface mhando inogadziriswa seAXI-Stream, kupi ndiyo nhamba ye slot.
Gadzirisa Slot seData uye/kana Trigger: Inosarudza isiri-AXI slot masiginecha yekutsanangura mamiriro ekutanga kana nekuda kwekuchengetedza data kana kune ese ari maviri slot. apo slot_ interface mhando inogadziriswa seisiri-AXI, kupi ndiyo nhamba ye slot.

Kuchengeta Sarudzo
Iyi inotevera nhamba inoratidza Kuchengeta Sarudzo tebhu iyo inokutendera iwe kuti usarudze rudzi rwekuchengetera chinangwa uye kudzika kwendangariro kushandiswa:

Chengetedzo Target: Iyi parameter inoshandiswa kusarudza rudzi rwekuchengetera chinangwa kubva pane yekudonha-pasi menyu.

Kudzika Kwedata: Iyi parameter inoshandiswa kusarudza yakakodzera sample kudzika kubva pane yekudonha-pasi menyu.

Advanced Options
Nhamba inotevera inoratidza iyo Advanced Options tab:

Gonesa AXI4-Stream Interface yeManual Connection kuAXI Debug Hub: Kana yagoneswa, iyi sarudzo inopa AXIS interface yeIP kuti ibatanidze kuAXI Debug Hub.
Gonesa Trigger Input Interface: Tarisa sarudzo iyi kuti ugone kugonesa yekusarudza yekupinza port port.
Gonesa Trigger Output Interface: Tarisa iyi sarudzo kuti igone kugonesa inokonzeresa yekuburitsa port.

Input Pipe Stages: Sarudza huwandu hwemarejista aunoda kuwedzera kune probe kuti uvandudze mabudiro ekuita. Iyi parameter inoshanda kune ese maprobes.
Yepamberi Trigger: Tarisa kugonesa iyo nyika muchina-based trigger sequencing.

Output Generation
Kuti uwane ruzivo, ona Vivado Dhizaini Suite Mushandisi Yekushandisa: Kugadzira neIP (UG896).

Kumanikidza Core

Zvinodiwa Zvisungo
Iyo ILA musimboti inosanganisira XDC file iyo ine zvipinganidzo zvemanyepo ekunyepa kudzivirira kuwanda-kumanikidza kwewachi kuyambuka nzira dzekubatanidza. Zvinotarisirwa zvakare kuti chiratidzo chewachi chakabatana neiyo clk yekupinza chiteshi cheiyo ILA musimboti inomanikidzwa mukugadzira kwako.

Chishandiso, Package, uye Speed Giredhi Sarudzo
Ichi chikamu hachishandi kune iyi IP core.

Clock Frequencies
Ichi chikamu hachishandi kune iyi IP core.

Clock Management
Ichi chikamu hachishandi kune iyi IP core.
Clock Placement
Ichi chikamu hachishandi kune iyi IP core.
Banking
Ichi chikamu hachishandi kune iyi IP core.

Transceiver Kuiswa
Ichi chikamu hachishandi kune iyi IP core.
I/O Standard uye Kuiswa
Ichi chikamu hachishandi kune iyi IP core.

Simulation

Kuti uwane ruzivo rwakakwana nezveVivado® simulation zvikamu, pamwe neruzivo rwekushandisa zvinotsigirwa zvechitatu-bato maturusi, ona Vivado Design Suite Mushandisi Wekushandisa: Logic Simulation (UG900).

Synthesis uye Implementation
Kuti uwane ruzivo nezve synthesis uye kuita, ona Vivado Dhizaini Suite Mushandisi Yekushandisa: Kugadzira neIP (UG896).

Debugging

Apendikisi iyi inosanganisira ruzivo nezve zviwanikwa zviripo paXilinx® Tsigiro websaiti uye debugging zvishandiso. Kana iyo IP ichida kiyi rezinesi, kiyi inofanirwa kusimbiswa. Iyo Vivado® dhizaini maturusi ane akati wandei marezinesi ekutarisa egating ine rezinesi IP kuburikidza nekuyerera. Kana cheki yerezinesi ikabudirira, IP inogona kuenderera mberi nechizvarwa. Zvikasadaro, chizvarwa chinomira nekukanganisa. Marezenisi ekutarisa anosimbiswa neanotevera maturusi:

Vivado Synthesis

Vivado Implementation
nyora_bitstream (Tcl command)

ZVINOKOSHA! IP rezinesi level inofuratirwa panzvimbo dzekutarisa. Muedzo unosimbisa rezinesi ririko. Iyo haitarise IP rezinesi level.

Kutsvaga Rubatsiro paXilinx.com

Kubatsira mukugadzira uye kugadzirisa maitiro kana uchishandisa musimboti, iyo Xilinx Tsigiro web peji ine zvakakosha zviwanikwa zvakaita sezvinyorwa zvechigadzirwa, zvinyorwa zvekuburitsa, marekodhi emhinduro, ruzivo nezvenyaya dzinozivikanwa, uye zvinongedzo zvekuwana kumwe kutsigirwa kwechigadzirwa. Iyo Xilinx Nharaunda Forums inowanikwawo apo nhengo dzinogona kudzidza, kutora chikamu, kugovana, uye kubvunza mibvunzo nezve Xilinx mhinduro.

Zvinyorwa
Ichi chigadzirwa gwara ndiro gwaro guru rakabatana nepakati. Gwaro iri, pamwe chete nemagwaro ane hukama kune zvese zvigadzirwa zvinobatsira mukugadzira maitiro, zvinogona kuwanikwa paXilinx Tsigiro. web peji kana kushandisa Xilinx® Documentation Navigator. Dhawunirodha iyo Xilinx Documentation Navigator kubva paKurodha peji. Kuti uwane rumwe ruzivo nezve chishandiso ichi uye maficha aripo, vhura iyo online rubatsiro mushure mekuisa.

Mhinduro Zvinyorwa
Mhinduro Zvinyorwa zvinosanganisira ruzivo pamusoro pezvinetso zvinowanzosangana nazvo, ruzivo runobatsira rwekugadzirisa matambudziko aya, uye chero nyaya dzinozivikanwa nechigadzirwa cheXilinx. Mhinduro Marekodhi anogadzirwa uye anochengetwa zuva nezuva achivimbisa kuti vashandisi vanokwanisa kuwana ruzivo rwakanyanya ruripo. Mhinduro Marekodhi eiyi musimboti anogona kuwanikwa nekushandisa Bhokisi reKutsvaga Tsigiro pane main Xilinx rutsigiro web peji. Kuti uwedzere mibairo yako yekutsvaga, shandisa mazwi makuru akadai se:

Product name
Turusi message(s)
Pfupiso yenyaya yasangana nayo

Kutsvaga kwesefa kunowanikwa mushure mekunge mhinduro dzadzoserwa kuti dziwedzere kunanga mhinduro.

Technical Support
Xilinx inopa rutsigiro rwehunyanzvi paXilinx Nharaunda Maforamu eiyi LogiCORE™ IP chigadzirwa kana ichishandiswa sekutsanangurwa kwechigadzirwa zvinyorwa. Xilinx haigone kuvimbisa nguva, kushanda, kana tsigiro kana ukaita chimwe chezvinotevera:

Shandisa mhinduro mumidziyo isina kutsanangurwa muzvinyorwa.

Gadzirisa mhinduro kupfuura inobvumidzwa mune zvinyorwa zvechigadzirwa.
Chinja chero chikamu chedhizaini chakanyorwa USACHINJA.

Kubvunza mibvunzo, enda kuXilinx Community Forums.

Zvimwe Zvishandiso uye Zviziviso Zvemutemo

Nhoroondo ye Xilinx Resources
Kuti uwane zviwanikwa zvekutsigira seMhinduro, Zvinyorwa, Dhawunirodha, uye Maforamu, ona Xilinx Tsigiro.

Zvinyorwa Navigator uye Dhizaini Hubs
Xilinx® Documentation Navigator (DocNav) inopa mukana kune Xilinx zvinyorwa, mavhidhiyo, uye zviwanikwa zvekutsigira, izvo zvaunogona kusefa nekutsvaga kuti uwane ruzivo. Kuvhura DocNav:

• Kubva paVivado® IDE, sarudza Rubatsiro → Zvinyorwa uye Tutorials.
• PaWindows, sarudza Tanga → Zvirongwa Zvose → Xilinx Dhizaini Zvishandiso → DocNav.
• PaLinux command kukurumidza, isa docnav.

Xilinx Dhizaini Hubs inopa zvinongedzo kune zvinyorwa zvakarongwa nedhizaini mabasa uye zvimwe zvinyorwa, izvo zvaunogona kushandisa kudzidza akakosha pfungwa uye kugadzirisa mibvunzo inowanzo bvunzwa. Kuti uwane iyo Dhizaini Hubs:

MuDocNav, tinya Dhizaini Hubs View tab.
Pamusoro peXilinx websaiti, ona iyo Dhizaini Hubs peji.

Cherechedza: Kuti uwane rumwe ruzivo nezve DocNav, ona iyo Documentation Navigator peji paXilinx website.

References
Aya magwaro anopa zvimwe zvinhu zvinobatsira negwaro iri:

Vivado Dhizaini Suite Mushandisi Yekushandisa: Kuronga uye Kugadzirisa (UG908)

Vivado Dhizaini Suite Mushandisi Yekushandisa: Kugadzira neIP (UG896)
Vivado Dhizaini Suite Mushandisi Yekushandisa: Kugadzira IP Subsystems uchishandisa IP Integrator (UG994)
Vivado Dhizaini Suite Mushandisi Yekushandisa: Kutanga (UG910)

Vivado Dhizaini Suite Yemushandisi Yekushandisa: Logic Simulation (UG900)
Vivado Dhizaini Suite Mushandisi Yekushandisa: Implementation (UG904)
ISE kuenda kuVivado Dhizaini Suite Yekufambisa Yekufambisa (UG911)

AXI Protocol Checker LogiCORE IP Chigadzirwa Guide (PG101)
AXI4-Stream Protocol Checker LogiCORE IP Chigadzirwa Guide (PG145)

Revision History
Tafura inotevera inoratidza nhoroondo yekudzokorora yegwaro iri.

Chikamu	Yekudzokorora Summary
11/23/2020 Shanduro 1.1
Kusunungurwa kwekutanga.	N/A

Ndapota Verenga: Zviziviso Zvinokosha Zvemutemo
Ruzivo rwauudzwa pazasi (iyo "Zvishandiso") runopihwa chete pakusarudza uye kushandisa zvigadzirwa zveXilinx. Kusvika pamwero mukuru unobvumidzwa nemutemo unoshanda: (1) Zvishandiso zvinogadzirwa kuti zviwanikwe “SEZVIRI” uye nekukanganisa kwese, Xilinx pano INORAMBA ZVINHU ZVOSE NEZVINHU, ZVINOTAURWA, ZVINOITWA, KANA ZVIRI MUKATI, zvinosanganisira ASI ZVISI ZVINOGONA KUTI ZVINHU ZVINHU, N. -KUTAURWA, KANA KUKOdzera PANE CHINANGWA CHECHINHU; uye (2) Xilinx haizove nemhosva (ingave muchibvumirano kana kukanganisa, kusanganisira kuregeredza, kana pasi peimwe dzidziso yemhosva) kune chero kurasikirwa kana kukuvadzwa kwechero rudzi kana hunhu hune hukama, hunobva pasi, kana maererano ne, Zvishandiso. (kusanganisira mashandisiro ako eZvishandiso), kusanganisira chero yakananga, isina kunanga, yakakosha, yakaitika, kana yakakonzeresa kurasikirwa kana kukuvadzwa (kusanganisira kurasikirwa nedata, purofiti, nyasha, kana chero rudzi rwekurasikirwa kana kukuvadzwa kwakakonzerwa nechero chiitiko chinounzwa. nemunhu wechitatu) kunyangwe kukuvadzwa kwakadai kana kurasikirwa kwaionekwa zvine musoro kana Xilinx akange audzwa nezve mukana wezvimwe.

Xilinx haatore chisungo chekugadzirisa chero zvikanganiso zviri muZvishandiso kana kukuzivisa iwe nezvekuvandudzwa kune Zvishandiso kana kune zvigadzirwa. Iwe haugone kuburitsa, kushandura, kugovera, kana kuratidza pachena Zvishandiso pasina mvumo yakanyorwa. Zvimwe zvigadzirwa zviri pasi pezvirevo uye mamiriro eiyo Xilinx's diki waranti, ndapota tarisa kune Xilinx's Mitemo yekutengesa iyo inogona viewed pa https://www.xilinx.com/legal.htm#tos; IP cores inogona kunge iri pasi pewaranti uye mazwi ekutsigira ari murezinesi rawakapihwa naXilinx. Zvigadzirwa zveXilinx hazvina kugadzirwa kana kuitirwa kutadza-kuchengetedza kana kushandiswa mune chero application inoda kutadza-kuchengetedza kuita; iwe unofungidzira njodzi yega uye mutoro wekushandisa zvigadzirwa zveXilinx mune zvakakomba maapplication, ndapota tarisa kune Xilinx's Terms of Sale inogona viewed pa https://www.xilinx.com/legal.htm#tos.
Gwaro iri rine ruzivo rwekutanga uye rinogona kuchinja pasina chiziviso. Ruzivo rwunopihwa pano rwune chekuita nezvigadzirwa uye/kana masevhisi haasati awanikwa kutengeswa, uye anopihwa nekuda kweruzivo chete uye haafanirwe, kana kutorwa sechipo chekutengesa kana kuedza kutengeserana kwezvigadzirwa uye/kana masevhisi anotaurwa nezvawo. muno.

AUTOMOTIVE APPLICATIONS DISCLAIMER
ZVINHU ZVINHU ZVINHU ZVINHU ZVINOGONA KUTI “XA” MUCHIKAMU NUMBER) HAZVIZVINHU ZVINOGONA KUTI ZVISHANDISWA PAKUPIWA MAAIRBAGS KANA KUTI KUSHANDISA MUMAKUMBIRA HUNOBVISA KUTONGIRWA KWEMOTA (“KUTEVEDZERA APPLICATION”) KASI PASINA KUTI KUTI KUTI KUTI KUTI KUTI KUTI KUTI KUTI KUTI KUTI KUTI KUTI KUTI KUTI KUTI KUTI KUTI KUTI KUSHANDISWE MUZVIKWERERO NE ISO 26262 AUTOMOTIVE SAFETY STANDARD ("KUDZIVIRIRA DESIGN"). VATENGI VACHANGE VASATI KUSHANDISA KANA KUGOVA ZVINHU ZVINO zvinosanganisira ZVIGADZO, NYATSOEDZA ZVINHU ZVINO ZVINHU ZVINHU ZVINHU ZVINHU ZVAKASIYANA. KUSHANDISA ZVINHU ZVINHU ZVINHU ZVINO SHANDISA ZVINHU ZVISINA KUDZVANWA ZVINONYADZERA PANGOZI YEMUTETESI, ZVINONYANYA CHETE PEMITEMO INOSHANDISA NEZVITENGO ZVINOITA MAPIMIRO PAMUSORO PAMUSORO PAMUSORO.
Copyright 2020 Xilinx, Inc. Xilinx, iyo Xilinx logo, Alveo, Artix, Kintex, Spartan, Versal, Virtex, Vivado, Zynq, uye mamwe mabhureki akasarudzwa anosanganisirwa muno zviratidzo zveXilinx muUnited States nedzimwe nyika. Zvimwe zviratidzo zvese zvinhu zvevaridzi vazvo.PG357 (v1.1) Mbudzi 23, 2020, ILA with AXI4-Stream Interface v1.1
Dhawunirodha PDF: Xilinx AXI4-Kuyerera Yakabatanidzwa Logic Analyzer Guide

References

User Manual