Xilinx AXI4-Stream Integrated Logic Analyzer Guide

Integrated Logic Analyzer (ILA) nrog AXI4-Stream Interface core yog ib qho kev hloov kho logic analyzer IP uas tuaj yeem siv los saib xyuas cov teeb liab sab hauv thiab cuam tshuam ntawm tus qauv tsim. ILA core suav nrog ntau yam kev tshaj lij ntawm cov cuab yeej ntsuas niaj hnub no, suav nrog boolean trigger sib npaug thiab ntug kev hloov pauv. Cov tub ntxhais tseem muaj kev sib tham debugging thiab saib xyuas kev muaj peev xwm nrog rau kev kuaj xyuas kev nco-mapped AXI thiab AXI4-kwj. Vim tias ILA core yog synchronous rau tus qauv tsim tau saib xyuas, txhua qhov kev tsim lub moos txwv uas siv rau koj tus qauv kuj tseem siv rau cov khoom ntawm ILA core. Txhawm rau debug interfaces hauv tus qauv tsim, ILA IP yuav tsum tau ntxiv rau kev tsim thaiv hauv Vivado® IP integrator. Ib yam li ntawd, AXI4 / AXI4-Stream raws tu qauv kev tshuaj xyuas kev xaiv tuaj yeem qhib rau ILA IP hauv IP integrator. Kev ua txhaum cai raws tu qauv tuaj yeem tshwm sim nyob rau hauv lub waveform viewer ntawm Vivado logic analyzer.

Nta

Tus neeg siv xaiv tau tus naj npawb ntawm cov chaw nres nkoj sojntsuam thiab qhov dav dav.

Cov neeg siv xaiv lub hom phiaj cia xws li thaiv RAM thiab UltraRAM
Ntau qhov chaw sojntsuam tuaj yeem muab tso ua ke rau hauv ib qho kev mob tshwm sim.

Cov neeg siv xaiv tau AXI qhov rau kev debug AXI interfaces hauv kev tsim.
Configurable xaiv rau AXI interfaces nrog rau hom interface thiab kab sample tob.

Cov ntaub ntawv thiab ua cov cuab yeej rau kev soj ntsuam.
Muaj tus lej sib piv thiab qhov dav rau txhua qhov kev sojntsuam thiab cov chaw nres nkoj ib leeg hauv cov interfaces.

Input/output cross-triggering interfaces.
Configurable pipelining rau input probes.

AXI4-MM thiab AXI4-Stream raws tu qauv kuaj.

Yog xav paub ntxiv txog ILA core, saib Vivado Design Suite User Guide: Programming and Debugging (UG908).

IP Qhov Tseeb

LogiCORE™ IP Facts Table
Core Specifications
Txhawb Kev Pabcuam Tsev Neeg1	Versal™ ACAP
Txhawb Cov Neeg Siv Khoom	IEEE Standard 1149.1 – JTAG
Muab nrog Core
Tsim Files	RTL
Examptsim	Verilog
Test Bench	Tsis Muaj
Kev txwv File	Xilinx® Design Constraints (XDC)
Simulation qauv	Tsis Muaj
Txhawb S/W Tsav Tsheb	N/A
Tested Design Flows2
Tsim kev nkag	Vivado® Design Suite
Kev simulation	Rau kev txhawb nqa simulators, saib cov Xilinx Tsim Cov Cuab Yeej: Tshaj Tawm Phau Ntawv Qhia.
Synthesis	Vivado Synthesis
Txhawb nqa
Tag nrho Vivado IP Hloov Log	Master Vivado IP Hloov Log: 72775
Xilinx Txhawb nqa web nplooj
Nco tseg: 1. Rau ib daim ntawv teev tag nrho ntawm cov cuab yeej txhawb nqa, saib Vivado® IP catalog. 2. Rau cov kev txhawb nqa versions ntawm cov cuab yeej, saib cov Xilinx Tsim Cov Cuab Yeej: Tshaj Tawm Phau Ntawv Qhia.

Tshajview

Navigating Cov ntsiab lus los ntawm Tus Txheej Txheem Tsim
Xilinx® cov ntaub ntawv raug teeb tsa nyob ib puag ncig cov txheej txheem tsim qauv los pab koj nrhiav cov ntsiab lus cuam tshuam rau koj txoj haujlwm txhim kho tam sim no. Cov ntaub ntawv no suav nrog cov txheej txheem tsim qauv hauv qab no:

Kho vajtse, IP, thiab Platform Development: Tsim cov PL IP blocks rau lub hardware platform, tsim PL kernels, subsystem functional simulation, thiab soj ntsuam lub sij hawm Vivado®, kev siv peev txheej, thiab kaw lub hwj chim. Kuj tseem suav nrog kev tsim kho kho vajtse platform rau kev sib koom ua ke. Cov ntsiab lus hauv daim ntawv no uas siv rau cov txheej txheem tsim qauv no suav nrog:
Chaw Nres Nkoj

Clocking thiab Resets
Customizing thiab tsim cov Core

Core Tshajview
Cov teeb liab thiab qhov cuam tshuam hauv FPGA tsim yog txuas nrog ILA sojntsuam thiab qhov nkag. Cov teeb liab thiab cov interfaces, txuas mus rau qhov kev sojntsuam thiab qhov nkag qhov sib npaug, yog sampcoj los ntawm kev tsim nrawm thiab khaws cia siv ntawm-chip thaiv RAM. Cov teeb liab thiab kev cuam tshuam hauv Versal ™ ACAP tsim yog txuas nrog ILA sojntsuam thiab qhov nkag. Cov teeb liab txuas thiab interfaces yog sampcoj ntawm kev tsim nrawm siv lub moos tseem ceeb nkag thiab khaws cia hauv on-chip thaiv RAM nco. Cov core parameter qhia cov hauv qab no:

Ib tug xov tooj ntawm probes (txog 512) thiab sojntsuam dav (1 txog 1024).

Ib tug xov tooj ntawm slots thiab interface xaiv.
Trace sample tob.

Cov ntaub ntawv thiab/lossis ua rau cov cuab yeej rau kev sojntsuam.
Tus naj npawb ntawm cov sib piv rau txhua qhov kev sojntsuam.

Kev sib txuas lus nrog ILA core yog ua los ntawm kev siv ib qho piv txwv ntawm AXI Debug Hub uas txuas rau Kev Tswj, Interface, thiab Txheej Txheem Txheej Txheem (CIPS) IP core.

Tom qab tus qauv tsim tau ntim rau hauv Versal ACAP, siv Vivado® logic analyzer software los teeb tsa qhov tshwm sim tshwm sim rau ILA ntsuas. Tom qab qhov tshwm sim tshwm sim, sample tsis yog sau thiab muab tso rau hauv Vivado logic analyzer. Koj ua tau view cov ntaub ntawv no siv lub qhov rai waveform. Kev sojntsuam sample thiab trigger functionality yog siv nyob rau hauv lub programmable logic cheeb tsam. On-chip block RAM lossis UltraRAM nco raws li lub hom phiaj cia koj tau xaiv thaum lub sijhawm kho kom haum uas khaws cov ntaub ntawv kom txog thaum nws raug xa tawm los ntawm software. Tsis muaj tus neeg siv cov tswv yim lossis tso tawm yuav tsum ua kom tshwm sim, ntes cov ntaub ntawv, lossis sib txuas lus nrog ILA core. ILA core muaj peev xwm saib xyuas cov teeb liab interface-theem, nws tuaj yeem xa cov ntaub ntawv hloov pauv qib xws li kev lag luam zoo rau AXI4 interfaces.

ILA Probe Trigger Comparator
Txhua qhov kev sojntsuam tawm tswv yim txuas nrog rau qhov sib piv uas muaj peev xwm ua tau ntau yam haujlwm. Thaum lub sij hawm khiav tus sib piv tuaj yeem teeb tsa ua = lossis != kev sib piv. Qhov no suav nrog cov qauv sib piv, xws li X0XX101. Nws kuj suav nrog kev txheeb xyuas ntug kev hloov pauv xws li nce ntug (R), ntug kev poob (F), ntug (B), lossis tsis muaj kev hloov pauv (N). Qhov sib piv ntawm qhov sib piv tuaj yeem ua tau ntau qhov sib piv, suav nrog >, <, ≥, thiab ≤.

TSEEM CEEB! Tus sib piv yog teem rau lub sij hawm khiav los ntawm Vivado® logic analyzer.

ILA Trigger Condition
Cov xwm txheej tshwm sim yog qhov tshwm sim ntawm Boolean "AND" lossis "OR" suav ntawm txhua qhov ntawm ILA kev sojntsuam ua rau cov txiaj ntsig sib piv. Siv Vivado® logic analyzer, koj xaiv seb puas yuav "TSIS" kev sojntsuam ua rau cov neeg sib piv kev sojntsuam lossis "OR" lawv. Qhov "AND" teeb tsa ua rau muaj qhov tshwm sim tshwm sim thaum txhua qhov kev sib piv ntawm ILA tau txaus siab. Qhov "OR" teeb tsa ua rau muaj qhov tshwm sim tshwm sim thaum ib qho ntawm ILA soj ntsuam kev sib piv txaus siab. Cov xwm txheej tshwm sim yog qhov tshwm sim tshwm sim siv rau kev ntsuas ILA taug qab.

Daim ntawv thov

ILA core yog tsim los siv rau hauv ib daim ntawv thov uas yuav tsum tau muaj pov thawj los yog kev debugging siv Vivado®. Cov duab hauv qab no qhia tau hais tias CIPS IP core sau thiab nyeem los ntawm AXI thaiv RAM tswj los ntawm AXI Network ntawm Chip (NoC). ILA core yog txuas nrog lub interface net ntawm AXI NoC thiab AXI thaiv RAM maub los saib xyuas AXI4 kev lag luam hauv tus tswj hwm kho vajtse.

Daim ntawv tso cai thiab Ordering
Qhov no Xilinx® LogiCORE™ IP module yog muab tsis muaj nqi ntxiv nrog Xilinx Vivado® Design Suite raws li cov nqe lus ntawm Xilinx End User License.
Nco tseg: Txhawm rau txheeb xyuas tias koj xav tau daim ntawv tso cai, kos rau kab ntawv tso cai ntawm IP Catalog. suav nrog txhais tau tias daim ntawv tso cai suav nrog Vivado® Design Suite; Kev yuav khoom txhais tau tias koj yuav tsum tau yuav daim ntawv tso cai siv lub hauv paus. Cov ntaub ntawv hais txog lwm yam Xilinx® LogiCORE™ IP modules muaj nyob rau ntawm nplooj ntawv Xilinx Intellectual Property. Yog xav paub txog tus nqi thiab muaj lwm yam Xilinx LogiCORE IP modules thiab cov cuab yeej, hu rau koj tus neeg muag khoom Xilinx hauv zos.

Khoom Specification

Chaw Nres Nkoj
Cov lus hauv qab no muab cov ntsiab lus hais txog ILA cov chaw nres nkoj thiab cov kev txwv.
ILA Ports

Table 1: ILA Ports
Chaw nres nkoj npe	I/O	Kev piav qhia
clk	I	Tsim lub moos uas teev txhua qhov ua rau thiab khaws cov logic.
soj ntsuam [ – 1:0]	I	Probe chaw nres nkoj input. Tus nab npawb chaw sojntsuam yog nyob rau hauv qhov ntau ntawm 0 mus rau 511. Qhov kev sojntsuam chaw nres nkoj dav (denoted by ) yog nyob rau hauv thaj tsam ntawm 1 txog 1024. Koj yuav tsum tshaj tawm qhov chaw nres nkoj no ua vector. Rau qhov chaw nres nkoj 1-ntsis, siv kev sojntsuam [0:0].
trig_out	O	Qhov chaw nres nkoj trig_out tuaj yeem tsim los ntawm qhov xwm txheej tshwm sim lossis los ntawm qhov chaw nres nkoj sab nraud trig_in. Muaj lub sijhawm khiav tswj los ntawm Logic Analyzer hloov ntawm qhov xwm txheej tshwm sim thiab trig_in los tsav trig_out.
trig_ ib	I	Input trigger port siv nyob rau hauv cov txheej txheem raws li qhov system rau Embedded Cross Trigger. Yuav txuas nrog lwm ILA los tsim cascading Trigger.
slot_ _	I	Qhov interface. Hom ntawm lub interface yog tsim dynamically raws li lub slot_ _ interface hom parameter. Cov chaw nres nkoj ib leeg hauv cov interfaces muaj rau kev saib xyuas hauv tus thawj tswj kho vajtse.
trig_out_ack	I	Kev lees paub rau trig_out.
trig_in_ack	O	Kev lees paub rau trig_in.
rov teem dua	I	ILA Input Hom thaum teem rau 'Interface Monitor', qhov chaw nres nkoj no yuav tsum yog tib lub teeb liab pib dua tshiab uas yog synchronous rau cov qauv tsim uas txuas nrog rau Slot_ _ ports ntawm ILA core.
S_AXIS	I/O	Xaiv qhov chaw nres nkoj. Siv rau kev sib txuas nrog AXI Debug Hub core thaum 'Enable AXI4- Kwj Interface rau Manul Connection rau AXI Debug Hub' raug xaiv nyob rau hauv Advanced Options.
M_AXIS	I/O	Xaiv qhov chaw nres nkoj. Siv rau kev sib txuas ntawm phau ntawv nrog AXI Debug Hub core thaum 'Enable AXI4- Kwj Interface rau phau ntawv txuas rau AXI Debug Hub' raug xaiv hauv 'Advanced Options'.

Table 1: ILA Ports (cont'd)
Chaw nres nkoj npe	I/O	Kev piav qhia
muaj kev	I	Xaiv qhov chaw nres nkoj. Siv rau kev sib txuas ntawm phau ntawv nrog AXI Debug Hub core thaum 'Enable AXI4- Kwj Interface rau phau ntawv txuas rau AXI Debug Hub' raug xaiv hauv 'Advanced Options'. Qhov chaw nres nkoj no yuav tsum tau synchronous nrog rov pib dua chaw nres nkoj ntawm AXI Debug Hub.
ua aclk	I	Xaiv qhov chaw nres nkoj. Siv rau kev sib txuas ntawm phau ntawv nrog AXI Debug Hub core thaum 'Enable AXI4- Kwj Interface rau phau ntawv txuas rau AXI Debug Hub' raug xaiv hauv 'Advanced Options'. Qhov chaw nres nkoj no yuav tsum synchronous nrog moos chaw nres nkoj ntawm AXI Debug Hub.

ILA Parameters

Table 2: ILA Parameters
Parameter	Tso cai Tus nqi	Qhov Tseem Ceeb	Kev piav qhia
Component_Npe	Txoj hlua nrog A–Z, 0–9, thiab _ (underscore)	ib_0	Lub npe ntawm instantiated feem.
C_NUM_OF_PROBES	1–512 : kuv	1	Tus naj npawb ntawm ILA sojntsuam chaw nres nkoj.
C_MEMORY_TYPE	0, 1	0	Cia lub hom phiaj rau cov ntaub ntawv ntes. 0 sib raug rau thaiv RAM thiab 1 sib raug rau UltraRAM.
C_DATA_DEPTH	1,024, 2,048, ib. 4,096, 8,192, ib. 16,384, 32,768, ib. 65,536, 131,072	1,024	Kev sojntsuam cia qhov tob tob. Tus lej no sawv cev rau tus lej siab tshaj plaws ntawm samples uas tuaj yeem khaws cia rau lub sijhawm ua haujlwm rau txhua qhov kev sojntsuam nkag.
C_PROBE _WIDTH	1–1024 : kuv	1	Dav ntawm kev sojntsuam chaw nres nkoj . Qhov twg yog qhov chaw nres nkoj sojntsuam muaj tus nqi ntawm 0 txog 1,023.
C_TRIGOUT_EN	Tseeb/False	FALSE	Enables lub trig tawm functionality. Cov chaw nres nkoj trig_out thiab trig_out_ack tau siv.
C_TRIGIN_EN	Tseeb/False	FALSE	Enables lub trig hauv functionality. Cov chaw nres nkoj trig_in thiab trig_in_ack tau siv.
C_INPUT_PIPE_STAGES	0–6 : kuv	0	Ntxiv flops ntxiv rau qhov chaw sojntsuam. Ib qho parameter siv tau rau txhua qhov chaw sojntsuam.
ALL_PROBE_SAME_MU	Tseeb/False	TRUE	Qhov no yuam tib qhov sib piv cov nqi units (match units) rau tag nrho cov probes.
C_PROBE _MU_CNT	1–16 : kuv	1	Number of Compare Value (Match) units ib qhov kev sojntsuam. Qhov no tsuas siv tau yog tias ALL_PROBE_SAME_MU yog FALSE.
C_PROBE _TYPE	DATA thiab TRIGGER, TRIGGER, DATA	DATA thiab TRIGGER	Txhawm rau xaiv ib qho kev sojntsuam xaiv rau kev qhia qhov xwm txheej tshwm sim lossis rau cov ntaub ntawv khaws cia lossis rau ob qho tib si.
C_ADV_TRIGGER	Tseeb/False	FALSE	Enables qhov kev xaiv ua ntej pib. Qhov no ua rau lub xeev lub tshuab ua haujlwm thiab koj tuaj yeem sau koj tus kheej ua ntu zus hauv Vivado Logic Analyzer.

Table 2: ILA Parameters (cont'd)
Parameter	Tso cai Tus nqi	Qhov Tseem Ceeb	Kev piav qhia
C_NUM_MONITOR_SLOTS	1-11 : kuv	1	Number of Interface Slots.
Nco tseg: 1. Qhov siab tshaj plaws ntawm tus nqi sib piv (match) units yog txwv rau 1,024. Rau qhov pib pib (C_ADV_TRIGGER = FALSE), txhua qhov kev sojntsuam muaj ib qho piv txwv tus nqi (raws li hauv version dhau los). Tab sis rau qhov kev xaiv ua ntej (C_ADV_TRIGGER = TRUE), qhov no txhais tau hais tias tus neeg sojntsuam tseem tuaj yeem xaiv cov naj npawb ntawm cov nqi sib piv ntawm ib mus rau plaub. Tab sis txhua qhov sib piv tus nqi yuav tsum tsis pub tshaj 1,024. Qhov no txhais tau tias, yog tias koj xav tau plaub qhov sib piv rau ib qho kev sojntsuam ces koj raug tso cai siv 256 qhov kev sojntsuam xwb.

Tsim nrog Core

Tshooj lus no suav nrog cov lus qhia thiab cov ntaub ntawv ntxiv los pab tsim kev tsim nrog lub hauv paus.

Lub moos
Lub clk input chaw nres nkoj yog lub moos siv los ntawm ILA core los sau npe cov nqi sojntsuam. Txhawm rau kom tau txais txiaj ntsig zoo tshaj plaws, nws yuav tsum yog tib lub moos teeb liab uas yog synchronous rau cov qauv tsim uas txuas nrog rau cov chaw nres nkoj sojntsuam ntawm ILA core. Thaum txuas manually nrog AXI Debug Hub, aclk teeb liab yuav tsum synchronous rau AXI Debug Hub moos input chaw nres nkoj.

Rov pib dua
Thaum koj teeb tsa ILA Input Type rau Interface Monitor, rov pib qhov chaw nres nkoj yuav tsum yog tib lub teeb liab pib dua uas yog synchronous rau tus qauv tsim logic uas nws txuas nrog.
slot_ _ chaw nres nkoj ntawm ILA core. Rau kev sib txuas ntawm phau ntawv nrog AXI Debug Hub core, tam sim no chaw nres nkoj yuav tsum tau synchronous nrog qhov chaw nres nkoj pib dua ntawm AXI Debug Hub core.

Tsim cov kauj ruam
Tshooj lus no piav qhia txog kev hloov kho thiab tsim cov tub ntxhais, txwv cov tub ntxhais kawm, thiab kev simulation, kev sib txuas, thiab kev siv cov kauj ruam uas tshwj xeeb rau tus tub ntxhais IP no. Cov ncauj lus kom ntxaws ntxiv txog tus qauv Vivado® tsim ntws thiab tus IP integrator tuaj yeem pom hauv Vivado Design Suite cov lus qhia hauv qab no:

Vivado Design Suite User Guide: Tsim IP Subsystems siv IP Integrator (UG994)
Vivado Design Suite User Guide: Tsim nrog IP (UG896)
Vivado Design Suite User Guide: Pib (UG910)
Vivado Design Suite User Guide: Logic Simulation (UG900)

Customizing thiab tsim cov Core

Tshooj lus no suav nrog cov ntaub ntawv hais txog kev siv Xilinx® cov cuab yeej los kho thiab tsim cov tub ntxhais hauv Vivado® Design Suite. Yog tias koj tab tom kho thiab tsim cov tub ntxhais hauv Vivado IP integrator, saib Vivado Design Suite User Guide: Tsim IP Subsystems siv IP Integrator (UG994) kom paub meej cov ntaub ntawv. IP integrator tej zaum yuav pib xam tej yam configuration qhov tseem ceeb thaum validating los yog tsim cov tsim. Txhawm rau txheeb xyuas seb cov txiaj ntsig puas hloov pauv, saib cov lus piav qhia ntawm qhov ntsuas hauv tshooj no. Rau view tus nqi parameter, khiav validate_bd_design hais kom ua hauv Tcl console. Koj tuaj yeem kho tus IP rau kev siv hauv koj tus qauv tsim los ntawm kev qhia qhov tseem ceeb rau ntau yam tsis cuam tshuam nrog tus IP core siv cov kauj ruam hauv qab no:

Xaiv tus IP los ntawm tus IP catalog.
Ob-nias tus IP xaiv los yog xaiv Customize IP hais kom ua los ntawm toolbar lossis right-click lub tshuab raj.

Yog xav paub meej, saib Vivado Design Suite User Guide: Tsim nrog IP (UG896) thiab Vivado Design Suite User Guide: Tau Txais (UG910). Cov duab hauv tshooj no yog cov duab piv txwv ntawm Vivado IDE. Cov layout piav qhia ntawm no yuav txawv ntawm qhov tam sim no version.

Txhawm rau nkag mus rau qhov tseem ceeb, ua cov hauv qab no:

Qhib ib qhov project los ntawm kev xaiv File ces Qhib Project los yog tsim ib qhov project tshiab los ntawm kev xaiv File Tom qab ntawd New Project hauv Vivado.
Qhib tus IP catalog thiab mus rau ib qho ntawm cov taxonomies.

Muab ob npaug rau-nias ILA los nqa lub npe tseem ceeb Vivado IDE.

General Options Vaj Huam Sib Luag
Cov duab hauv qab no qhia txog General Options tab nyob rau hauv qhov chaw Native uas tso cai rau koj los qhia cov kev xaiv:

Cov duab hauv qab no qhia tau hais tias General Options tab nyob rau hauv qhov chaw AXI uas tso cai rau koj los qhia cov kev xaiv:

Lub Npe Lub Npe: Siv cov ntawv sau no los muab lub npe tshwj xeeb module rau ILA core.

ILA Input Type: Qhov kev xaiv no qhia txog hom kev sib cuam tshuam lossis teeb liab ILA yuav tsum tau debugging. Tam sim no, qhov tseem ceeb rau qhov ntsuas no yog "Native Probes", "Interface Monitor" thiab "Mixed."
Number of Probes: Siv cov ntawv no los xaiv cov naj npawb ntawm cov chaw nres nkoj ntawm ILA core. Qhov siv tau ntau yam siv hauv Vivado® IDE yog 1 txog 64. Yog tias koj xav tau ntau tshaj 64 qhov chaw nres nkoj, koj yuav tsum siv Tcl cov lus txib ntws los tsim cov tub ntxhais ILA.
Ib tug xov tooj ntawm Interface Slots (tsuas yog muaj nyob rau hauv Interface Monitor hom thiab Mixed hom): qhov kev xaiv no tso cai rau koj xaiv tus naj npawb ntawm AXI interface slots uas yuav tsum tau txuas nrog lub ILA.

Tib Tus naj npawb ntawm Cov Sib Piv rau Txhua Qhov Chaw Nres Nkoj: Tus naj npawb ntawm cov sib piv rau ib qho kev sojntsuam tuaj yeem teeb tsa ntawm lub vaj huam sib luag no. Tib tus lej ntawm kev sib piv rau txhua qhov kev sojntsuam tuaj yeem qhib los ntawm kev xaiv.

Probe Port Panels
Cov duab hauv qab no qhia tau hais tias Probe Ports tab uas tso cai rau koj los qhia cov chaw:

Probe Port Panel: Dav ntawm txhua qhov Chaw Nres Nkoj tuaj yeem teeb tsa hauv Probe Port Panels. Txhua qhov chaw nres nkoj Probe muaj txog li xya qhov chaw nres nkoj.
Probe Width: Dav ntawm txhua qhov Chaw Nres Nkoj tuaj yeem hais tau. Qhov siv tau yog 1 txog 1024.
Number of Comparators: Qhov kev xaiv no tsuas yog qhib thaum "Tib Tus Naj Npawb Sib Piv rau Txhua Qhov Chaw Tshawb Fawb" kev xaiv raug kaw. Kev sib piv rau txhua qhov kev sojntsuam hauv thaj tsam 1 txog 16 tuaj yeem teeb tsa.

Cov ntaub ntawv thiab/lossis Trigger: Hom kev sojntsuam rau txhua qhov kev sojntsuam tuaj yeem tsim los siv qhov kev xaiv no. Cov kev xaiv siv tau yog DATA_and_TRIGGER, DATA thiab TRIGGER.
Comparator Options: Hom kev ua haujlwm lossis kev sib piv rau txhua qhov kev sojntsuam tuaj yeem tsim los siv qhov kev xaiv no.

Interface Options
Cov duab hauv qab no qhia txog Interface Options tab thaum Interface Monitor lossis Mixed hom raug xaiv rau hom ILA input:

Hom Interface: Tus neeg muag khoom, Lub Tsev Qiv Ntawv, Lub Npe, thiab Version (VLNV) ntawm lub interface yuav tsum tau saib xyuas los ntawm ILA core.
AXI-MM ID Dav: Xaiv qhov dav ID ntawm AXI interface thaum lub slot_ interface hom yog configured li AXI-MM, qhov twg yog tus lej xov tooj.

AXI-MM Cov Ntaub Ntawv Dav: Xaiv qhov tsis sib xws rau slot_Xaiv cov ntaub ntawv dav ntawm AXI interface thaum lub slot_ interface hom yog configured li AXI-MM, qhov twg yog tus lej xov tooj.
AXI-MM Chaw Nyob Dav: Xaiv qhov chaw nyob dav ntawm AXI interface thaum lub slot_ interface hom yog configured li AXI-MM, qhov twg yog tus lej xov tooj.
Pab kom AXI-MM/Stream Protocol Checker: Pab kom AXI4-MM lossis AXI4-Stream raws tu qauv checker rau qhov thaum kawg_ interface hom yog configured li AXI-MM los yog AXI4-kwj, qhov twg yog tus lej xov tooj.

Pab Txhawb Kev Ua Lag Luam Taug Xyuas Cov Counters: Pab kom AXI4-MM kev lag luam taug qab muaj peev xwm.
Number of Outstanding Read Transactions: Qhia tus naj npawb ntawm cov ntawv nyeem tau zoo rau ib tus ID. Tus nqi yuav tsum sib npaug los yog ntau dua tus naj npawb ntawm cov ntawv nyeem zoo rau qhov kev sib txuas ntawd.
Number of Outstanding Sau Transactions: Qhia tus naj npawb ntawm cov ntawv sau ua lag luam zoo ib tus ID. Tus nqi yuav tsum sib npaug los yog ntau dua tus lej ntawm cov ntawv sau ua lag luam rau qhov kev sib txuas ntawd.

Saib xyuas APC Status Pib ntsais koj teeb: Pab saib xyuas cov xwm txheej APC cov cim rau qhov thaum kawg_ interface hom yog configured li AXI-MM, qhov twg yog tus lej xov tooj.
Configure AXI nyeem chaw nyob channel raws li Cov Ntaub Ntawv: Xaiv qhov chaw nyob cov cim qhia rau cov ntaub ntawv khaws cia lub hom phiaj rau qhov thaum kawg_ interface hom yog configured li AXI-MM, qhov twg yog tus lej xov tooj.
Configure AXI nyeem qhov chaw nyob channel li Trigger: Xaiv qhov chaw nyob channel cov cim qhia rau kev qhia txog qhov tshwm sim rau qhov thaum kawg_ interface hom yog configured li AXI-MM, qhov twg yog tus lej xov tooj.

Configure AXI nyeem cov ntaub ntawv channel raws li Cov Ntaub Ntawv: Xaiv cov ntawv nyeem cov cim qhia rau cov ntaub ntawv khaws cia rau lub hom phiaj thaum kawg_ interface hom yog configured li AXI-MM, qhov twg yog tus lej xov tooj.
Configure AXI nyeem cov ntaub ntawv channel raws li Trigger: Xaiv cov ntawv nyeem cov cim qhia rau kev qhia cov xwm txheej tshwm sim rau qhov thaum kawg_ interface hom yog configured li AXI-MM, qhov twg yog tus lej xov tooj.
Configure AXI sau chaw nyob channel raws li Cov Ntaub Ntawv: Xaiv qhov chaw nyob cov cim qhia rau cov ntaub ntawv khaws cia lub hom phiaj rau qhov thaum kawg_ interface hom yog configured li AXI-MM, qhov twg yog tus lej xov tooj.

Configure AXI sau chaw nyob channel raws li Trigger: xaiv sau chaw nyob channel cov cim qhia rau kev qhia txog qhov tshwm sim rau qhov thaum kawg_ interface hom yog configured li AXI-MM, qhov twg yog tus lej xov tooj.
Configure AXI sau cov ntaub ntawv channel raws li Cov Ntaub Ntawv: Xaiv sau cov ntaub ntawv channel cov cim rau cov ntaub ntawv khaws cia lub hom phiaj rau qhov thaum kawg_ interface hom yog configured li AXI-MM, qhov twg yog tus lej xov tooj.
Configure AXI sau cov ntaub ntawv channel raws li Trigger: Xaiv sau cov ntaub ntawv channel cov cim qhia rau kev qhia qhov tshwm sim rau qhov thaum kawg_ interface hom yog configured li AXI-MM, qhov twg yog tus lej xov tooj.

Configure AXI sau cov lus teb raws li Cov Ntaub Ntawv: Xaiv sau cov lus teb cov cim qhia rau cov ntaub ntawv khaws cia lub hom phiaj rau qhov thaum kawg_ interface hom yog configured li AXI-MM, qhov twg yog tus lej xov tooj.
Configure AXI sau cov lus teb raws li Trigger: Xaiv sau cov lus teb cov cim qhia rau kev qhia qhov tshwm sim rau qhov thaum kawg_ interface hom yog configured li AXI-MM, qhov twg yog tus lej xov tooj.
AXI-Stream Tdata Dav: Xaiv Tdata dav ntawm AXI-kwj interface thaum lub slot_ hom interface yog configured li AXI-kwj, qhov twg yog tus lej xov tooj.

AXI-Stream TID Dav: Xaiv qhov dav TID ntawm AXI-kwj interface thaum lub slot_ hom interface yog configured li AXI-kwj, qhov twg yog tus lej xov tooj.
AXI-Stream TUSER Dav: Xaiv TUSER dav ntawm AXI-kwj interface thaum lub slot_ hom interface yog configured li AXI-kwj, qhov twg yog tus lej xov tooj.
AXI-Stream TDEST Dav: Xaiv TDEST dav ntawm AXI-kwj interface thaum lub slot_ hom interface yog configured li AXI-kwj, qhov twg yog tus lej xov tooj.

Configure AXIS Signals raws li cov ntaub ntawv: Xaiv AXI4-kwj cov cim rau cov ntaub ntawv khaws cia lub hom phiaj rau qhov
thaum kawg_ interface hom yog configured li AXI-kwj qhov twg yog tus lej xov tooj.
Configure AXIS Signals li Trigger: Xaiv AXI4-kwj teeb liab rau kev qhia txog qhov tshwm sim rau qhov thaum kawg_ hom interface yog configured li AXI-kwj, qhov twg yog tus lej xov tooj.
Configure Slot raws li cov ntaub ntawv thiab/los yog Trigger: Xaiv cov uas tsis yog-AXI qhov teeb liab rau kev qhia qhov tshwm sim los yog rau cov ntaub ntawv cia lub hom phiaj los yog rau ob qho tib si rau qhov thaum kawg_ hom interface yog configured li non-AXI, qhov twg yog tus lej xov tooj.

Kev xaiv cia
Cov duab hauv qab no qhia txog Kev Xaiv Cia tab uas tso cai rau koj xaiv lub hom phiaj cia thiab qhov tob ntawm lub cim xeeb los siv:

Cia Lub Hom Phiaj: Qhov kev ntsuas no yog siv los xaiv cov hom phiaj cia los ntawm cov ntawv qhia zaub mov poob.

Cov ntaub ntawv qhov tob: Qhov ntsuas no yog siv los xaiv qhov tsim nyog sample qhov tob los ntawm cov ntawv qhia zaub mov.

Advanced Options
Cov duab hauv qab no qhia txog Advanced Options tab:

Pab kom AXI4-kwj Interface rau phau ntawv txuas rau AXI Debug Hub: Thaum qhib, qhov kev xaiv no muab AXIS interface rau IP txuas rau AXI Debug Hub.
Pab kom Trigger Input Interface: Txheeb xyuas qhov kev xaiv no txhawm rau txhawm rau txhawm rau txhawm rau nkag qhov chaw nkag.
Pab kom Trigger Output Interface: Kos qhov kev xaiv no kom pab tau qhov kev xaiv qhov chaw tso zis tawm.

Input Tube Stages: Xaiv tus naj npawb ntawm cov ntawv sau npe uas koj xav ntxiv rau qhov kev sojntsuam txhawm rau txhim kho kev ua tiav. Qhov kev ntsuas no siv tau rau txhua qhov kev sojntsuam.
Advanced Trigger: Txheeb xyuas kom ua kom lub xeev lub tshuab ua raws li kev sib tw.

Tso zis tiam
Yog xav paub ntxiv, saib Vivado Design Suite User Guide: Designing with IP (UG896).

Constraining lub Core

Yuav tsum tau txwv
ILA core suav nrog XDC file uas muaj cov kev txwv tsis raug cai uas tsim nyog los tiv thaiv kev txwv tsis pub dhau ntawm lub moos sau hla txoj hauv kev synchronization. Nws tseem yuav tsum tau hais tias lub moos teeb liab txuas nrog lub clk input chaw nres nkoj ntawm ILA core raug txwv kom raug rau hauv koj tus qauv tsim.

Ntaus, Pob, thiab Kev Xaiv Qib Siab
Tshooj lus no tsis muaj feem xyuam rau tus tub ntxhais IP no.

Lub moos zaus
Tshooj lus no tsis muaj feem xyuam rau tus tub ntxhais IP no.

Tswj moos
Tshooj lus no tsis muaj feem xyuam rau tus tub ntxhais IP no.
Lub moos tso
Tshooj lus no tsis muaj feem xyuam rau tus tub ntxhais IP no.
Kev txhab nyiaj
Tshooj lus no tsis muaj feem xyuam rau tus tub ntxhais IP no.

Transceiver Placement
Tshooj lus no tsis muaj feem xyuam rau tus tub ntxhais IP no.
I/O Standard thiab Placement
Tshooj lus no tsis muaj feem xyuam rau tus tub ntxhais IP no.

Kev simulation

Yog xav paub ntxiv txog Vivado® simulation Cheebtsam, nrog rau cov ntaub ntawv hais txog kev siv cov cuab yeej thib peb, saib Vivado Design Suite User Guide: Logic Simulation (UG900).

Synthesis thiab Implementation
Yog xav paub meej txog kev sib txuas thiab kev siv, saib Vivado Design Suite User Guide: Designing with IP (UG896).

Kev debugging

Cov ntawv txuas ntxiv no suav nrog cov ntsiab lus hais txog cov peev txheej muaj nyob ntawm Xilinx® Support website thiab debugging cuab yeej. Yog tias tus IP xav tau tus yuam sij daim ntawv tso cai, tus yuam sij yuav tsum raug txheeb xyuas. Cov cuab yeej tsim Vivado® muaj ntau qhov chaw kuaj xyuas daim ntawv tso cai rau kev nkag mus rau IP daim ntawv tso cai los ntawm kev ntws. Yog tias daim ntawv tso cai kuaj ua tiav, IP tuaj yeem txuas ntxiv mus. Txwv tsis pub, tiam halts nrog ib qho yuam kev. Daim ntawv tso cai checkpoints raug tswj los ntawm cov cuab yeej hauv qab no:

Vivado Synthesis

Kev siv Vivado
write_bitstream (Tcl hais kom ua)

TSEEM CEEB! IP daim ntawv tso cai qib tsis quav ntsej ntawm cov chaw kuaj xyuas. Qhov kev ntsuam xyuas pom tias muaj daim ntawv tso cai siv tau. Nws tsis kuaj IP daim ntawv tso cai qib.

Nrhiav Kev Pab ntawm Xilinx.com

Txhawm rau pab tsim thiab kho cov txheej txheem thaum siv cov tub ntxhais, Xilinx Support web nplooj ntawv muaj cov ntaub ntawv tseem ceeb xws li cov ntaub ntawv tsim khoom, cov ntawv tso tawm, cov ntaub ntawv teb, cov ntaub ntawv hais txog cov teeb meem paub, thiab kev sib txuas kom tau txais kev txhawb nqa khoom ntxiv. Xilinx Community Forums kuj muaj nyob qhov twg cov tswv cuab tuaj yeem kawm, koom, sib koom, thiab nug cov lus nug txog Xilinx cov kev daws teeb meem.

Cov ntaub ntawv
Cov khoom qhia no yog cov ntaub ntawv tseem ceeb cuam tshuam nrog lub hauv paus. Cov lus qhia no, nrog rau cov ntaub ntawv hais txog txhua yam khoom uas pab hauv cov txheej txheem tsim, tuaj yeem pom ntawm Xilinx Support web nplooj ntawv lossis los ntawm kev siv Xilinx® Documentation Navigator. Download Xilinx Documentation Navigator los ntawm nplooj ntawv Downloads. Yog xav paub ntxiv txog cov cuab yeej no thiab cov yam ntxwv muaj, qhib qhov kev pab online tom qab kev teeb tsa.

Teb cov ntaub ntawv
Cov ntaub ntawv teb suav nrog cov ntaub ntawv hais txog cov teeb meem feem ntau ntsib, cov ntaub ntawv muaj txiaj ntsig ntawm kev daws cov teeb meem no, thiab cov teeb meem paub txog ntawm Xilinx khoom. Cov ntaub ntawv teb yog tsim thiab khaws cia txhua hnub kom ntseeg tau tias cov neeg siv tau nkag mus rau cov ntaub ntawv muaj tseeb tshaj plaws. Teb Cov Ntaub Ntawv rau cov tub ntxhais no tuaj yeem nyob tau los ntawm kev siv lub thawv Tshawb Nrhiav ntawm lub ntsiab Xilinx txhawb nqa web nplooj. Txhawm rau kom ua tiav koj cov txiaj ntsig tshawb fawb, siv cov lus tseem ceeb xws li:

Khoom npe
Tool message(s)
Cov ntsiab lus ntawm qhov teeb meem ntsib

Kev tshawb nrhiav lim dej muaj nyob tom qab cov txiaj ntsig tau rov qab los rau lub hom phiaj ntxiv cov txiaj ntsig.

Kev pab txhawb nqa
Xilinx muab kev txhawb nqa ntawm Xilinx Community Forums rau LogiCORE™ IP khoom siv thaum siv raws li tau piav qhia hauv cov ntaub ntawv khoom. Xilinx tsis tuaj yeem lav lub sijhawm, kev ua haujlwm, lossis kev txhawb nqa yog tias koj ua ib qho hauv qab no:

Siv cov kev daws teeb meem hauv cov khoom siv uas tsis tau txhais hauv cov ntaub ntawv.

Customize qhov kev daws teeb meem tshaj qhov tau tso cai hauv cov ntaub ntawv khoom.
Hloov txhua ntu ntawm tus tsim daim ntawv sau npe TSIS TXHOB hloov kho.

Txhawm rau nug cov lus nug, mus rau Xilinx Community Forums.

Cov peev txheej ntxiv thiab cov ntawv ceeb toom raug cai

Xilinx Resources
Rau kev txhawb nqa xws li Cov Lus Teb, Cov Ntaub Ntawv, Downloads, thiab Cov Rooj Sib Tham, saib Xilinx Support.

Documentation Navigator thiab Design Hubs
Xilinx® Documentation Navigator (DocNav) muab kev nkag mus rau Xilinx cov ntaub ntawv, yeeb yaj kiab, thiab kev txhawb nqa, uas koj tuaj yeem lim thiab tshawb nrhiav cov ntaub ntawv. Txhawm rau qhib DocNav:

• Los ntawm Vivado® IDE, xaiv Kev Pab → Cov Ntaub Ntawv thiab Cov Lus Qhia.
• Hauv Windows, xaiv Pib → Tag Nrho Cov Kev Pabcuam → Xilinx Tsim Cov Cuab Yeej → DocNav.
• Ntawm Linux hais kom ua, sau docnav.

Xilinx Design Hubs muab cov ntawv txuas mus rau cov ntaub ntawv tsim los ntawm cov haujlwm tsim thiab lwm yam ntsiab lus, uas koj tuaj yeem siv los kawm cov ntsiab lus tseem ceeb thiab teb cov lus nug nquag. Txhawm rau nkag mus rau Design Hubs:

Hauv DocNav, nyem qhov Tsim Hubs View tab.
Hauv Xilinx website, saib nplooj ntawv Tsim Hubs.

Nco tseg: Yog xav paub ntxiv txog DocNav, saib nplooj ntawv Cov Ntaub Ntawv Navigator ntawm Xilinx webqhov chaw.

Cov ntaub ntawv
Cov ntaub ntawv no muab cov ntaub ntawv ntxiv muaj txiaj ntsig nrog cov lus qhia no:

Vivado Design Suite User Guide: Programming thiab Debugging (UG908)

Vivado Design Suite User Guide: Tsim nrog IP (UG896)
Vivado Design Suite User Guide: Tsim IP Subsystems siv IP Integrator (UG994)
Vivado Design Suite User Guide: Pib (UG910)

Vivado Design Suite User Guide: Logic Simulation (UG900)
Vivado Design Suite Daim Ntawv Qhia Tus Neeg Siv: Kev Ua Haujlwm (UG904)
ISE rau Vivado Design Suite Migration Guide (UG911)

AXI Protocol Checker LogiCORE IP Khoom Qhia (PG101)
AXI4-Stream Protocol Checker LogiCORE IP Khoom Qhia (PG145)

Kev kho keeb kwm
Cov lus hauv qab no qhia txog keeb kwm kho dua tshiab rau daim ntawv no.

Tshooj	Cov ntsiab lus kho dua
11/23/2020 Version 1.1
Kev tso tawm thawj zaug.	N/A

Thov Nyeem: Cov Ntawv Ceeb Toom Tseem Ceeb
Cov ntaub ntawv tshaj tawm rau koj hauv qab no ("Cov Khoom") tsuas yog muab rau kev xaiv thiab siv cov khoom siv Xilinx. Txog qhov siab tshaj plaws uas tau tso cai los ntawm txoj cai lij choj: (1) Cov ntaub ntawv tau tsim muaj "AS YOG" thiab nrog txhua qhov ua txhaum cai, Xilinx ntawm no tsis lees paub txhua qhov kev lav phib xaub thiab cov xwm txheej, EXPRESS, IMPLIED, OR STATUTORY, suav nrog TABSIS TSIS TXAUS SIAB RAU WARRANTIES -Kev ua txhaum cai, lossis kev haum xeeb rau txhua lub hom phiaj tshwj xeeb; thiab (2) Xilinx yuav tsis lav (txawm hais tias nyob rau hauv daim ntawv cog lus los yog tsim txom, nrog rau kev tsis saib xyuas, los yog nyob rau hauv lwm yam kev xav ntawm kev lav phib xaub) rau ib qho kev poob los yog kev puas tsuaj ntawm ib yam dab tsi uas cuam tshuam nrog, tshwm sim hauv qab, lossis cuam tshuam nrog, Cov Khoom Siv (xws li koj siv cov khoom siv), suav nrog rau txhua yam ncaj qha, tsis ncaj, tshwj xeeb, xwm txheej, lossis qhov tshwm sim los yog kev puas tsuaj (nrog rau cov ntaub ntawv poob, cov txiaj ntsig, kev ua siab zoo, lossis txhua yam kev poob lossis kev puas tsuaj raug cuam tshuam los ntawm kev nqis tes ua. los ntawm ib tug thib peb) txawm hais tias xws li kev puas tsuaj los yog poob yog tsim nyog los pom los yog Xilinx tau qhia txog qhov muaj peev xwm ntawm tib yam.

Xilinx xav tias tsis muaj lub luag haujlwm los kho cov teeb meem uas muaj nyob hauv Cov Khoom Siv lossis ceeb toom koj txog kev hloov tshiab rau Cov Khoom Siv lossis cov khoom tshwj xeeb. Koj tsis tuaj yeem tsim tawm, hloov kho, faib, lossis nthuav tawm cov khoom siv yam tsis tau tso cai ua ntej. Qee cov khoom lag luam raug ua raws li cov lus cog tseg thiab cov xwm txheej ntawm Xilinx lub warranty txwv, thov xa mus rau Xilinx Cov Cai Muag Khoom uas tuaj yeem ua tau. viewed ua https://www.xilinx.com/legal.htm#tos; IP cores yuav raug lees paub thiab cov lus txhawb nqa uas muaj nyob rau hauv daim ntawv tso cai muab rau koj los ntawm Xilinx. Xilinx cov khoom tsis tsim los yog npaj kom tsis txhob muaj kev nyab xeeb lossis siv rau hauv ib daim ntawv thov uas xav tau kev ua haujlwm tsis zoo; koj xav tias ib qho kev pheej hmoo thiab kev lav phib xaub rau kev siv Xilinx cov khoom lag luam hauv cov ntawv thov tseem ceeb, thov xa mus rau Xilinx Cov Lus Cog Tseg ntawm Kev Muag Khoom uas tuaj yeem yog viewed ua https://www.xilinx.com/legal.htm#tos.
Cov ntaub ntawv no muaj cov ntaub ntawv ua ntej thiab yuav hloov pauv yam tsis tau ceeb toom. Cov ntaub ntawv muab los ntawm no muaj feem xyuam rau cov khoom lag luam thiab / lossis cov kev pabcuam tseem tsis tau muaj muag, thiab tsuas yog muab rau cov ntaub ntawv xov xwm nkaus xwb thiab tsis yog npaj, lossis raug txhais, raws li kev muab muag lossis sim ua lag luam ntawm cov khoom thiab / lossis cov kev pabcuam raug xa mus rau ntawm no.

AUTOMOTIVE APPLICATIONS DISCLAIMER
AUTOMOTIVE PRODUCTS (XAIV KOM "XA" nyob rau hauv PART NUMBER) TSIS MUAJ TSEEB HAUV CHAW UA HAUJ LWM HAUV LUB AIRbags los yog siv nyob rau hauv daim ntawv thov uas cuam tshuam rau kev tswj ntawm ib lub tsheb ("SAIB NTAUB NTAWV KEV PAB CUAM" TSIS TXAUS SIAB Nrog rau ISO 26262 AUTOMOTIVE SAFETY STANDARD ("SAFETY DESIGN"). Cov neeg siv khoom yuav tsum, ua ntej siv lossis faib cov kab ke uas koom nrog cov khoom lag luam, ua tib zoo sim cov txheej txheem no kom muaj kev nyab xeeb. Kev siv cov khoom lag luam hauv daim ntawv thov kev nyab xeeb yam tsis muaj kev nyab xeeb tsim yog tag nrho ntawm kev pheej hmoo ntawm cov neeg siv khoom, tsuas yog siv rau txoj cai lij choj thiab cov cai tswj hwm kev txwv ntawm cov khoom lag luam.
Copyright 2020 \ Crushing Tsob Nroj \ 357 Xilinx, Inc. Xilinx, Xilinx logo, Alveo, Artix, Kintex, Spartan, Versal, Virtex, Vivado, Zynq, thiab lwm hom npe uas suav nrog hauv no yog cov cim lag luam ntawm Xilinx hauv Tebchaws Meskas thiab lwm lub tebchaws. Tag nrho lwm cov cim lag luam yog cov cuab yeej ntawm lawv cov tswv.PG1.1 (v23) Lub Kaum Ib Hlis 2020, 4, ILA nrog AXI1.1-Stream Interface vXNUMX
Rub tawm PDF: Xilinx AXI4-Stream Integrated Logic Analyzer Guide

Cov ntaub ntawv

Cov neeg siv phau ntawv