intel AN 522 Kukhazikitsa Mabasi LVDS Chiyankhulo mu Mabanja Othandizira a FPGA Chipangizo

Mabasi LVDS (BLVDS) amakulitsa kuthekera kwa kulumikizana kwa LVDS poyambira mpaka kumayitanidwe ambiri. Multipoint BLVDS imapereka yankho lothandiza pamapulogalamu ambiri obwerera kumbuyo.

BLVDS Implementation Support mu Intel FPGA Devices

Mutha kugwiritsa ntchito mawonekedwe a BLVDS pazida za Intel izi pogwiritsa ntchito miyezo ya I/O yomwe yalembedwa.

Zindikirani:
Mphamvu zamagalimoto osinthika komanso mawonekedwe ophatikizika pazida izi zimakupatsani mwayi wosinthira makina anu ambiri kuti mugwire bwino ntchito. Kuti mudziwe kuchuluka kwa data yomwe imathandizira, chitani kayesedwe kapena muyeso kutengera dongosolo lanu komanso kagwiritsidwe ntchito kanu.
BLVDS Paview patsamba 4
BLVDS Technology mu Intel Devices patsamba 6
Kugwiritsa Ntchito Mphamvu kwa BLVDS patsamba 9
BLVDS Design Example patsamba 10
Kusanthula Kachitidwe patsamba 17
Mbiri Yokonzanso Zolemba za AN 522: Kukhazikitsa Chiyankhulo cha Bus LVDS mu Mabanja a Chipangizo cha Intel FPGA patsamba 25
Zambiri Zogwirizana
Miyezo ya I/O ya BLVDS Interface mu Intel FPGA Devices patsamba 7

BLVDS Paview

Dongosolo lodziwika bwino la multipoint BLVDS lili ndi ma transmitter angapo ndi olandila awiriawiri (transceivers) omwe amalumikizidwa ndi basi.
Multipoint BLVDSKusintha kwa chithunzi chapitachi kumapereka kulankhulana kwapawiri-hafu-duplex pamene kumachepetsa kusamvana kwapakati. Transceiver iliyonse imatha kutenga gawo la transmitter, ndi ma transceivers otsalawo omwe amakhala ngati olandila (chotumiza chimodzi chokha chingathe kugwira ntchito panthawi imodzi). Kuwongolera magalimoto pamabasi, mwina kudzera mu protocol kapena njira ya hardware nthawi zambiri kumafunika kupewa mikangano yoyendetsa basi. Kuchita kwa multipoint BLVDS kumakhudzidwa kwambiri ndi kukweza kwa capacitive ndi kutha kwa basi.
Malingaliro Opanga
Mapangidwe abwino a ma multipoint ayenera kuganizira za kuchuluka kwa capacitive ndi kuyimitsa pa basi kuti apeze kukhulupirika kwa siginecha. Mutha kuchepetsa kuchuluka kwa katunduyo posankha transceiver yokhala ndi pini yotsika, cholumikizira chokhala ndi mphamvu yochepa, ndikusunga kutalika kwa stub. Chimodzi mwazolingalira zamapangidwe a multipoint BLVDS ndikusiyana kokwanira kwa basi yodzaza kwathunthu, komwe kumatchedwa kulepheretsa kogwira mtima, komanso kuchedwa kufalitsa kudzera m'basi. Zolinga zina zamitundu yambiri za BLVDS zikuphatikiza kukondera kotetezedwa, mtundu wolumikizira ndi pin-out, masanjidwe a basi ya PCB, ndi mawonekedwe amtundu wa driver.
Impedans Yogwira
Kulepheretsa kogwira mtima kumadalira momwe mabasi amayendera Impedans Zo komanso kutsitsa kwapa basi. Zolumikizira, zomangira pa plug-in khadi, zoyikapo, ndi mphamvu yolowera yolandila zonse zimathandizira pakukweza, zomwe zimachepetsa kutsekeka kwa basi.
Equation 1. Kusiyana kothandiza kwa Impedans equation
Gwiritsani ntchito equation iyi kuti muyerekeze kusiyana kosiyana kwa basi yodzaza (Zeff).Kumene:

• Zdiff (Ω) ≈ 2 × Zo = kusiyana kwa mawonekedwe a basi
•  Co (pF/inchi) = luso lapadera pa kutalika kwa basi
• CL (pF) = mphamvu ya katundu aliyense
•  N = chiwerengero cha katundu pa basi
•  H (inchi) = d × N = kutalika kwa basi
•  d (inchi) = kusiyana pakati pa plug-in iliyonse khadi
•  Cd (pF/inchi) = CL/d = mphamvu yogawidwa pa utali wa unit kudutsa basi

Kuwonjezeka kwa kuchuluka kwa katundu kapena kuyandikira kwapakati pakati pa makhadi a pulagi kumachepetsa kutsekereza kogwira mtima. Kuti muwonjezere magwiridwe antchito, ndikofunikira kusankha transceiver otsika capacitance ndi cholumikizira. Pini iliyonse yolandira wolandila pakati pa cholumikizira ndi pini ya transceiver I/O ikhale yayifupi momwe mungathere.
Normalized Effective Impedans Versus Cd/Co
Chiwerengerochi chikusonyeza zotsatira za capacitance anagawira pa normalized ogwira impedance.Kuthetsa kumafunika kumapeto kwa basi, pamene deta imayenda mbali zonse ziwiri. Kuti muchepetse kusinkhasinkha ndi kulira m'basi, muyenera kufananiza choletsa choyimitsa ndi cholepheretsa chogwira ntchito. Kwa dongosolo lomwe lili ndi Cd/Co = 3, cholepheretsa chogwira ntchito ndi 0.5 nthawi za Zdiff. Ndi kutha kawiri pa basi, dalaivala amawona katundu wofanana wa 0.25 nthawi za Zdiff; ndipo motero amachepetsa kugwedezeka kwa ma siginecha ndi malire a phokoso pazolowera zolandila (ngati woyendetsa wa LVDS agwiritsidwa ntchito). Dalaivala wa BLVDS amawongolera nkhaniyi powonjezera ma drive apano kuti akwaniritse voltagndi kusuntha pa zolowetsa zolandila.
Kuchedwa Kufalitsa
Kuchedwetsa kufalitsa (tPD = Zo × Co) ndi kuchedwa kwa nthawi kudzera pamzere wopatsira pautali wa unit. Zimatengera chikhalidwe cha impedance ndi khalidwe
luso la basi.
Kuchedwa Kufalitsa Mogwira
Pabasi yodzaza, mutha kuwerengera kuchedwerako kwa kufalitsa ndi equation iyi. Mutha kuwerengera nthawi yoti chizindikirocho chifalikire kuchokera kwa woyendetsa A kupita ku wolandila B monga tPDEFF × kutalika kwa mzere pakati pa dalaivala A ndi wolandila B.

BLVDS Technology mu Intel Devices

Pazida za Intel zothandizidwa, mawonekedwe a BLVDS amathandizidwa pamzere uliwonse kapena magawo I/ mabanki omwe amayendetsedwa ndi VCCIO ya 1.8 V (zida za Intel Arria 10 ndi Intel Cyclone 10 GX) kapena 2.5 V (zida zina zothandizira). M'mabanki a I/O awa, mawonekedwewa amathandizidwa pazikhomo za I/O koma osati pamawotchi odzipatulira kapena mawotchi otulutsa. Komabe, pazida za Intel Arria 10 ndi Intel Cyclone 10 GX, mawonekedwe a BLVDS amathandizidwa ndi mawotchi odzipereka omwe amagwiritsidwa ntchito ngati ma I/Os.

•  BLVDS transmitter imagwiritsa ntchito ma buffer awiri okhala ndi mbali imodzi yokhala ndi buffer yachiwiri yopangidwa ngati inverted.
•  Wolandila BLVDS amagwiritsa ntchito buffer yodzipatulira ya LVDS.

BLVDS I/O Buffers mu Zida ZothandiziraGwiritsani ntchito zolowetsa kapena zotulutsa zosiyanasiyana kutengera mtundu wa ntchito:

• Multidrop application-gwiritsani ntchito zolowetsa kapena zotulutsa kutengera ngati chipangizocho chimapangidwira dalaivala kapena wolandila.
• Multipoint application-chosungira chotulutsa ndi chosungira cholowetsa chimagawana mapini a I/O omwewo. Mufunika chizindikiro chothandizira (oe) kuti muwonetsere buffer ya LVDS pamene sichitumiza zizindikiro.
•  Osatsegula pa-chip series termination (RS OCT) pa buffer yotulutsa.
• Gwiritsani ntchito zopinga zakunja pamabafa otulutsa kuti mufanane ndi zopinga pa plug-in khadi.
• Osatsegula pa-chip differential termination (RD OCT) pamalo olowera mosiyanitsira chifukwa kuyimitsa mabasi nthawi zambiri kumakhazikitsidwa pogwiritsa ntchito zoletsa zoyimitsa zakunja malekezero onse a basi.

Miyezo ya I/O ya BLVDS Interface mu Intel FPGA Devices
Mutha kugwiritsa ntchito mawonekedwe a BLVDS pogwiritsa ntchito miyezo yoyenera ya I/O ndi zofunikira zamphamvu zamakono pazida za Intel zothandizidwa.
I/O Standard ndi Mbali Zothandizira BLVDS Interface mu Zida za Intel Zothandizira

1.  DIFFIO_TX pini sichirikiza zolandila zowona za LVDS.

Kuti mudziwe zambiri, onani zolemba za chipangizocho monga momwe zalembedwera mugawo logwirizana:

• Kuti mudziwe zambiri zamapini, onani pini-out ya chipangizocho files.
• Pazotsatira za I/O, onani mutu wa I/O wa kachipangizo kachipangizo.
•  Kuti mudziwe zambiri zamagetsi, tchulani dawunilodi ya chipangizocho kapena DC ndi zolemba zamasinthidwe.

Zambiri Zogwirizana

•  Intel Stratix 10 Pin-Out Files
•  Stratix V Pin-Out Files
• Stratix IV Pin-Out Files
•  Stratix III Chipangizo Pin-Out Files
•  Intel Arria 10 Chipangizo Pin-Out Files
•  Arria V Chipangizo Pin-Out Files
•  Arria II GX Chipangizo Pin-Out Files
• Intel Cyclone 10 GX Chipangizo Pin-Out Files
• Intel Cyclone 10 LP Chipangizo Pin-Out Files
• Cyclone V Chipangizo Pin-Out Files
•  Cyclone IV Chipangizo Pin-Out Files
• Cyclone III Chipangizo Pin-Out Files
• Intel MAX 10 Chipangizo Pin-Out Files
• Intel Stratix 10 General Purpose I/O User Guide
•  Ma I/O mu Zida za Stratix V
•  I/O Zomwe zili mu Stratix IV Chipangizo
•  Makhalidwe a Stratix III Chipangizo cha I/O
• Ma I/O mu Zida za Stratix V
•  I/O Zomwe zili mu Stratix IV Chipangizo
•  Makhalidwe a Stratix III Chipangizo cha I/O
•  I/O ndi High Speed ​​I/O mu Intel Arria 10 Devices
•  Ma I/O mu Zida za Arria V
• I/O Mbali mu Arria II Devices
•  I/O ndi High Speed ​​I/O mu Intel Cyclone 10 GX Devices
•  I/O ndi High Speed ​​I/O mu Intel Cyclone 10 LP Devices
• Ma I/O mu Zida za Cyclone V
• I/O Mbali mu Cyclone IV Devices
•  I/O Mbali mu Cyclone III Chipangizo Banja
• Intel MAX 10 General Purpose I/O User Guide
•  Intel Stratix 10 Device Datasheet
• Stratix V Chipangizo Datasheet
•  DC ndi Kusintha kwa Makhalidwe a Stratix IV Devices
•  Stratix III Device Datasheet: DC ndi Kusintha Makhalidwe
•  Intel Arria 10 Device Datasheet
•  Arria V Device Datasheet
• Device Datasheet ya Arria II Devices
• Intel Cyclone 10 GX Device Datasheet
•  Intel Cyclone 10 LP Device Datasheet
•  Cyclone V Chipangizo Datasheet
•  Cyclone IV Device Datasheet
• Chipangizo cha Cyclone III Device Datasheet
• Intel MAX 10 Device Datasheet

Kugwiritsa Ntchito Mphamvu kwa BLVDS

• Musanagwiritse ntchito kapangidwe kanu pachipangizocho, gwiritsani ntchito EPE yochokera ku Excel pa chipangizo chomwe mumagwiritsa ntchito kuti mupeze kuchuluka kwa kugwiritsa ntchito mphamvu kwa BLVDS I/O.
•  Pa mapini olowetsa ndi bidirectional, buffer yolowetsa ya BLVDS imakhala yoyatsidwa nthawi zonse. Buffer yolowetsa ya BLVDS imadya mphamvu ngati pali kusintha kwa basi (kwa mwachitsanzoample, ma transceivers ena akutumiza ndi kulandira deta, koma chipangizo cha Cyclone III sichimene chikufuna kulandira).
•  Ngati mugwiritsa ntchito BLVDS ngati chotchinga cholowera mu ma multidrop kapena ngati chotchingira chambiri pamapulogalamu ambiri, Intel imalimbikitsa kulowetsa mulingo wosinthira womwe umaphatikizapo zochitika zonse m'basi, osati zochitika zomwe zimapangidwira chipangizo cha Intel BLVDS cholowetsa buffer.

Example ya BLVDS I/O Data Kulowa mu EPE
Chiwerengerochi chikuwonetsa kulowa kwa BLVDS I/O mu Cyclone III EPE. Pamiyezo ya I/O kuti musankhe mu EPE ya zida zina za Intel zothandizidwa, tchulani zambiri zokhudzana nazo.Intel imalimbikitsa kuti mugwiritse ntchito Intel Quartus Prime Power Analyzer Tool kuti muyese molondola mphamvu ya BLVDS I/O mukamaliza kupanga. Chida cha Power Analyzer chimayerekeza mphamvu kutengera zomwe zidapangidwa pambuyo pomaliza ndi njira. Chida cha Power Analyzer chimagwiritsa ntchito zophatikizira zomwe zidalowetsedwa ndi ogwiritsa ntchito, zongoyerekeza, komanso zoyerekeza zomwe, kuphatikiza ndi zitsanzo zatsatanetsatane zadera, zimapereka kuyerekezera kwamphamvu kolondola kwambiri.
Zambiri Zogwirizana

• Mutu Wowunika Mphamvu, Intel Quartus Prime Pro Edition Handbook
  Amapereka zambiri za chida cha Intel Quartus Prime Pro Edition Power Analyzer cha Intel Stratix 10, Intel Arria 10, ndi mabanja a Intel Cyclone 10 GX.
• Mutu Analysis Chaputala, Intel Quartus Prime Standard Edition Handbook
  Amapereka zambiri za Intel Quartus Prime Standard Edition Power Analyzer chida cha Stratix V, Stratix IV, Stratix III, Arria V, Arria II, Intel Cyclone 10 LP, Cyclone V, Cyclone IV, Cyclone III LS, Cyclone III, ndi Intel. MAX 10 zida mabanja.
• Tsamba la Early Power Estimators (EPE) ndi Power Analyzer
  Amapereka zambiri za EPE ndi chida cha Intel Quartus Prime Power Analyzer.
• Kukhazikitsa Chiyankhulo cha Bus LVDS mu Mabanja a Chipangizo cha Intel FPGA patsamba 3
  Imalemba milingo ya I/O yoti musankhe mu EPE kuti muyerekeze kugwiritsa ntchito mphamvu kwa BLVDS.

BLVDS Design Example
Mapangidwe example amakuwonetsani momwe mungakhazikitsire buffer ya BLVDS I/O pazida zothandizidwa ndi cholinga chachikulu cha I/O (GPIO) IP cores mu pulogalamu ya Intel Quartus Prime.

•  Intel Stratix 10, Intel Arria 10, ndi Intel Cyclone 10 GX zida—gwiritsani ntchito GPIO Intel FPGA IP pachimake.
•  Zida za Intel MAX 10—gwiritsani ntchito GPIO Lite Intel FPGA IP pachimake.
•  Zida zina zonse zothandizira—gwiritsani ntchito ALTIOBUF IP core.

Mukhoza kukopera kapangidwe example kuchokera pa ulalo womwe uli muzambiri zofananira. Pachitsanzo cha BLVDS I/O, Intel imalimbikitsa zinthu zotsatirazi:

•  Khazikitsani GPIO IP pachimake mumayendedwe apawiri ndikuyatsa njira yosiyanitsira.
•  Perekani muyeso wa I/O pazikhomo ziwiri:
•  BLVDS-Intel Cyclone 10 LP, Cyclone IV, Cyclone III, ndi zida za Intel MAX 10.
•  Differential SSTL-2 Class I or Class II—Stratix V, Stratix IV, Stratix III, Arria V, Arria II, and Cyclone V zipangizo.
• Zosiyana za SSTL-18 Class I kapena Class II—Intel Stratix 10, Intel Arria 10, ndi zida za Intel Cyclone 10 GX.

Zolowetsa kapena Zotulutsa Zimagwira Ntchito Panthawi Yolemba ndi Kuwerenga

• Doko la oe limalandira siginecha ya oe kuchokera pachimake cha chipangizo kuti athe kuletsa kapena kuletsa ma buffer okhala ndi mbali imodzi.
•  Sungani siginecha ya oe yotsika kuti mutchule katatu zomwe zimatuluka panthawi yowerenga.
•  Ntchito ya NDI chipata ndikuletsa chizindikiro chopatsirana kuti chisabwererenso pachimake cha chipangizocho. Mabafa olowetsa masiyanidwe amayatsidwa nthawi zonse.

Zambiri Zogwirizana

•  I/O Buffer (ALTIOBUF) IP Core User Guide
•  GPIO IP Core User Guide
•  Maupangiri Othandizira a Intel MAX 10 I/O
• Chiyambi cha Intel FPGA IP Cores
• Design Exampza AN522

Amapereka kapangidwe ka Intel Quartus Prime exampzogwiritsidwa ntchito muzolemba izi.
Design Example Maupangiri a Intel Stratix 10 Devices
Izi zikugwira ntchito pazida za Intel Stratix 10 zokha. Onetsetsani kuti mukugwiritsa ntchito GPIO Intel FPGA IP core.

1. Pangani GPIO Intel FPGA IP pachimake chomwe chitha kuthandizira kulowetsamo ndi kutulutsa buffer:
   • a. Yambitsani GPIO Intel FPGA IP pachimake.
   • b. Mu Data Direction, sankhani Bidir.
   • c. Mu Data wide, lowetsani 1.
   • d. Yatsani Gwiritsani ntchito buffer yosiyana.
   • e. Mu Register mode, sankhani chilichonse.
2. Lumikizani ma module ndi madoko olowera ndi otuluka monga momwe zikuwonekera pachithunzichi:
   Zolowetsa ndi Zotuluka Connection Example kwa Intel Stratix 10 Devices
3. Mu Assignment Editor, perekani mulingo woyenera wa I/O monga momwe zasonyezedwera pachithunzichi. Mukhozanso kukhazikitsa mphamvu zamakono ndi zosankha zakupha. Kupanda kutero, pulogalamu ya Intel Quartus Prime imatengera zosintha zosasinthika.
   Ntchito ya BLVDS I/O mu Intel Quartus Prime Assignment Editor ya Intel Stratix 10 Devices
4. Sungani ndikuchita zoyeserera ndi ModelSim* - Intel FPGA Edition software.

Zambiri Zogwirizana

• ModelSim - Intel FPGA Edition Software Support
  Amapereka zambiri za pulogalamu ya ModelSim - Intel FPGA Edition ndipo ili ndi maulalo osiyanasiyana pamitu monga kukhazikitsa, kugwiritsa ntchito, ndi kuthetsa mavuto.
• Miyezo ya I/O ya BLVDS Interface mu Intel FPGA Devices patsamba 7
  Imalemba mapini ndi miyezo ya I/O yomwe mungagawire pamanja pazida za Intel FPGA zogwiritsa ntchito BLVDS.
• Design Exampza AN522
  Amapereka kapangidwe ka Intel Quartus Prime exampzogwiritsidwa ntchito muzolemba izi.

Design Example Maupangiri a Intel Arria 10 Devices
Izi zikugwira ntchito pazida za Intel Arria 10 zogwiritsa ntchito Intel Quartus Prime Standard Edition kokha. Onetsetsani kuti mukugwiritsa ntchito GPIO Intel FPGA IP core.

1. Tsegulani StratixV_blvds.qar file kuti mulowetse mawonekedwe a Stratix V examplembani pulogalamu ya Intel Quartus Prime Standard Edition.
2. Samutsirani kapangidwe kakaleample kugwiritsa ntchito GPIO Intel FPGA IP pachimake:
   • a. Pa menyu, sankhani Pulojekiti ➤ Sinthani Zowonjezera IP.
   • b. Dinani kawiri chinthu cha "ALIOBUF".
     Zenera la MegaWizard Plug-In Manager la ALTIOBUF IP core likuwonekera.
   • c. Zimitsani projekiti ya Match/zosasintha.
   • d. Mu banja lazida zomwe zasankhidwa pano, sankhani Arria 10.
   • e. Dinani Malizani ndiyeno dinani Malizani kachiwiri.
   • f. M'bokosi la zokambirana lomwe likuwoneka, dinani Chabwino.
     Pulogalamu ya Intel Quartus Prime Pro Edition imachita kusamuka ndikuwonetsa GPIO IP parameter editor.
3. Konzani GPIO Intel FPGA IP pachimake kuti muthandizire kulowetsa kwapawiri ndi kutulutsa buffer:
   • a. Mu Data Direction, sankhani Bidir.
   • b. Mu Data wide, lowetsani 1.
   • c. Yatsani Gwiritsani ntchito buffer yosiyana.
   • d. Dinani Malizani ndikupanga IP core.
4. Lumikizani ma module ndi madoko olowera ndi otuluka monga momwe zikuwonekera pachithunzichi:
   Zolowetsa ndi Zotuluka Connection Example kwa Intel Arria 10 Devices
5. Mu Assignment Editor, perekani mulingo woyenera wa I/O monga momwe zasonyezedwera pachithunzichi. Mukhozanso kukhazikitsa mphamvu zamakono ndi zosankha zakupha. Kupanda kutero, pulogalamu ya Intel Quartus Prime Standard Edition imatengera zosintha za Intel Arria 10—Differential SSTL-18 Class I or Class II I/O standard.
   Ntchito ya BLVDS I/O mu Intel Quartus Prime Assignment Editor ya Intel Arria 10 DevicesZindikirani:
   Pazida za Intel Arria 10, mutha kugawa pamanja p ndi n pin malo a LVDS mapini ndi Assignment Editor.
6. Phatikizani ndikuchita zoyeserera ndi pulogalamu ya ModelSim - Intel FPGA Edition.

Zambiri Zogwirizana

• ModelSim - Intel FPGA Edition Software Support
  Amapereka zambiri za pulogalamu ya ModelSim - Intel FPGA Edition ndipo ili ndi maulalo osiyanasiyana pamitu monga kukhazikitsa, kugwiritsa ntchito, ndi kuthetsa mavuto.
• Miyezo ya I/O ya BLVDS Interface mu Intel FPGA Devices patsamba 7
  Imalemba mapini ndi miyezo ya I/O yomwe mungagawire pamanja pazida za Intel FPGA zogwiritsa ntchito BLVDS.
• Design Exampza AN522
  Amapereka kapangidwe ka Intel Quartus Prime exampzogwiritsidwa ntchito muzolemba izi.

Design Example Maupangiri a Intel MAX 10 Devices
Izi zikugwira ntchito pazida za Intel MAX 10 zokha. Onetsetsani kuti mumagwiritsa ntchito GPIO Lite Intel FPGA IP core.

1. Pangani GPIO Lite Intel FPGA IP pachimake chomwe chitha kuthandizira kulowetsa ndi kutulutsa buffer:
   • a. Yambitsani GPIO Lite Intel FPGA IP pachimake.
   • b. Mu Data Direction, sankhani Bidir.
   • c. Mu Data wide, lowetsani 1.
   • d. Yatsani Gwiritsani ntchito buffer yosiyana.
   • e. Mu Register mode, sankhani Bypass.
2. Lumikizani ma module ndi madoko olowera ndi otuluka monga momwe zikuwonekera pachithunzichi:
    Zolowetsa ndi Zotuluka Connection Example kwa Intel MAX 10 Devices
3. Mu Assignment Editor, perekani mulingo woyenera wa I/O monga momwe zasonyezedwera pachithunzichi. Mukhozanso kukhazikitsa mphamvu zamakono ndi zosankha zakupha. Kupanda kutero, pulogalamu ya Intel Quartus Prime imatengera zosintha zosasinthika.
   Ntchito ya BLVDS I/O mu Intel Quartus Prime Assignment Editor ya Intel MAX 10 Devices
4. Phatikizani ndikuchita zoyeserera ndi pulogalamu ya ModelSim - Intel FPGA Edition.

Zambiri Zogwirizana

• ModelSim - Intel FPGA Edition Software Support
  Amapereka zambiri za pulogalamu ya ModelSim - Intel FPGA Edition ndipo ili ndi maulalo osiyanasiyana pamitu monga kukhazikitsa, kugwiritsa ntchito, ndi kuthetsa mavuto.
• Miyezo ya I/O ya BLVDS Interface mu Intel FPGA Devices patsamba 7
  Imalemba mapini ndi miyezo ya I/O yomwe mungagawire pamanja pazida za Intel FPGA zogwiritsa ntchito BLVDS.
• Design Exampza AN522
  Amapereka kapangidwe ka Intel Quartus Prime exampzogwiritsidwa ntchito muzolemba izi.

Design Example Maupangiri a Zida Zonse Zothandizira Kupatula Intel Arria 10, Intel Cyclone 10 GX, ndi Intel MAX 10

Masitepewa amagwira ntchito pazida zonse zothandizira kupatula Intel Arria 10, Intel Cyclone 10 GX, ndi Intel MAX 10. Onetsetsani kuti mumagwiritsa ntchito ALTIOBUF IP core.

1.  Pangani maziko a IP a ALTIOBUF omwe atha kuthandizira kulowetsa kwapawiri ndi kutulutsa buffer:
   • a. Yambitsani ALTIOBUF IP core.
   • b. Konzani gawoli ngati buffer yolowera pawiri.
   • c. Mu Ziwerengero zotani zomwe ziyenera kukhazikitsidwa, lowetsani 1.
   • d. Yatsani Gwiritsani ntchito mosiyanasiyana.
2. Lumikizani ma module ndi madoko olowera ndi otuluka monga momwe zikuwonekera pachithunzichi:
    Zolowetsa ndi Zotuluka Connection Example kwa Zida Zonse Zothandizira Kupatula Intel Arria 10, Intel Cyclone 10 GX, ndi Intel MAX 10 Devices
3. Mu Assignment Editor, perekani mulingo woyenera wa I/O monga momwe zasonyezedwera pachithunzichi molingana ndi chipangizo chanu. Mukhozanso kukhazikitsa mphamvu zamakono ndi zosankha zakupha. Kupanda kutero, pulogalamu ya Intel Quartus Prime imatengera zosintha zosasinthika.
   • Zida za Intel Cyclone 10 LP, Cyclone IV, Cyclone III, ndi Cyclone III LS—BLVDS I/O muyezo ku bidirectional p ndi n pin monga momwe zasonyezedwera pachithunzi chotsatirachi.
   • Stratix V, Stratix IV, Stratix III, Arria V, Arria II, ndi Cyclone V zipangizo—Differential SSTL-2 Class Class I or Class II I/O standard.
     Ntchito ya BLVDS I/O mu Intel Quartus Prime Assignment EditorZindikirani: Mutha kugawira pamanja malo onse a p ndi n pin pachida chilichonse chothandizidwa ndi Assignment Editor. Pazida zothandizidwa ndi mapini omwe mungagawire pamanja, tchulani zambiri zokhudzana nazo.
4. Phatikizani ndikuchita zoyeserera ndi pulogalamu ya ModelSim - Intel FPGA Edition.

Exampzotsatira za Functional Simulation Results
Chizindikiro cha oe chikatsimikiziridwa, BLVDS imakhala mumayendedwe olembera. Chizindikiro cha oe chikachotsedwa, BLVDS imakhala mumayendedwe owerengera.Zindikirani:
Poyerekeza pogwiritsa ntchito Verilog HDL, mutha kugwiritsa ntchito blvds_tb.v testbench, yomwe imaphatikizidwa ndi kapangidwe kake kakale.ample.
Zambiri Zogwirizana

• ModelSim - Intel FPGA Edition Software Support
  Amapereka zambiri za pulogalamu ya ModelSim - Intel FPGA Edition ndipo ili ndi maulalo osiyanasiyana pamitu monga kukhazikitsa, kugwiritsa ntchito, ndi kuthetsa mavuto.
• Miyezo ya I/O ya BLVDS Interface mu Intel FPGA Devices patsamba 7
  Imalemba mapini ndi miyezo ya I/O yomwe mungagawire pamanja pazida za Intel FPGA zogwiritsa ntchito BLVDS.
• Design Exampza AN522
  Amapereka kapangidwe ka Intel Quartus Prime exampzogwiritsidwa ntchito muzolemba izi.

Kusanthula Kachitidwe

Kusanthula kwa magwiridwe antchito a Multipoint BLVDS kukuwonetsa momwe mabasi amayimitsira, kutsitsa, mawonekedwe oyendetsa ndi olandila, komanso malo omwe wolandila kuchokera kwa dalaivala pamakina. Mutha kugwiritsa ntchito mawonekedwe ophatikizidwa a BLVDSampkusanthula magwiridwe antchito a multipoint application:

•  Cyclone III BLVDS mapangidwe example - kapangidwe kakeample imagwira ntchito pazida zonse za Stratix, Arria, ndi Cyclone. Kwa banja la chipangizo cha Intel Arria 10 kapena Intel Cyclone 10 GX, muyenera kusamutsa kapangidwe kake.amplembani ku banja la chipangizocho kaye musanagwiritse ntchito.
• Intel MAX 10 BLVDS mapangidwe example - kapangidwe kakeample imagwira ntchito ku banja la chipangizo cha Intel MAX 10.
• Intel Stratix 10 BLVDS mapangidwe example - kapangidwe kakeampLe imagwira ntchito kubanja la chipangizo chaIntel Stratix 10.

Zindikirani:
Kusanthula kachitidwe ka ma multipoint BLVDS mu gawoli kutengera kayesedwe ka Cyclone III BLVDS input/output buffer information specification (IBIS) mu HyperLynx*.
Intel ikulimbikitsa kuti mugwiritse ntchito mitundu iyi ya Intel IBIS poyerekezera:

• Zida za Stratix III, Stratix IV, ndi Stratix V—chitsanzo chapadera cha Differential SSTL-2 IBIS
• Intel Stratix 10, Intel Arria 10(2) ndi Intel Cyclone 10 GX zida:
  •  Zotulutsa zotulutsa—Zosiyana za SSTL-18 IBIS
  • Lowetsani chitetezo—chitsanzo cha LVDS IBIS

Zambiri Zogwirizana

• Tsamba la Intel FPGA IBIS Model
  Amapereka kutsitsa kwamitundu yazida za Intel FPGA.
•  Design Exampza AN522
  Amapereka kapangidwe ka Intel Quartus Prime exampzogwiritsidwa ntchito muzolemba izi.

Kukonzekera Kwadongosolo

 Multipoint BLVDS yokhala ndi Cyclone III BLVDS Transceivers
Chiwerengerochi chikuwonetsa schematic ya multipoint topology yokhala ndi ma transceivers khumi a Cyclone III BLVDS (otchedwa U1 mpaka U10).Njira yodutsa mabasi imaganiziridwa kuti ili ndi izi:

•  Mzere wa mzere
•  Kulepheretsa kwa 50 Ω
• Khalidwe lamphamvu la 3.6 pF pa inchi
•  Kutalika kwa mainchesi 10
• Mitundu ya Intel Arria 10 IBIS ndi yoyambirira ndipo sapezeka pamtundu wa Intel IBIS web tsamba. Ngati mukufuna mitundu yoyambirira ya Intel Arria 10 IBIS, funsani Intel.
• Masiyanidwe a mabasi amasiyana pafupifupi 100 Ω
•  Mpata pakati pa transceiver iliyonse ndi inchi imodzi
• Basi yoyimitsidwa mbali zonse ziwiri ndi termination resistor RT

• Mphamvu yagalimoto yofikira 12 mA
• Zokonda zochedwa pang'onopang'ono mwachikhazikitso
• Pini mphamvu ya transceiver iliyonse ya 6 pF
•  Stub pa transceiver iliyonse ya BLVDS ndi 1-inch microstrip ya chikhalidwe cha 50 Ω ndi mphamvu ya 3 pF pa inchi.
•  Mphamvu yolumikizira (cholumikizira, pad, ndi kudzera mu PCB) ya transceiver iliyonse kupita ku basi imaganiziridwa kuti ndi 2 pF.
• Mphamvu yonse ya katundu aliyense ndi pafupifupi 11 pF

Pamalo olemetsa a 1 inchi, mphamvu yogawidwa ndi 11 pF pa inchi. Kuchepetsa kusinkhasinkha komwe kumachitika chifukwa cha ma stubs, komanso kuchepetsa ma sign omwe akutuluka
dalaivala, cholepheretsa chofanana ndi 50 Ω resistor RS chimayikidwa pakupanga kwa transceiver iliyonse.

Kuyimitsa Mabasi
Kulepheretsa kogwira bwino kwa basi yodzaza ndi 52 Ω ngati mungalowe m'malo mwa mawonekedwe a basi ndi mphamvu yogawidwa pautali wagawo la kukhazikitsidwa kuti mugwirizane ndi kusiyana kwa impedance equation. Kuti mutsimikizire kukhulupirika kwa siginecha, muyenera kufanana ndi RT ndi 52 Ω. Ziwerengero zotsatirazi zikuwonetsa zotsatira za kufananiza, kuchepera, komanso kutha kwa ma waveform (VID) pamapini olowetsa olandila. Mtengo wa data ndi 100 Mbps. M'ziwerengerozi, kutha kwapansi (RT = 25 Ω) kumabweretsa kusinkhasinkha ndi kuchepetsa kwambiri phokoso la phokoso. Nthawi zina, kuthetsedwa kumaphwanya malire olandila (VTH = ± 100 mV). RT ikasinthidwa kukhala 50 Ω, pamakhala phokoso lalikulu pokhudzana ndi VTH ndipo chiwonetserocho chimakhala chonyozeka.

Zotsatira za Kuyimitsa Mabasi (Oyendetsa mu U1, Wolandira mu U2)
Pachiwerengerochi, U1 imagwira ntchito ngati transmitter ndipo U2 kupita ku U10 ndi omwe amalandila.

Zotsatira za Kuyimitsa Mabasi (Oyendetsa mu U1, Wolandira mu U10)
Pachiwerengerochi, U1 imagwira ntchito ngati transmitter ndipo U2 kupita ku U10 ndi omwe amalandila.

Zotsatira za Kuyimitsa Mabasi (Oyendetsa mu U5, Wolandira mu U6)
Pachithunzichi, U5 ndiye wotumiza ndipo ena onse ndi olandila.

Zotsatira za Kuyimitsa Mabasi (Oyendetsa mu U5, Wolandira mu U10)
Pachithunzichi, U5 ndiye wotumiza ndipo ena onse ndi olandila.Malo achibale a dalaivala ndi wolandira m'basi amakhudzanso khalidwe lachidziwitso cholandira. Wolandira pafupi kwambiri ndi dalaivala amakumana ndi vuto lalikulu kwambiri chifukwa pamalo ano, m'mphepete mwake ndiwothamanga kwambiri. Izi zimaipiraipira pamene dalaivala ali pakati pa basi.
Za example, yerekezerani Chithunzi 16 patsamba 20 ndi Chithunzi 18 patsamba 21. VID pa wolandila U6 (woyendetsa pa U5) akuwonetsa kulira kokulirapo kuposa kolandila U2 (woyendetsa pa U1). Kumbali inayi, mlingo wa m'mphepete umachepetsedwa pamene wolandirayo ali kutali ndi dalaivala. Nthawi yokwera kwambiri yolembedwa ndi 1.14 ns ndi dalaivala yemwe ali kumapeto kwa basi (U1) ndi wolandila kumapeto kwina (U10).

Kutalika kwa Stub
Kutalika kwa stub sikungowonjezera nthawi yowuluka kuchokera kwa dalaivala kupita kwa wolandila, komanso kumabweretsa mphamvu yokulirapo, yomwe imayambitsa kuwunikira kwakukulu.

Zotsatira za Kuchulukitsa Kwautali wa Stub (Driver mu U1, Receiver mu U10)
Chiwerengerochi chikufanizira VID ku U10 pamene kutalika kwa stub kumawonjezeka kuchoka pa inchi imodzi kufika mainchesi awiri ndipo dalaivala ali pa U1.

Kuchotsedwa kwa Stub
Muyenera kufananiza dalaivala impedance ndi stub characteristic impedance. Kuyika makina oletsa kuletsa RS pamayendedwe a dalaivala amachepetsa kwambiri zotsatira zoyipa za mzere wopatsirana wobwera chifukwa cha zikwatu zazitali komanso mitengo yothamanga. Kuphatikiza apo, RS ikhoza kusinthidwa kuti ichepetse VID kuti ikwaniritse zomwe wolandila.

Zotsatira za Stub Termination (Driver mu U1, Receiver mu U2 ndi U10)
Chiwerengerochi chikufanizira VID ku U2 ndi U10 pomwe U1 ikutumiza.

Dalaivala Slew Rate
Kupha mwachangu kumathandizira kukonza nthawi yokwera, makamaka pa wolandila kutali kwambiri ndi dalaivala. Komabe, kupha kofulumira kumakulitsanso kulira chifukwa cha kusinkhasinkha.

Zotsatira za Driver Edge Rate (Driver mu U1, Receiver mu U2 ndi U10)
Chithunzichi chikuwonetsa kuchuluka kwa oyendetsa galimoto. Kuyerekeza kumapangidwa pakati pa kupha pang'onopang'ono komanso mwachangu ndi mphamvu ya 12 mA pagalimoto. Dalaivala ali ku U1 ndipo mawonekedwe osiyana pa U2 ndi U10 amawunikidwa.

Kugwira Ntchito Kwadongosolo lonse

Chiwerengero chapamwamba kwambiri cha deta chothandizidwa ndi multipoint BLVDS chimatsimikiziridwa poyang'ana chithunzi cha diso la wolandira kutali kwambiri kuchokera kwa dalaivala. Pamalo awa, chizindikiro chopatsirana chimakhala chocheperako kwambiri ndipo chimakhudza kutseguka kwa maso. Ngakhale mtundu wa siginecha yomwe walandilidwa ndi cholinga cha phokoso laphokoso zimadalira zomwe zagwiritsidwa ntchito, kutseguka kwa maso, kumakhala bwinoko. Komabe, muyenera kuyang'ananso wolandila pafupi ndi dalaivala, chifukwa zotsatira za mzere wotumizira zimakhala zoipitsitsa ngati wolandila ali pafupi ndi dalaivala.
Chithunzi 23. Diso Digram pa 400 Mbps (Driver mu U1, Receiver mu U2 ndi U10)
Chithunzichi chikuwonetsa zojambula zamaso pa U2 (mpindi wofiyira) ndi U10 (njira yabuluu) pamlingo wa data pa 400 Mbps. Kuwombera kosasintha kwa 1% kwa nthawi ya unit kumaganiziridwa poyerekezera. Dalaivala ali pa U1 wokhala ndi mphamvu zokhazikika komanso zosintha zakupha. Basi yadzaza kwathunthu ndi RT = 50 Ω. Diso laling'ono kwambiri lili ku U10, komwe kuli kutali kwambiri ndi U1. Kutalika kwa diso sampkutsogozedwa ndi 0.5 unit interval ndi 692 mV ndi 543 mV kwa U2 ndi U10, motsatana. Pali phokoso lalikulu pokhudzana ndi VTH = ± 100 mV pazochitika zonsezi.

Mbiri Yokonzanso Zolemba za AN 522: Kugwiritsa Ntchito Ma Bus LVDS Interface mu Mabanja a Chipangizo cha Intel FPGA

Zolemba / Zothandizira

intel AN 522 Kukhazikitsa Mabasi LVDS Chiyankhulo mu Mabanja Othandizira a FPGA Chipangizo [pdf] Buku Logwiritsa Ntchito AN 522 Kugwiritsa Ntchito Ma Bus LVDS Interface mu Mabanja Othandizira a FPGA, AN 522, Kukhazikitsa Mabasi LVDS Interface mu Mabanja Othandizira a FPGA Chipangizo, Chiyankhulo mu Mabanja Othandizira FPGA Chipangizo, FPGA Chipangizo Mabanja

Maumboni

• Buku Logwiritsa Ntchito