intel AN 522 Yana Aiwatar da Motar LVDS Bus a cikin Iyalan Na'urar FPGA

Bus LVDS (BLVDS) yana ƙara ƙarfin sadarwar LVDS-zuwa-aya zuwa daidaitawar maki mai yawa. Multipoint BLVDS yana ba da ingantaccen bayani don aikace-aikacen jirgin baya da yawa.

Tallafin Aiwatar da BLVDS a cikin Na'urorin Intel FPGA

Kuna iya aiwatar da mu'amalar BLVDS a cikin waɗannan na'urorin Intel ta amfani da ƙa'idodin I/O da aka jera.

Lura:
Ƙarfin tuƙi mai shirye-shirye da fasalin ƙimar kashewa a cikin waɗannan na'urori suna ba ku damar keɓance tsarin makirufo don iyakar aiki. Don ƙayyade matsakaicin adadin bayanan da aka goyan baya, yi simulation ko auna dangane da takamaiman saitin tsarin ku da aikace-aikacenku.
Farashin BLVDSview shafi na 4
Fasahar BLVDS a cikin Na'urorin Intel akan shafi na 6
Amfanin Wutar Lantarki na BLVDS akan shafi na 9
BLVDS Design Example a shafi na 10
Binciken Ayyuka a shafi na 17
Tarihin Bita na Daftarin aiki don AN 522: Aiwatar da Motar LVDS ta Bus a cikin Iyalan Na'urar Intel FPGA masu Goyan bayan shafi na 25
Bayanai masu alaƙa
Ka'idodin I/O don Interface BLVDS a cikin na'urorin Intel FPGA akan shafi na 7

Farashin BLVDSview

Tsarin BLVDS na al'ada da yawa ya ƙunshi nau'i-nau'i na watsawa da masu karɓa (masu ɗauka) waɗanda ke haɗe da bas.
Multipoint BLVDSƘimar da ke cikin adadi na baya yana samar da sadarwar rabin-duplex na biyu yayin da ake rage yawan haɗin haɗin gwiwa. Duk wani mai watsawa zai iya ɗaukar matsayin mai watsawa, tare da ragowar masu karɓa suna aiki azaman masu karɓa (mai watsawa ɗaya ne kawai zai iya aiki a lokaci ɗaya). Ikon zirga-zirgar bas, ko dai ta hanyar yarjejeniya ko kayan aikin kayan aiki yawanci ana buƙata don gujewa jayayyar direba akan bas. Ayyukan BLVDS multipoint yana tasiri sosai ta hanyar ɗaukar nauyi da ƙarewa akan bas ɗin.
Abubuwan Tsara
Kyakkyawan ƙira mai mahimmanci dole ne yayi la'akari da nauyi mai ƙarfi da ƙarewa akan bas don samun ingantaccen sigina. Kuna iya rage ƙarfin ƙarfin lodi ta zaɓin transceiver tare da ƙarancin ƙarfin fil, mai haɗawa tare da ƙarancin ƙarfin ƙarfi, da kiyaye tsayin stub gajere. Ofaya daga cikin la'akari da ƙira mai yawa BLVDS shine ingantacciyar rarrabuwar bambance-bambancen bas ɗin da aka ɗora, wanda ake magana da shi a matsayin ingantacciyar ƙarfi, da jinkirin yaduwa ta cikin bas. Sauran la'akari da ƙira na BLVDS masu yawa sun haɗa da rashin aminci da son rai, nau'in haɗin kai da fitin-fiti, shimfidar bus ɗin PCB, da ƙayyadaddun ƙimar ƙimar direba.
Tasirin Tasiri
Ingantacciyar impedance ya dogara ne akan alamar alamar bas ɗin Zo da ɗaukar nauyi akan bas ɗin. Masu haɗawa, stub akan katin filogi, marufi, da ƙarfin shigar da mai karɓa duk suna ba da gudummawa ga ɗaukar nauyi, wanda ke rage tasirin bas ɗin mai inganci.
Equation 1. Ingantacciyar Ƙa'idar Tasirin Bambanci
Yi amfani da wannan ma'auni don kimanta tasirin tasiri mai tasiri na bas ɗin da aka ɗora (Zeff).Inda:

• Zdiff (Ω) ≈ 2 × Zo = bambance-bambancen halayen motar bas
•  Co (pF/inch) = iyawar halayyar kowane tsayin raka'a na bas
• CL (pF) = ƙarfin kowane kaya
•  N = adadin lodi akan bas
•  H (inch) = d × N = jimlar tsawon motar bas
•  d (inch) = tazara tsakanin kowane katin toshe
•  Cd (pF/inch) = CL/d = iyawar da aka rarraba kowane tsayin raka'a a cikin motar bas

Ƙara ƙarfin ƙarfin lodi ko tazarar kusanci tsakanin katunan toshewa yana rage tasiri mai tasiri. Don inganta aikin tsarin, yana da mahimmanci a zaɓi ƙaramin ƙarfin ƙarfin aiki da mai haɗawa. Rike kowane tsayin kumfa mai karɓa tsakanin mai haɗawa da fitin I/O transceiver gajere gwargwadon yiwuwa.
Matsakaicin Tasirin Tasirin Tsare-tsaren Tsare-tsare Tsakanin Cd/Co
Wannan adadi yana nuna tasirin ƙarfin da aka rarraba akan ingantaccen tasiri mai tasiri.Ana buƙatar ƙarewa a kowane ƙarshen bas ɗin, yayin da bayanai ke gudana a bangarorin biyu. Don rage tunani da ringi a kan bas ɗin, dole ne ku dace da mai tsayayyar ƙarewa zuwa ingantaccen impedance. Don tsarin tare da Cd/Co = 3, tasiri mai tasiri shine sau 0.5 na Zdiff. Tare da ƙare sau biyu akan bas ɗin, direba yana ganin nauyin daidai 0.25 na Zdiff; don haka yana rage siginonin jujjuyawar da keɓancewar hayaniyar hayaniyar a cikin abubuwan shigar da mai karɓa (idan ana amfani da madaidaicin direban LVDS). Direban BLVDS yana magance wannan batu ta hanyar ƙara ƙarfin halin yanzu don cimma irin wannan voltage lilo a abubuwan shigar da mai karɓa.
Jinkirin Yaduwa
Jinkirin yaduwa (tPD = Zo × Co) shine jinkirin lokacin ta layin watsa kowane tsayin raka'a. Ya dogara da sifa da sifa da sifa
capacitance na bas.
Ingantacciyar Jinkirin Yadawa
Don bas ɗin da aka ɗora, zaku iya ƙididdige ingantaccen jinkirin yadawa tare da wannan ma'auni. Kuna iya lissafin lokacin siginar don yaduwa daga direba A zuwa mai karɓa B azaman tPDEFF × tsawon layin tsakanin direban A da mai karɓar B.

Fasahar BLVDS a cikin Na'urorin Intel

A cikin na'urorin Intel da ke da tallafi, ana samun tallafin BLVDS interface a kowace jere ko shafi I/bankunan da VCCIO na 1.8 V (Intel Arria 10 da Intel Cyclone 10 GX na'urorin) ko 2.5 V (sauran na'urori masu goyan baya). A cikin waɗannan bankunan I/O, ana samun goyan bayan mu'amalar akan nau'ikan I/O daban-daban amma ba akan shigar da agogon da aka keɓe ba ko fitattun fitattun agogo. Koyaya, a cikin na'urorin Intel Arria 10 da Intel Cyclone 10 GX, ana samun goyan bayan BLVDS interface akan fitattun agogo waɗanda ake amfani da su azaman I/Os na gabaɗaya.

•  Mai watsawa na BLVDS yana amfani da buffers masu ƙarewa guda biyu tare da buffer na biyu wanda aka tsara azaman jujjuyawar.
•  Mai karɓar BLVDS yana amfani da keɓaɓɓen shigar da shigar LVDS.

BLVDS I/O Buffers a cikin Na'urori masu TallafiYi amfani da shigarwa daban-daban ko abubuwan fitarwa dangane da nau'in aikace-aikacen:

• Multidrop aikace-aikace-amfani da shigarwa ko buffer fitarwa dangane da ko an yi nufin na'urar don aikin direba ko mai karɓa.
• Aikace-aikacen Multipoint — buffer na fitarwa da buffer ɗin shigarwa suna raba madaidaitan I/O iri ɗaya. Kuna buƙatar siginar kunna fitarwa (oe) don daidaita madaidaicin fitarwa na LVDS lokacin da baya aika sigina.
•  Kar a ba da damar ƙarewar jerin kan-chip (RS OCT) don buffer fitarwa.
• Yi amfani da resistors na waje a maɓuɓɓugan fitarwa don samar da madaidaicin matsi da taurin kan katin filogi.
• Kar a ba da damar ƙarewar bambancin kan-chip (RD OCT) don madaidaicin shigar da buffer saboda ƙarewar bas yawanci ana aiwatar da shi ta amfani da masu tsayayyar ƙarewa na waje a ƙarshen bas ɗin.

Ka'idojin I/O don Interface BLVDS a cikin Na'urorin FPGA na Intel
Kuna iya aiwatar da ƙirar BLVDS ta amfani da matakan I/O masu dacewa da buƙatun ƙarfin halin yanzu don na'urorin Intel masu goyan baya.
Matsayin I/O da Taimako na Fasaloli don Interface BLVDS a cikin Na'urorin Intel masu Tallafi

1.  DIFFIO_TX fil baya goyan bayan masu karɓa na gaskiya na LVDS.

Don ƙarin bayani, koma zuwa takaddun na'urar kamar yadda aka jera a sashin bayanin da ke da alaƙa:

• Don bayanin ayyukan fil, koma zuwa fitin na'urar files.
• Don fasalulluka na I/O, koma zuwa babin I/O na littafin jagora.
•  Don ƙayyadaddun wutar lantarki, koma zuwa takaddar bayanan na'urar ko DC da daftarin fasali.

Bayanai masu alaƙa

•  Intel Stratix 10 Pin-Out Files
•  Stratix V Pin-Out Files
• Stratix IV Pin-Out Files
•  Na'urar Stratix III Pin-Out Files
•  Intel Arria 10 Na'urar Pin-Out Files
•  Arria V Na'urar Pin-Out Files
•  Arria II GX Na'urar Pin-Out Files
• Intel Cyclone 10 GX Na'urar Pin-Out Files
• Intel Cyclone 10 LP Na'urar Pin-Out Files
• Cyclone V Na'urar Pin-Out Files
•  Cyclone IV Na'urar Pin-Out Files
• Cyclone III Na'urar Pin-Out Files
• Intel MAX 10 Na'urar Pin-Out Files
• Intel Stratix 10 Babban Manufar I/O Jagorar Mai Amfani
•  Siffofin I/O a cikin na'urorin Stratix V
•  Siffofin I/O a cikin na'urar Stratix IV
•  Stratix III Na'urar I/O Features
• Siffofin I/O a cikin na'urorin Stratix V
•  Siffofin I/O a cikin na'urar Stratix IV
•  Stratix III Na'urar I/O Features
•  I/O da Babban Gudun I/O a cikin na'urorin Intel Arria 10
•  Siffofin I/O a cikin na'urorin Arria V
• Siffofin I/O a cikin na'urorin Arria II
•  I/O da Babban Gudun I/O a cikin na'urorin Intel Cyclone 10 GX
•  I/O da Babban Gudun I/O a cikin na'urorin Intel Cyclone 10 LP
• Siffofin I/O a cikin na'urorin Cyclone V
• Siffofin I/O a cikin na'urorin Cyclone IV
•  Siffofin I/O a cikin Iyalin Na'urar Cyclone III
• Intel MAX 10 Babban Manufar I/O Jagorar mai amfani
•  Bayanan Bayani na Na'urar Intel Stratix 10
• Bayanan Bayani na Na'urar Stratix V
•  DC da Halayen Canjawa don na'urorin Stratix IV
•  Bayanan na'urar Stratix III: DC da Halayen Canjawa
•  Bayanan Bayani na Na'urar Intel Arria 10
•  Takardar bayanan Na'urar Arria V
• Takardar bayanan Na'urar don Na'urorin Arria II
• Bayanan Bayani na Na'urar Intel Cyclone 10 GX
•  Bayanan Bayani na Na'urar Intel Cyclone 10 LP
•  Takardar bayanan Na'urar Cyclone V
•  Takardar bayanan Na'urar Cyclone IV
• Takardar bayanan Na'urar Cyclone III
• Takardar bayanan Na'urar Intel MAX 10

Amfanin Wutar Lantarki na BLVDS

• Kafin aiwatar da ƙirar ku a cikin na'urar, yi amfani da EPE na tushen Excel don na'urar da aka goyan baya da kuke amfani da ita don samun ƙimar ƙimar ƙarfin BLVDS I/O.
•  Don shigarwa da filaye biyu, ana kunna buffer shigar da BLVDS koyaushe. Buffer na shigar da BLVDS yana cinye wuta idan akwai aikin sauya sheka akan bas (misaliample, sauran transceivers suna aikawa da karɓar bayanai, amma na'urar Cyclone III ba ita ce mai karɓa ba).
•  Idan kuna amfani da BLVDS azaman abin shigar da bayanai a cikin multidrop ko azaman buffer bidirectional a cikin aikace-aikacen multipoint, Intel yana ba da shawarar shigar da ƙimar juzu'i wanda ya haɗa da duk ayyuka akan bas, ba kawai ayyukan da aka yi niyya don buffer na'urar Intel BLVDS ba.

ExampShigar da bayanan BLVDS I/O a cikin EPE
Wannan adadi yana nuna shigarwar BLVDS I/O a cikin Cyclone III EPE. Don ƙa'idodin I/O don zaɓar a cikin EPE na wasu na'urorin Intel masu goyan bayan, koma zuwa bayanan da ke da alaƙa.Intel yana ba da shawarar ku yi amfani da kayan aikin Analyzer na Quartus Prime Power Analyzer don aiwatar da ingantaccen bincike na ikon BLVDS I/O bayan kun kammala ƙirar ku. Kayan aikin Analyzer Power yana ƙididdige ƙarfi bisa ƙayyadaddun ƙira bayan an kammala wuri-da-hanyar. Kayan aikin Analyzer Power yana amfani da haɗin shigar mai amfani, wanda aka samo asali, da ƙididdiga ayyukan sigina waɗanda, haɗe tare da cikakkun samfuran da'irar, suna haifar da ingantacciyar ƙididdiga ta wutar lantarki.
Bayanai masu alaƙa

• Babin Analysis Power, Intel Quartus Prime Pro Edition Handbook
  Yana ba da ƙarin bayani game da kayan aikin Analyzer na Intel Quartus Prime Pro Edition don Intel Stratix 10, Intel Arria 10, da dangin na'urar Intel Cyclone 10 GX.
• Babin Analysis Power, Intel Quartus Prime Standard Handbook
  Yana ba da ƙarin bayani game da Intel Quartus Prime Standard Edition Power Analyzer kayan aiki don Stratix V, Stratix IV, Stratix III, Arria V, Arria II, Intel Cyclone 10 LP, Cyclone V, Cyclone IV, Cyclone III LS, Cyclone III, da Intel Iyalan na'ura MAX 10.
• Ƙimar Ƙarfin Farko (EPE) da Shafin Analyzer Power
  Yana ba da ƙarin bayani game da EPE da Intel Quartus Prime Power Analyzer kayan aiki.
• Aiwatar da Motar LVDS ta Bus a cikin Iyalan Na'urar Intel FPGA masu Goyan bayan shafi na 3
  Ya lissafa ma'auni na I/O don zaɓar a cikin EPE don ƙididdige yawan wutar lantarki na BLVDS.

BLVDS Design Example
Zane example yana nuna muku yadda ake aiwatar da buffer na BLVDS I/O a cikin na'urori masu goyan baya tare da maƙasudin maƙasudin I/O (GPIO) da suka dace a cikin software na Intel Quartus Prime.

•  Intel Stratix 10, Intel Arria 10, da Intel Cyclone 10 GX na'urorin - suna amfani da GPIO Intel FPGA IP core.
•  Intel MAX 10 na'urorin - suna amfani da GPIO Lite Intel FPGA IP core.
•  Duk sauran na'urori masu goyan baya-amfani da ALTIBUF IP core.

Zaku iya saukar da zane example daga mahada a cikin bayanan da suka danganci. Don misalin buffer I/O BLVDS, Intel yana ba da shawarar abubuwa masu zuwa:

•  Aiwatar da GPIO IP core a cikin yanayin biyu tare da yanayin banbanta da aka kunna.
•  Sanya ma'auni na I/O zuwa fil masu bi-directional:
•  BLVDS-Intel Cyclone 10 LP, Cyclone IV, Cyclone III, da Intel MAX 10 na'urorin.
•  Daban-daban SSTL-2 Class I ko Class II-Stratix V, Stratix IV, Stratix III, Arria V, Arria II, da Cyclone V na'urorin.
• Daban-daban SSTL-18 Class I ko Class II-Intel Stratix 10, Intel Arria 10, da na'urorin Intel Cyclone 10 GX.

Ayyukan Buffers na shigarwa ko fitarwa yayin Rubutu da karanta Ayyuka

• Tashar tashar jiragen ruwa na karɓar siginar oe daga ainihin na'urar don kunna ko kashe maɓallan fitarwa mai ƙarewa ɗaya.
•  Rike siginar e yayi ƙasa da ƙasa don daidaita abubuwan buffer yayin karantawa.
•  Ayyukan ƙofar AND shine dakatar da siginar da aka watsa daga komawa cikin ainihin na'urar. Ana kunna buffer ɗin shigar da banbanta koyaushe.

Bayanai masu alaƙa

•  I/O Buffer (ALTIOBUF) IP Core User Guide
•  GPIO IP Core Jagora Jagora
•  Jagorar Aiwatar da Intel MAX 10 I/O
• Gabatarwa zuwa Intel FPGA IP Cores
• Zane ExampFarashin AN522

Yana ba da ƙirar Intel Quartus Prime ExampKadan amfani a cikin wannan bayanin kula.
Zane ExampJagorar na'urorin Intel Stratix 10
Waɗannan matakan sun shafi na'urorin Intel Stratix 10 kawai. Tabbatar cewa kayi amfani da GPIO Intel FPGA IP core.

1. Ƙirƙirar GPIO Intel FPGA IP core wanda zai iya goyan bayan shigarwar bidirection da buffer fitarwa:
   • a. Ƙaddamar da GPIO Intel FPGA IP core.
   • b. A cikin Hanyar Bayanai, zaɓi Bidir.
   • c. A cikin fadin bayanai, shigar da 1.
   • d. Kunna Yi amfani da buffer na daban.
   • e. A yanayin yin rijista, zaɓi babu.
2. Haɗa kayan aikin da shigarwar da tashoshin fitarwa kamar yadda aka nuna a cikin adadi mai zuwa:
   Input and Output Connection Ports Exampna'urorin Intel Stratix 10
3. A cikin Editan Ayyuka, sanya ma'aunin I/O mai dacewa kamar yadda aka nuna a adadi mai zuwa. Hakanan zaka iya saita ƙarfin halin yanzu da zaɓuɓɓukan ƙimar kashewa. In ba haka ba, Intel Quartus Prime software yana ɗaukar saitunan tsoho.
   Aikin BLVDS I/O a cikin Intel Quartus Prime Assignment Editan don Intel Stratix 10 Na'urorin
4. Haɗa da yin simintin aiki tare da ModelSim* - Intel FPGA Edition software.

Bayanai masu alaƙa

• ModelSim – Intel FPGA Edition Software Support
  Yana ba da ƙarin bayani game da ModelSim – Intel FPGA Edition software kuma ya ƙunshi hanyoyi daban-daban zuwa batutuwa kamar shigarwa, amfani, da gyara matsala.
• Ka'idodin I/O don Interface BLVDS a cikin na'urorin Intel FPGA akan shafi na 7
  Ya lissafa ma'auni na fil da I/O za ku iya sanyawa da hannu a cikin na'urorin FPGA masu goyan bayan Intel don aikace-aikacen BLVDS.
• Zane ExampFarashin AN522
  Yana ba da ƙirar Intel Quartus Prime ExampKadan amfani a cikin wannan bayanin kula.

Zane ExampJagorar Intel Arria 10 na'urorin
Waɗannan matakan sun dace da na'urorin Intel Arria 10 masu amfani da Intel Quartus Prime Standard Edition kawai. Tabbatar cewa kayi amfani da GPIO Intel FPGA IP core.

1. Bude StratixV_blvds.qar file don shigo da ƙirar Stratix V exampshiga cikin Intel Quartus Prime Standard Edition software.
2. Ƙaura da ƙira exampdon amfani da GPIO Intel FPGA IP core:
   • a. A cikin menu, zaɓi Project ➤ Haɓaka Abubuwan IP.
   • b. Danna maɓallin "ALIOBUF" sau biyu.
     Tagar MegaWizard Plug-In Manager don ainihin ALTIOBUF IP yana bayyana.
   • c. Kashe Match project/default.
   • d. A cikin dangin na'ura da aka zaɓa a halin yanzu, zaɓi Arria 10.
   • e. Danna Gama sannan kuma danna Gama sake.
   • f. A cikin akwatin maganganu da ya bayyana, danna Ok.
     Software na Intel Quartus Prime Pro Edition yana aiwatar da tsarin ƙaura sannan yana nuna editan sigar IP na GPIO.
3. Sanya GPIO Intel FPGA IP core don tallafawa shigarwar bidi'a da buffer na fitarwa:
   • a. A cikin Hanyar Bayanai, zaɓi Bidir.
   • b. A cikin fadin bayanai, shigar da 1.
   • c. Kunna Yi amfani da buffer na daban.
   • d. Danna Gama kuma samar da ainihin IP.
4. Haɗa kayan aikin da shigarwar da tashoshin fitarwa kamar yadda aka nuna a cikin adadi mai zuwa:
   Input and Output Connection Ports Exampna'urorin Intel Arria 10
5. A cikin Editan Ayyuka, sanya ma'aunin I/O mai dacewa kamar yadda aka nuna a adadi mai zuwa. Hakanan zaka iya saita ƙarfin halin yanzu da zaɓuɓɓukan ƙimar kashewa. In ba haka ba, Intel Quartus Prime Standard Edition software yana ɗaukan saitunan tsoho don na'urorin Intel Arria 10-Differential SSTL-18 Class I ko Class II I/O.
   Aikin BLVDS I/O a cikin Intel Quartus Prime Assignment Editan na Intel Arria 10 na'urorinLura:
   Don na'urorin Intel Arria 10, zaku iya sanya wuraren p da n pin na LVDS da hannu tare da Editan Assignment.
6. Haɗa da yin simintin aiki tare da ModelSim – Intel FPGA Edition software.

Bayanai masu alaƙa

• ModelSim – Intel FPGA Edition Software Support
  Yana ba da ƙarin bayani game da ModelSim – Intel FPGA Edition software kuma ya ƙunshi hanyoyi daban-daban zuwa batutuwa kamar shigarwa, amfani, da gyara matsala.
• Ka'idodin I/O don Interface BLVDS a cikin na'urorin Intel FPGA akan shafi na 7
  Ya lissafa ma'auni na fil da I/O za ku iya sanyawa da hannu a cikin na'urorin FPGA masu goyan bayan Intel don aikace-aikacen BLVDS.
• Zane ExampFarashin AN522
  Yana ba da ƙirar Intel Quartus Prime ExampKadan amfani a cikin wannan bayanin kula.

Zane ExampJagorar na'urorin Intel MAX 10
Waɗannan matakan sun shafi na'urorin Intel MAX 10 kawai. Tabbatar cewa kayi amfani da GPIO Lite Intel FPGA IP core.

1. Ƙirƙirar GPIO Lite Intel FPGA IP core wanda zai iya tallafawa shigarwar bidi'a da buffer na fitarwa:
   • a. Ƙaddamar da GPIO Lite Intel FPGA IP core.
   • b. A cikin Hanyar Bayanai, zaɓi Bidir.
   • c. A cikin fadin bayanai, shigar da 1.
   • d. Kunna Amfani da ɓatanci daban-daban.
   • e. A Yanayin Rijista, zaɓi Ketare.
2. Haɗa kayan aikin da shigarwar da tashoshin fitarwa kamar yadda aka nuna a cikin adadi mai zuwa:
    Input and Output Connection Ports Exampdon na'urorin Intel MAX 10
3. A cikin Editan Ayyuka, sanya ma'aunin I/O mai dacewa kamar yadda aka nuna a adadi mai zuwa. Hakanan zaka iya saita ƙarfin halin yanzu da zaɓuɓɓukan ƙimar kashewa. In ba haka ba, Intel Quartus Prime software yana ɗaukar saitunan tsoho.
   Aikin BLVDS I/O a cikin Intel Quartus Prime Assignment Editan na Intel MAX 10 na'urorin
4. Haɗa da yin simintin aiki tare da ModelSim – Intel FPGA Edition software.

Bayanai masu alaƙa

• ModelSim – Intel FPGA Edition Software Support
  Yana ba da ƙarin bayani game da ModelSim – Intel FPGA Edition software kuma ya ƙunshi hanyoyi daban-daban zuwa batutuwa kamar shigarwa, amfani, da gyara matsala.
• Ka'idodin I/O don Interface BLVDS a cikin na'urorin Intel FPGA akan shafi na 7
  Ya lissafa ma'auni na fil da I/O za ku iya sanyawa da hannu a cikin na'urorin FPGA masu goyan bayan Intel don aikace-aikacen BLVDS.
• Zane ExampFarashin AN522
  Yana ba da ƙirar Intel Quartus Prime ExampKadan amfani a cikin wannan bayanin kula.

Zane ExampJagorar Duk Na'urori masu Tallafi Ban da Intel Arria 10, Intel Cyclone 10 GX, da Intel MAX 10

Waɗannan matakan suna da amfani ga duk na'urori masu tallafi ban da Intel Arria 10, Intel Cyclone 10 GX, da Intel MAX 10. Tabbatar cewa kuna amfani da ALTIOBUF IP core.

1.  Ƙirƙiri ainihin tushen IP ALTIOBUF wanda zai iya tallafawa shigarwar bidirectional da buffer fitarwa:
   • a. Ƙaddamar da ALTIOBUF IP core.
   • b. Saita tsarin a matsayin madaidaicin buffer biyu.
   • c. A cikin Menene adadin buffers da za'a kunna, shigar da 1.
   • d. Kunna Yi amfani da yanayin banbanta.
2. Haɗa kayan aikin da shigarwar da tashoshin fitarwa kamar yadda aka nuna a cikin adadi mai zuwa:
    Input and Output Connection Ports Example don Duk Na'urori masu Tallafi Ban da Intel Arria 10, Intel Cyclone 10 GX, da na'urorin Intel MAX 10
3. A cikin Editan Ayyuka, sanya ma'aunin I/O mai dacewa kamar yadda aka nuna a adadi mai zuwa bisa ga na'urarka. Hakanan zaka iya saita ƙarfin halin yanzu da zaɓuɓɓukan ƙimar kashewa. In ba haka ba, Intel Quartus Prime software yana ɗaukar saitunan tsoho.
   • Intel Cyclone 10 LP, Cyclone IV, Cyclone III, da Cyclone III LS na'urorin-BLVDS I/O ma'auni zuwa p da n fil bidirectional kamar yadda aka nuna a cikin adadi mai zuwa.
   • Stratix V, Stratix IV, Stratix III, Arria V, Arria II, da Cyclone V na'urorin - Daban-daban SSTL-2 Class I ko Class II I/O misali.
     Aikin BLVDS I/O a cikin Intel Quartus Prime Assignment EditanLura: Kuna iya sanya duka wuraren p da n fil ga kowace na'ura mai goyan baya tare da Editan Ayyuka. Don na'urori masu goyan baya da fil ɗin da zaku iya sanyawa da hannu, koma zuwa bayanan da ke da alaƙa.
4. Haɗa da yin simintin aiki tare da ModelSim – Intel FPGA Edition software.

ExampSakamakon Sakamakon Kwaikwayo Na Aiki
Lokacin da aka tabbatar da siginar e, BLVDS yana cikin yanayin aiki na rubutu. Lokacin da siginar oe ya ɗanɗana, BLVDS yana cikin yanayin aikin karantawa.Lura:
Don kwaikwaiyo ta amfani da Verilog HDL, zaku iya amfani da blvds_tb.v testbench, wanda aka haɗa a cikin tsoffin ƙira.ample.
Bayanai masu alaƙa

• ModelSim – Intel FPGA Edition Software Support
  Yana ba da ƙarin bayani game da ModelSim – Intel FPGA Edition software kuma ya ƙunshi hanyoyi daban-daban zuwa batutuwa kamar shigarwa, amfani, da gyara matsala.
• Ka'idodin I/O don Interface BLVDS a cikin na'urorin Intel FPGA akan shafi na 7
  Ya lissafa ma'auni na fil da I/O za ku iya sanyawa da hannu a cikin na'urorin FPGA masu goyan bayan Intel don aikace-aikacen BLVDS.
• Zane ExampFarashin AN522
  Yana ba da ƙirar Intel Quartus Prime ExampKadan amfani a cikin wannan bayanin kula.

Binciken Ayyuka

Binciken aikin multipoint BLVDS yana nuna tasirin ƙarewar bas, kaya, direba da halayen mai karɓa, da kuma wurin da mai karɓa daga direba a kan tsarin. Kuna iya amfani da ƙirar BLVDS da aka haɗa exampdon bincika aikin aikace-aikacen multipoint:

•  Cyclone III BLVDS zane example-wannan zane example ya dace da duk masu goyan bayan Stratix, Arria, da jerin na'urorin Cyclone. Don Intel Arria 10 ko Intel Cyclone 10 GX dangin na'urar, kuna buƙatar ƙaura tsohon ƙirar ƙira.ampfara zuwa ga dangin na'urar kafin ku iya amfani da shi.
• Intel MAX 10 BLVDS zane example-wannan zane example ya dace da dangin na'urar Intel MAX 10.
• Intel Stratix 10 BLVDS zane example-wannan zane exampLe ya dace da dangin na'urar Intel Stratix 10.

Lura:
Binciken wasan kwaikwayon na BLVDS mai yawa a cikin wannan sashe ya dogara ne akan ƙirar Cyclone III BLVDS shigarwar / bayanin bayanan buffer (IBIS) samfurin simulation a HyperLynx *.
Intel yana ba da shawarar ku yi amfani da waɗannan samfuran Intel IBIS don kwaikwayo:

• Stratix III, Stratix IV, da Stratix V na'urorin - takamaiman na'urar SSTL-2 IBIS na musamman
• Intel Stratix 10, Intel Arria 10(2) da Intel Cyclone 10 GX na'urorin:
  •  Buffer na fitarwa-Bambancin SSTL-18 IBIS samfurin
  • Buffer na shigarwa-samfurin LVDS IBIS

Bayanai masu alaƙa

• Intel FPGA IBIS Model shafi
  Yana ba da zazzagewar ƙirar na'urar Intel FPGA.
•  Zane ExampFarashin AN522
  Yana ba da ƙirar Intel Quartus Prime ExampKadan amfani a cikin wannan bayanin kula.

Saita Tsarin

 Multipoint BLVDS tare da Cyclone III BLVDS Transceivers
Wannan adadi yana nuna tsarin tsarin topology mai yawa tare da masu karɓar Cyclone III BLVDS goma (mai suna U1 zuwa U10).Ana tsammanin layin watsa bas yana da halaye masu zuwa:

•  Layin tsiri
•  Halayen tauyewa na 50 Ω
• Halayen ƙarfin 3.6 pF kowace inch
•  Tsawon inci 10
• Samfuran Intel Arria 10 IBIS na farko ne kuma ba a samun su akan ƙirar Intel IBIS web shafi. Idan kuna buƙatar waɗannan samfuran farko na Intel Arria 10 IBIS, tuntuɓi Intel.
• Matsalolin bambancin bas na kusan 100 Ω
•  Tazara tsakanin kowane transceiver na inch 1
• Motar bas ta ƙare a ƙarshen biyu tare da ƙarewar resistor RT

• Tsohuwar ƙarfin tuƙi na 12mA
• Slew rates saituna ta tsohuwa
• Capacitance fil na kowane transceiver na 6 pF
•  Stub akan kowane mai ɗaukar BLVDS shine inch microstrip 1-inch na ƙayyadaddun halayen halayen 50 Ω da ƙimar halayyar 3 pF a kowace inch.
•  Ƙarfin haɗin haɗin (mai haɗawa, pad, da ta cikin PCB) na kowane mai ɗaukar hoto zuwa bas ana tsammanin ya zama 2 pF
• Jimlar ƙarfin kowane kaya yana da kusan 11 pF

Don tazarar nauyin inch 1, ƙarfin da aka rarraba yana daidai da 11 pF kowace inch. Don rage tunani da stubs ke haifarwa, da kuma rage alamun da ke fitowa daga ciki
direban, an sanya impedance madaidaicin 50 Ω resistor RS a wurin fitarwa na kowane transceiver.

Karshen Bus
Ingantacciyar maƙarƙashiyar bas ɗin da aka ɗora ta ita ce 52 Ω idan kun musanya ƙarfin halayen motar bas da ƙarfin da aka rarraba kowane tsayin raka'a na saitin zuwa ingantaccen daidaiton impedance. Don ingantaccen ingancin siginar, dole ne ku dace da RT zuwa 52 Ω. Alkaluman da ke biyowa suna nuna tasirin matches-, under-, da over-termination akan nau'in igiyar ruwa daban-daban (VID) a fil ɗin shigar da mai karɓa. Adadin bayanai shine 100 Mbps. A cikin waɗannan alkaluman, ƙarancin ƙarewa (RT = 25 Ω) yana haifar da tunani da raguwar haɓakar amo. A wasu lokuta, a ƙarƙashin ƙarewa har ma ya keta iyakar mai karɓa (VTH = ± 100 mV). Lokacin da aka canza RT zuwa 50 Ω, akwai babban gefen ƙarar amo game da VTH kuma tunanin ba shi da komai.

Tasirin Ƙarshen Bus (Direba a U1, Mai karɓa a U2)
A cikin wannan adadi, U1 yana aiki azaman mai watsawa kuma U2 zuwa U10 sune masu karɓa.

Tasirin Ƙarshen Bus (Direba a U1, Mai karɓa a U10)
A cikin wannan adadi, U1 yana aiki azaman mai watsawa kuma U2 zuwa U10 sune masu karɓa.

Tasirin Ƙarshen Bus (Direba a U5, Mai karɓa a U6)
A cikin wannan adadi, U5 shine mai watsawa kuma sauran masu karɓa ne.

Tasirin Ƙarshen Bus (Direba a U5, Mai karɓa a U10)
A cikin wannan adadi, U5 shine mai watsawa kuma sauran masu karɓa ne.Matsayin dangi na direba da mai karɓa akan bas ɗin shima yana shafar ingancin siginar da aka karɓa. Mai karɓar mafi kusa da direba yana fuskantar mummunan tasirin layin watsawa saboda a wannan wurin, ƙimar gefen shine mafi sauri. Wannan ya fi muni idan direban yana tsakiyar motar bas.
Don misaliample, kwatanta hoto na 16 a shafi na 20 da Hoto 18 a shafi na 21. VID a mai karɓar U6 (direba a U5) yana nuna ƙarar ƙara fiye da na mai karɓar U2 (direba a U1). A gefe guda, ƙimar gefen yana raguwa lokacin da mai karɓa ya kasance nesa da direba. Mafi girman lokacin tashin da aka yi rikodin shine 1.14 ns tare da direban da ke gefen ɗaya ƙarshen bas (U1) da mai karɓa a ɗayan ƙarshen (U10).

Tsawon Kankara
Tsawon tsayi mai tsayi ba kawai yana ƙara lokacin tashi daga direba zuwa mai karɓa ba, amma har ma yana haifar da babban nauyin kaya, wanda ke haifar da tunani mai girma.

Tasirin Haɓaka Tsawon Stub (Direba a U1, Mai karɓa a U10)
Wannan adadi yana kwatanta VID a U10 lokacin da aka karu tsayin stub daga inci ɗaya zuwa inci biyu kuma direban yana U1.

Karshen Stub
Dole ne ku dace da matsananciyar direba da siffa ta stub. Ajiye jerin ƙarewar resistor RS a fitowar direba yana rage mummunan tasirin layin watsawa wanda ke haifar da dogon stub da ƙimar gefen sauri. Bugu da ƙari, ana iya canza RS don rage VID don saduwa da ƙayyadaddun mai karɓa.

Tasirin Ƙarshen Stub (Direba a U1, Mai karɓa a U2 da U10)
Wannan adadi yana kwatanta VID a U2 da U10 lokacin da U1 ke watsawa.

Direba Slew Rate
Matsakaicin kisa mai sauri yana taimakawa haɓaka lokacin tashi, musamman a mai karɓar mafi nisa daga direba. Koyaya, saurin kashewa shima yana haɓaka ringi saboda tunani.

Tasirin Rate ɗin Direba (Direba a U1, Mai karɓa a U2 da U10)
Wannan adadi yana nuna tasirin kashe direban. Ana yin kwatance tsakanin saurin kisa da sauri tare da ƙarfin tuƙi 12mA. Direba yana U1 kuma ana duba nau'ikan raƙuman ruwa na U2 da U10.

Ayyukan Tsarin Gabaɗaya

Mafi girman ƙimar bayanai da ke da goyan bayan multipoint BLVDS ana ƙaddara ta hanyar kallon zanen ido na mai karɓa mafi nisa daga direba. A wannan wurin, siginar da aka watsa yana da mafi girman ƙimar gefen kuma yana rinjayar buɗe ido. Kodayake ingancin siginar da aka karɓa da makasudin gefen amo ya dogara da aikace-aikacen, mafi girman buɗe ido, mafi kyau. Koyaya, dole ne ku duba mai karɓar mafi kusa da direba, saboda tasirin layin watsawa yakan yi muni idan mai karɓar yana kusa da direba.
Hoto 23. Tsarin ido a 400 Mbps (Direba a U1, Mai karɓa a U2 da U10)
Wannan adadi yana kwatanta zane-zanen ido a U2 (Raunin jan hankali) da U10 (launi shuɗi) don ƙimar bayanai a 400 Mbps. Bazuwar jitter na tazara na 1% ana ɗauka a cikin simintin. Direba yana U1 tare da tsohowar ƙarfin halin yanzu da saitunan ƙimar kashewa. An cika motar bas ɗin tare da mafi kyawun RT = 50 Ω. Mafi ƙarancin buɗe ido yana U10, wanda shine mafi nisa daga U1. Tsawon ido sampjagoranci a tazarar naúrar 0.5 shine 692 mV da 543 mV don U2 da U10, bi da bi. Akwai babban gefen amo dangane da VTH = ± 100 mV na duka lokuta biyu.

Tarihin Bita na Takardu don AN 522: Aiwatar da Motar LVDS ta Bus a cikin Iyalan Na'urar Intel FPGA

Takardu / Albarkatu

intel AN 522 Yana Aiwatar da Motar LVDS Bus a cikin Iyalan Na'urar FPGA [pdf] Jagorar mai amfani AN 522 Mai Aiwatar da Interface LVDS Bus a cikin Iyalan Na'urar FPGA masu Goyan baya, AN 522, Aiwatar da Interface LVDS Bus a cikin Iyalan Na'urar FPGA masu Goyan bayan, Matsala a cikin Iyalan Na'urar FPGA masu Goyan baya, Iyalan Na'urar FPGA

Magana

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