intel AN 522 Kev Siv Tsheb Npav LVDS Interface hauv Kev Txhawb FPGA Cov Tsev Neeg

Tsheb npav LVDS (BLVDS) txuas ntxiv lub peev xwm ntawm LVDS point-to-point kev sib txuas lus mus rau multipoint configuration. Multipoint BLVDS muab cov kev daws teeb meem zoo rau cov ntawv thov multipoint backplane.

BLVDS Kev Txhawb Nqa Kev Ua Haujlwm hauv Intel FPGA Devices

Koj tuaj yeem siv BLVDS interfaces hauv cov khoom siv Intel no siv cov qauv I/O teev.

Nco tseg:
Lub programmable tsav lub zog thiab slew tus nqi nta hauv cov khoom siv no tso cai rau koj los kho koj qhov system multipoint kom ua tau zoo tshaj plaws. Txhawm rau txiav txim siab qhov siab tshaj plaws cov ntaub ntawv txhawb nqa, ua qhov simulation lossis ntsuas raws li koj qhov kev teeb tsa tshwj xeeb thiab daim ntawv thov.
BLVDS dhauview hauv paj 4
BLVDS Technology hauv Intel Devices ntawm nplooj 6
BLVDS Power Consumption ntawm nplooj 9
BLVDS Design Exampli ntawm nplooj 10
Kev Ntsuam Xyuas Kev Ua Haujlwm ntawm nplooj 17
Cov Ntaub Ntawv Hloov Kho Keeb Kwm rau AN 522: Kev Siv Tsheb Npav LVDS Interface hauv Kev Txhawb Intel FPGA Cov Tsev Neeg ntawm nplooj 25
Cov ntaub ntawv ntsig txog
I/O Standards for BLVDS Interface in Intel FPGA Devices ntawm nplooj 7

BLVDS dhauview

Hom multipoint BLVDS system muaj ntau lub transmitter thiab receiver khub (transceivers) uas txuas nrog lub npav.
Multipoint BLVDSKev teeb tsa hauv daim duab ua ntej muab kev sib txuas lus bidirectional ib nrab-duplex thaum txo qis kev sib txuas ceev. Txhua lub transceiver tuaj yeem ua lub luag haujlwm ntawm lub transmitter, nrog rau cov transceivers ntxiv ua tus txais (tsuas yog ib lub transmitter tuaj yeem ua haujlwm ntawm ib lub sijhawm). Kev tswj cov tsheb npav, xws li los ntawm cov txheej txheem lossis kev daws teeb meem kho vajtse feem ntau yuav tsum tau ua kom tsis txhob muaj kev sib cav ntawm tus neeg tsav tsheb. Kev ua tau zoo ntawm multipoint BLVDS cuam tshuam zoo heev los ntawm kev thauj khoom thiab kev txiav tawm ntawm lub npav.
Kev txiav txim siab tsim
Ib tug zoo multipoint tsim yuav tsum xav txog lub capacitive load thiab txiav ntawm lub tsheb npav kom tau zoo dua teeb liab kev ncaj ncees. Koj tuaj yeem txo qhov load capacitance los ntawm kev xaiv lub transceiver nrog tsawg tus pin capacitance, connector nrog tsawg capacitance, thiab ua kom lub stub ntev luv. Ib qho ntawm ntau qhov kev txiav txim siab tsim qauv BLVDS yog qhov zoo sib txawv impedance ntawm lub tsheb thauj khoom tag nrho, hu ua impedance zoo, thiab kev nthuav tawm qeeb los ntawm lub npav. Lwm qhov kev txiav txim siab tsim ntau yam ntawm BLVDS suav nrog kev tsis sib haum xeeb tsis zoo, hom kev sib txuas thiab tus pin-tawm, PCB tsheb npav taug qab layout, thiab tus tsav tsheb ntug tus nqi specifications.
Muaj txiaj ntsig Impedance
Qhov zoo impedance nyob ntawm lub tsheb npav tus yam ntxwv impedance Zo thiab capacitive loading ntawm lub npav. Cov connectors, lub stub ntawm daim card plug-in, ntim, thiab cov receiver input capacitance tag nrho ua rau lub capacitive loading, uas txo cov tsheb npav zoo impedance.
Equation 1. Muaj txiaj ntsig sib txawv Impedance Equation
Siv qhov sib npaug no los kwv yees qhov sib txawv impedance zoo ntawm lub npav thauj khoom (Zeff).Qhov twg:

• Zdiff (Ω) ≈ 2 × Zo = tus yam ntxwv txawv impedance ntawm lub npav
•  Co (pF/inch) = tus yam ntxwv capacitance ib chav tsev ntev ntawm lub npav
• CL (pF) = capacitance ntawm txhua qhov load
•  N = tus naj npawb ntawm cov loads ntawm lub npav
•  H (inch) = d × N = tag nrho qhov ntev ntawm lub npav
•  d (inch) = qhov sib nrug ntawm txhua daim npav plug-in
•  Cd (pF/inch) = CL/d = faib capacitance rau ib chav tsev ntev hla lub npav

Qhov nce hauv load capacitance lossis ze dua qhov sib nrug ntawm daim npav plug-in txo cov impedance zoo. Txhawm rau txhim kho qhov kev ua tau zoo ntawm lub cev, nws yog ib qho tseem ceeb uas yuav tsum xaiv qhov tsis tshua muaj peev xwm transceiver thiab connector. Khaws txhua tus txais qhov ntev ntawm lub connector thiab transceiver I / O tus pin kom luv li sai tau.
Normalized Effective Impedance Versus Cd/Co
Daim duab no qhia txog qhov cuam tshuam ntawm kev faib cov peev txheej ntawm kev ua haujlwm zoo impedance.Kev txiav tawm yog xav tau ntawm txhua qhov kawg ntawm lub npav, thaum cov ntaub ntawv ntws hauv ob qho tib si. Txhawm rau txo qhov kev xav thiab lub suab nrov ntawm lub tsheb npav, koj yuav tsum ua kom haum rau qhov kev txiav tawm ntawm qhov cuam tshuam rau qhov zoo impedance. Rau lub kaw lus nrog Cd / Co = 3, qhov zoo impedance yog 0.5 npaug ntawm Zdiff. Nrog ob qhov kev txiav tawm ntawm lub npav, tus neeg tsav tsheb pom qhov sib npaug ntawm 0.25 npaug ntawm Zdiff; thiab yog li txo cov teeb liab viav vias thiab qhov sib txawv ntawm lub suab nrov thoob plaws lub receiver inputs (yog siv tus qauv LVDS). Tus neeg tsav tsheb BLVDS daws qhov teeb meem no los ntawm kev nce tus tsav tam sim no kom ua tiav qhov zoo sib xwstage viav vias ntawm lub receiver inputs.
Kev nthuav tawm qeeb
Kev nthuav tawm ncua sij hawm (tPD = Zo × Co) yog lub sij hawm ncua los ntawm kev sib kis kab hauv ib chav tsev ntev. Nws nyob ntawm tus yam ntxwv impedance thiab tus yam ntxwv
capacitance ntawm lub tsheb npav.
Kev ncua sij hawm siv tau zoo
Rau lub tsheb npav thauj khoom, koj tuaj yeem suav qhov kev nthuav tawm tau zoo nrog qhov sib npaug no. Koj tuaj yeem suav lub sijhawm rau lub teeb liab tawm ntawm tus tsav tsheb A mus rau tus txais B raws li tPDEFF × ntev ntawm kab ntawm tus tsav tsheb A thiab tus txais B.

BLVDS Technology hauv Intel Devices

Hauv kev txhawb nqa Intel cov khoom siv, BLVDS interface tau txais kev txhawb nqa hauv txhua kab lossis kab I / cov tsev txhab nyiaj uas tau siv los ntawm VCCIO ntawm 1.8 V (Intel Arria 10 thiab Intel Cyclone 10 GX li) lossis 2.5 V (lwm cov khoom txhawb nqa). Hauv cov tsev txhab nyiaj I / O no, qhov kev sib txuas tau txais kev txhawb nqa ntawm qhov sib txawv I / O pins tab sis tsis yog nyob rau ntawm lub sij hawm nkag siab lossis lub moos tso zis pins. Txawm li cas los xij, hauv Intel Arria 10 thiab Intel Cyclone 10 GX cov khoom siv, BLVDS interface tau txais kev txhawb nqa ntawm lub moos pins uas tau siv los ua I/Os.

•  Lub BLVDS transmitter siv ob qhov kawg tso zis buffers nrog qhov thib ob tso zis tsis programmed li inverted.
•  BLVDS receiver siv lub siab LVDS input buffer.

BLVDS I/O Buffers hauv cov khoom siv txhawb nqaSiv cov tswv yim sib txawv lossis cov khoom tso tawm nyob ntawm seb hom ntawv thov:

• Multidrop daim ntawv thov-siv lub input lossis output buffer nyob ntawm seb lub cuab yeej yog npaj rau kev tsav tsheb lossis kev ua haujlwm txais.
• Multipoint daim ntawv thov - cov zis tsis thiab cov tswv yim tsis sib koom ua ke tib tus I / O tus pins. Koj xav tau qhov tso zis tso zis (oe) teeb liab rau tri-xeev LVDS cov zis tsis tawm thaum nws tsis xa cov teeb liab.
•  Tsis txhob tso cai rau ntawm-chip series termination (RS OCT) rau cov zis tsis tawm.
• Siv cov resistors sab nraud ntawm cov zis buffers los muab impedance txuam rau cov stub ntawm daim npav plug-in.
• Tsis txhob tso cai rau qhov kev txiav tawm ntawm qhov sib txawv ntawm qhov sib txawv (RD OCT) rau qhov sib txawv ntawm qhov sib txawv ntawm qhov tsis sib txawv vim hais tias qhov kev txiav tawm ntawm lub npav feem ntau yog siv los ntawm kev txiav tawm sab nraud ntawm ob qho kawg ntawm lub npav.

I/O Cov Qauv rau BLVDS Interface hauv Intel FPGA Devices
Koj tuaj yeem siv BLVDS interface siv cov qauv I / O cuam tshuam thiab tam sim no lub zog xav tau rau cov khoom siv Intel txhawb.
I/O Standard thiab Nta Txhawb rau BLVDS Interface hauv Kev Txhawb Intel Devices

1.  DIFFIO_TX tus pin tsis txhawb qhov tseeb LVDS qhov sib txawv txais.

Yog xav paub ntxiv, xa mus rau cov ntaub ntawv hais txog cov cuab yeej raws li teev nyob rau hauv cov ntaub ntawv ntsig txog ntu:

• Yog xav paub ntxiv txog kev ua haujlwm tus pin, xa mus rau lub cuab yeej pin-out files.
• Rau cov qauv I/O cov qauv, xa mus rau phau ntawv txhais tes I/O tshooj.
•  Rau cov khoom siv hluav taws xob tshwj xeeb, xa mus rau cov ntaub ntawv ntaus ntawv lossis DC thiab cov ntaub ntawv hloov cov yam ntxwv.

Cov ntaub ntawv ntsig txog

•  Intel Stratix 10 Pin-Out Files
•  Stratix V Pin-Out Files
• Stratix IV Pin-Out Files
•  Stratix III Device Pin-Out Files
•  Intel Arria 10 Ntaus Pin-Out Files
•  Arria V Device Pin-out Files
•  Arria II GX Device Pin-Out Files
• Intel Cyclone 10 GX Device Pin-Out Files
• Intel Cyclone 10 LP Ntaus Pin-Out Files
• Cyclone V Device Pin-Out Files
•  Cyclone IV Device Pin-Out Files
• Cyclone III Device Pin-Out Files
• Intel MAX 10 Device Pin-Out Files
• Intel Stratix 10 General Purpose I/O User Guide
•  I/O nta hauv Stratix V Devices
•  I/O Nta hauv Stratix IV Ntaus
•  Stratix III Ntaus I/O Nta
• I/O nta hauv Stratix V Devices
•  I/O Nta hauv Stratix IV Ntaus
•  Stratix III Ntaus I/O Nta
•  I/O thiab High Speed ​​I/O hauv Intel Arria 10 Devices
•  I/O Nta hauv Arria V Devices
• I/O Nta hauv Arria II Devices
•  I/O thiab High Speed ​​I/O hauv Intel Cyclone 10 GX Devices
•  I/O thiab High Speed ​​I/O hauv Intel Cyclone 10 LP Devices
• I/O Nta hauv Cyclone V Devices
• I/O Nta hauv Cyclone IV Devices
•  I/O Nta hauv Cyclone III Device Family
• Intel MAX 10 General Purpose I/O User Guide
•  Intel Stratix 10 Device Datasheet
• Stratix V Device Datasheet
•  DC thiab Hloov Cov yam ntxwv rau Stratix IV Devices
•  Stratix III Device Datasheet: DC thiab Hloov Cov yam ntxwv
•  Intel Arria 10 Device Datasheet
•  Arria V Device Datasheet
• Device Datasheet rau Arria II Devices
• Intel Cyclone 10 GX Device Datasheet
•  Intel Cyclone 10 LP Device Datasheet
•  Cyclone V Device Datasheet
•  Cyclone IV Device Datasheet
• Cyclone III Device Datasheet
• Intel MAX 10 Device Datasheet

BLVDS Kev siv hluav taws xob

• Ua ntej siv koj tus qauv tsim rau hauv lub cuab yeej, siv Excel-based EPE rau cov cuab yeej txhawb nqa koj siv kom tau txais qhov kwv yees qhov loj ntawm BLVDS I / O lub zog noj.
•  Rau cov tswv yim thiab bidirectional pins, BLVDS input buffer yeej ib txwm qhib. Lub BLVDS input tsis siv hluav taws xob yog tias muaj kev hloov pauv ntawm lub npav (xws liample, lwm cov transceivers yog xa thiab tau txais cov ntaub ntawv, tab sis cov cuab yeej Cyclone III tsis yog tus neeg tau txais kev pab).
•  Yog tias koj siv BLVDS los ua ib qho kev tawm tswv yim tsis nyob hauv ntau qhov los yog ua ib qho kev tsis sib haum xeeb hauv kev siv ntau qhov chaw, Intel pom zoo kom nkag mus rau tus nqi sib tw uas suav nrog txhua yam dej num ntawm lub tsheb npav, tsis yog kev ua ub no rau Intel ntaus ntawv BLVDS input buffer.

Example ntawm BLVDS I/O Data Entry in the EPE
Daim duab no qhia txog BLVDS I/O nkag hauv Cyclone III EPE. Rau cov qauv I/O xaiv hauv EPE ntawm lwm cov khoom siv Intel txhawb, xa mus rau cov ntaub ntawv ntsig txog.Intel xav kom koj siv Intel Quartus Prime Power Analyzer Tool los ua qhov tseeb BLVDS I/O lub zog tsom xam tom qab koj ua tiav koj qhov tsim. Lub Hwj Chim Analyzer Tool kwv yees lub zog raws li qhov tshwj xeeb ntawm tus qauv tsim tom qab qhov chaw-thiab-kev ua tiav. Lub Hwjchim Analyzer Tool siv kev sib xyaw ua ke ntawm cov neeg siv nkag mus, simulation-derived, thiab kwv yees cov haujlwm teeb liab uas, ua ke nrog cov qauv qhia hauv Circuit Court, yields qhov kev kwv yees muaj zog heev.
Cov ntaub ntawv ntsig txog

• Nqe Kev Tshawb Fawb Lub Zog, Intel Quartus Prime Pro Phau Ntawv Qhia
  Muab cov ntaub ntawv ntau ntxiv txog Intel Quartus Prime Pro Edition Power Analyzer cuab yeej rau Intel Stratix 10, Intel Arria 10, thiab Intel Cyclone 10 GX cov tsev neeg.
• Tshooj Kev Ntsuas Hluav Taws Xob, Intel Quartus Prime Standard Edition Phau Ntawv Qhia
  Muab cov ntaub ntawv ntau ntxiv txog Intel Quartus Prime Standard Edition Power Analyzer cuab yeej rau Stratix V, Stratix IV, Stratix III, Arria V, Arria II, Intel Cyclone 10 LP, Cyclone V, Cyclone IV, Cyclone III LS, Cyclone III, thiab Intel MAX 10 Device Family.
• Kev Ntsuas Hluav Taws Xob Thaum Ntxov (EPE) thiab nplooj ntawv ntsuas hluav taws xob
  Muab cov ntaub ntawv ntau ntxiv txog EPE thiab Intel Quartus Prime Power Analyzer cuab yeej.
• Kev Siv Tsheb Npav LVDS Interface hauv Kev Txhawb Intel FPGA Cov Tsev Neeg ntawm nplooj 3
  Sau cov qauv I/O los xaiv hauv EPE los kwv yees BLVDS lub zog siv.

BLVDS Design Example
Design example qhia koj yuav ua li cas kom sai sai BLVDS I / O tsis nyob hauv cov khoom siv txhawb nqa nrog lub hom phiaj dav dav I / O (GPIO) IP cores hauv Intel Quartus Prime software.

•  Intel Stratix 10, Intel Arria 10, thiab Intel Cyclone 10 GX li-siv GPIO Intel FPGA IP core.
•  Intel MAX 10 li-siv GPIO Lite Intel FPGA IP core.
•  Tag nrho lwm cov khoom siv txhawb nqa-siv ALTIBUF IP core.

Koj tuaj yeem rub tawm tus tsim example los ntawm qhov txuas hauv cov ntaub ntawv ntsig txog. Rau BLVDS I / O qhov tsis zoo, Intel pom zoo cov khoom hauv qab no:

•  Siv GPIO IP core nyob rau hauv hom bidirectional nrog rau qhov sib txawv hom qhib.
•  Muab tus qauv I/O rau tus pins bidirectional:
•  BLVDS—Intel Cyclone 10 LP, Cyclone IV, Cyclone III, thiab Intel MAX 10 li.
•  Differential SSTL-2 Class I lossis Class II—Stratix V, Stratix IV, Stratix III, Arria V, Arria II, thiab Cyclone V.
• Differential SSTL-18 Class I lossis Class II—Intel Stratix 10, Intel Arria 10, thiab Intel Cyclone 10 GX li.

Input lossis Output Buffers Ua Haujlwm Thaum Sau thiab Nyeem Ua Haujlwm

• Qhov chaw nres nkoj oe tau txais oe teeb liab los ntawm lub cuab yeej tseem ceeb los pab lossis lov tes taw cov khoom tso tawm ib zaug.
•  Khaws lub teeb liab oe qis rau tri-xeev cov zis buffers thaum nyeem ntawv ua haujlwm.
•  Lub luag haujlwm ntawm AND lub rooj vag yog txwv tsis pub cov teeb liab kis tau rov qab mus rau hauv cov tub ntxhais ntaus ntawv. Qhov sib txawv input tsis yog ib txwm qhib.

Cov ntaub ntawv ntsig txog

•  I/O Buffer (ALTIOBUF) IP Tus Neeg Siv Khoom Qhia
•  GPIO IP Core User Guide
•  Intel MAX 10 I/O Cov Lus Qhia Ua Haujlwm
• Taw qhia rau Intel FPGA IP Cores
• Tsim Examprau AN522

Muab Intel Quartus Prime tsim examples siv hauv daim ntawv thov no.
Tsim Example Cov Lus Qhia rau Intel Stratix 10 Devices
Cov kauj ruam no muaj feem xyuam rau Intel Stratix 10 cov khoom siv nkaus xwb. Xyuas kom tseeb tias koj siv GPIO Intel FPGA IP core.

1. Tsim ib qho GPIO Intel FPGA IP core uas tuaj yeem txhawb nqa ob txoj kev tawm tswv yim thiab tso tawm tsis tawm:
   • ib. Instantiate GPIO Intel FPGA IP core.
   • b. Hauv Data Direction, xaiv Bidir.
   • c. Hauv cov ntaub ntawv dav, sau 1.
   • d. Tig rau Siv qhov tsis sib txawv.
   • e. Hauv Register hom, xaiv tsis muaj.
2. Txuas cov modules thiab cov input thiab output ports raws li qhia hauv daim duab hauv qab no:
   Input thiab Output Ports Connection Example rau Intel Stratix 10 Devices
3. Nyob rau hauv Tus Thawj Saib Xyuas Haujlwm, muab tus qauv I/O cuam tshuam raws li qhia hauv daim duab hauv qab no. Koj tuaj yeem teeb tsa lub zog tam sim no thiab kev xaiv tus nqi slew. Tsis tas li ntawd, Intel Quartus Prime software xav tias qhov chaw pib.
   BLVDS I/O Assignment hauv Intel Quartus Prime Assignment Editor rau Intel Stratix 10 Devices
4. Sau thiab ua haujlwm simulation nrog ModelSim * - Intel FPGA Edition software.

Cov ntaub ntawv ntsig txog

• ModelSim - Intel FPGA Edition Software Support
  Muab cov ntaub ntawv ntau ntxiv txog ModelSim - Intel FPGA Edition software thiab muaj ntau yam txuas rau cov ncauj lus xws li kev teeb tsa, kev siv, thiab kev daws teeb meem.
• I/O Standards for BLVDS Interface in Intel FPGA Devices ntawm nplooj 7
  Sau cov pins thiab I / O cov qauv koj tuaj yeem muab rau hauv cov khoom siv txhawb Intel FPGA rau BLVDS daim ntawv thov.
• Tsim Examprau AN522
  Muab Intel Quartus Prime tsim examples siv hauv daim ntawv thov no.

Tsim Example Cov Lus Qhia rau Intel Arria 10 Devices
Cov kauj ruam no siv tau rau Intel Arria 10 li siv Intel Quartus Prime Standard Edition nkaus xwb. Xyuas kom tseeb tias koj siv GPIO Intel FPGA IP core.

1. Qhib StratixV_blvds.qar file import Stratix V tsim exampmus rau hauv Intel Quartus Prime Standard Edition software.
2. Migrate tus tsim exampsiv GPIO Intel FPGA IP core:
   • a. Ntawm cov ntawv qhia zaub mov, xaiv qhov Project ➤ Txhim kho IP Cheebtsam.
   • b. Ob npaug nyem rau "ALIOBUF" qhov chaw.
     Lub qhov rais MegaWizard Plug-In Manager rau ALTIOBUF IP core tshwm.
   • c. Tua tawm Match project/default.
   • d. Hauv tsev neeg xaiv khoom tam sim no, xaiv Arria 10.
   • e. Nyem Finish thiab ces nias Finish dua.
   • f. Nyob rau hauv lub dialog box uas tshwm, nyem OK.
     Intel Quartus Prime Pro Edition software ua cov txheej txheem tsiv teb tsaws thiab tom qab ntawd qhia txog GPIO IP parameter editor.
3. Configure GPIO Intel FPGA IP core los txhawb kev tawm tswv yim bidirectional thiab tso zis tsis zoo:
   • ib. Hauv Data Direction, xaiv Bidir.
   • b. Hauv cov ntaub ntawv dav, sau 1.
   • c. Tig rau Siv qhov tsis sib txawv.
   • d. Nyem Ua kom tiav thiab tsim cov tub ntxhais IP.
4. Txuas cov modules thiab cov input thiab output ports raws li qhia hauv daim duab hauv qab no:
   Input thiab Output Ports Connection Example rau Intel Arria 10 Devices
5. Nyob rau hauv Tus Thawj Saib Xyuas Haujlwm, muab tus qauv I/O cuam tshuam raws li qhia hauv daim duab hauv qab no. Koj tuaj yeem teeb tsa lub zog tam sim no thiab kev xaiv tus nqi slew. Txwv tsis pub, Intel Quartus Prime Standard Edition software suav tias yog qhov chaw pib rau Intel Arria 10 li-Differential SSTL-18 Class I lossis Class II I / O tus qauv.
   BLVDS I/O Assignment hauv Intel Quartus Prime Assignment Editor rau Intel Arria 10 DevicesNco tseg:
   Rau Intel Arria 10 cov khoom siv, koj tuaj yeem muab ob qho tib si p thiab n tus pin qhov chaw rau LVDS tus pins nrog Tus Thawj Saib Xyuas Haujlwm.
6. Sau thiab ua haujlwm simulation nrog ModelSim - Intel FPGA Edition software.

Cov ntaub ntawv ntsig txog

• ModelSim - Intel FPGA Edition Software Support
  Muab cov ntaub ntawv ntau ntxiv txog ModelSim - Intel FPGA Edition software thiab muaj ntau yam txuas rau cov ncauj lus xws li kev teeb tsa, kev siv, thiab kev daws teeb meem.
• I/O Standards for BLVDS Interface in Intel FPGA Devices ntawm nplooj 7
  Sau cov pins thiab I / O cov qauv koj tuaj yeem muab rau hauv cov khoom siv txhawb Intel FPGA rau BLVDS daim ntawv thov.
• Tsim Examprau AN522
  Muab Intel Quartus Prime tsim examples siv hauv daim ntawv thov no.

Tsim Example Cov Lus Qhia rau Intel MAX 10 Devices
Cov kauj ruam no siv tau rau Intel MAX 10 cov khoom siv nkaus xwb. Xyuas kom tseeb tias koj siv GPIO Lite Intel FPGA IP core.

1. Tsim ib qho GPIO Lite Intel FPGA IP core uas tuaj yeem txhawb nqa ob txoj kev tawm tswv yim thiab tso tawm tsis tawm:
   • ib. Instantiate GPIO Lite Intel FPGA IP core.
   • b. Hauv Data Direction, xaiv Bidir.
   • c. Hauv cov ntaub ntawv dav, sau 1.
   • d. Tig rau Siv pseudo differential tsis.
   • e. Hauv Register hom, xaiv Bypass.
2. Txuas cov modules thiab cov input thiab output ports raws li qhia hauv daim duab hauv qab no:
    Input thiab Output Ports Connection Example rau Intel MAX 10 Devices
3. Nyob rau hauv Tus Thawj Saib Xyuas Haujlwm, muab tus qauv I/O cuam tshuam raws li qhia hauv daim duab hauv qab no. Koj tuaj yeem teeb tsa lub zog tam sim no thiab kev xaiv tus nqi slew. Tsis tas li ntawd, Intel Quartus Prime software xav tias qhov chaw pib.
   BLVDS I/O Assignment hauv Intel Quartus Prime Assignment Editor rau Intel MAX 10 Devices
4. Sau thiab ua haujlwm simulation nrog ModelSim - Intel FPGA Edition software.

Cov ntaub ntawv ntsig txog

• ModelSim - Intel FPGA Edition Software Support
  Muab cov ntaub ntawv ntau ntxiv txog ModelSim - Intel FPGA Edition software thiab muaj ntau yam txuas rau cov ncauj lus xws li kev teeb tsa, kev siv, thiab kev daws teeb meem.
• I/O Standards for BLVDS Interface in Intel FPGA Devices ntawm nplooj 7
  Sau cov pins thiab I / O cov qauv koj tuaj yeem muab rau hauv cov khoom siv txhawb Intel FPGA rau BLVDS daim ntawv thov.
• Tsim Examprau AN522
  Muab Intel Quartus Prime tsim examples siv hauv daim ntawv thov no.

Tsim Example Cov Lus Qhia rau Txhua Cov Khoom Txhawb Nqa Tsuas Yog Intel Arria 10, Intel Cyclone 10 GX, thiab Intel MAX 10

Cov kauj ruam no siv tau rau txhua qhov kev txhawb nqa tshwj tsis yog Intel Arria 10, Intel Cyclone 10 GX, thiab Intel MAX 10. Xyuas kom meej tias koj siv ALTIOBUF IP core.

1.  Tsim ib qho ALTIOBUF IP core uas tuaj yeem txhawb nqa ob txoj kev tawm tswv yim thiab tso tawm tsis tawm:
   • ib. Instantiate lub ALTIOBUF IP core.
   • b. Configure lub module Raws li ib tug bidirectional tsis.
   • c. Nyob rau hauv dab tsi yog tus naj npawb ntawm buffers yuav tsum instantiated, sau 1.
   • d. Qhib Siv hom sib txawv.
2. Txuas cov modules thiab cov input thiab output ports raws li qhia hauv daim duab hauv qab no:
    Input thiab Output Ports Connection Example rau Tag Nrho Cov Cuab Yeej Txhawb Ntxiv Tsuas yog Intel Arria 10, Intel Cyclone 10 GX, thiab Intel MAX 10 Devices
3. Nyob rau hauv Tus Thawj Saib Xyuas Haujlwm, muab tus qauv I/O cuam tshuam raws li qhia hauv daim duab hauv qab no raws li koj lub cuab yeej. Koj tuaj yeem teeb tsa lub zog tam sim no thiab kev xaiv tus nqi slew. Tsis tas li ntawd, Intel Quartus Prime software xav tias qhov chaw pib.
   • Intel Cyclone 10 LP, Cyclone IV, Cyclone III, thiab Cyclone III LS li-BLVDS I/O standard to the bidirectional p and n pins as displayed in the following picture.
   • Stratix V, Stratix IV, Stratix III, Arria V, Arria II, thiab Cyclone V li—Differential SSTL-2 Class I lossis Class II I/O standard.
     BLVDS I/O Assignment hauv Intel Quartus Prime Assignment EditorNco tseg: Koj tuaj yeem muab ob qho tib si p thiab n tus pin qhov chaw rau txhua lub cuab yeej txhawb nqa nrog Tus Thawj Saib Xyuas Haujlwm. Rau cov cuab yeej txhawb nqa thiab cov pins koj tuaj yeem muab manually, xa mus rau cov ntaub ntawv ntsig txog.
4. Sau thiab ua haujlwm simulation nrog ModelSim - Intel FPGA Edition software.

Example ntawm Functional Simulation Results
Thaum lub teeb liab oe tau lees paub, BLVDS nyob rau hauv hom kev sau ntawv. Thaum lub teeb liab oe yog deasserted, BLVDS nyob rau hauv kev nyeem ntawv hom.Nco tseg:
Rau kev simulation siv Verilog HDL, koj tuaj yeem siv blvds_tb.v testbench, uas yog suav nrog cov qauv tsim ex.ample.
Cov ntaub ntawv ntsig txog

• ModelSim - Intel FPGA Edition Software Support
  Muab cov ntaub ntawv ntau ntxiv txog ModelSim - Intel FPGA Edition software thiab muaj ntau yam txuas rau cov ncauj lus xws li kev teeb tsa, kev siv, thiab kev daws teeb meem.
• I/O Standards for BLVDS Interface in Intel FPGA Devices ntawm nplooj 7
  Sau cov pins thiab I / O cov qauv koj tuaj yeem muab rau hauv cov khoom siv txhawb Intel FPGA rau BLVDS daim ntawv thov.
• Tsim Examprau AN522
  Muab Intel Quartus Prime tsim examples siv hauv daim ntawv thov no.

Kev Ntsuam Xyuas Kev Ua Haujlwm

Lub multipoint BLVDS kev soj ntsuam kev ua tau zoo qhia tau hais tias qhov cuam tshuam ntawm kev tshem tawm lub tsheb npav, kev thauj khoom, tus neeg tsav tsheb thiab tus neeg txais cov yam ntxwv, thiab qhov chaw ntawm lub receiver ntawm tus tsav tsheb ntawm lub system. Koj tuaj yeem siv qhov suav nrog BLVDS tsim examples los txheeb xyuas qhov ua tau zoo ntawm daim ntawv thov multipoint:

•  Cyclone III BLVDS design example — this design example yog siv tau rau txhua qhov kev txhawb nqa Stratix, Arria, thiab Cyclone ntaus ntawv series. Rau Intel Arria 10 lossis Intel Cyclone 10 GX ntaus ntawv tsev neeg, koj yuav tsum tau tsiv mus rau tus tsim example mus rau tsev neeg cov cuab yeej ua ntej ua ntej koj siv tau.
• Intel MAX 10 BLVDS tsim example — this design example yog muaj feem xyuam rau Intel MAX 10 ntaus ntawv tsev neeg.
• Intel Stratix 10 BLVDS tsim example — this design example yog muaj feem xyuam rauIntel Stratix 10 ntaus ntawv tsev neeg.

Nco tseg:
Kev soj ntsuam kev ua tau zoo ntawm multipoint BLVDS hauv ntu no yog ua raws li Cyclone III BLVDS input/output buffer information specification (IBIS) model simulation in HyperLynx*.
Intel xav kom koj siv cov Intel IBIS qauv no rau simulation:

• Stratix III, Stratix IV, thiab Stratix V cov khoom siv-cov cuab yeej tshwj xeeb sib txawv SSTL-2 IBIS qauv
• Intel Stratix 10, Intel Arria 10 (2) thiab Intel Cyclone 10 GX li:
  •  Output tsis-Differential SSTL-18 IBIS qauv
  • Input buffer-LVDS IBIS model

Cov ntaub ntawv ntsig txog

• Intel FPGA IBIS Model page
  Muab kev rub tawm ntawm Intel FPGA cov qauv khoom siv.
•  Tsim Examprau AN522
  Muab Intel Quartus Prime tsim examples siv hauv daim ntawv thov no.

Kev teeb tsa

 Multipoint BLVDS nrog Cyclone III BLVDS Transceivers
Daim duab no qhia txog cov schematic ntawm ib qho kev qhia ntau yam nrog kaum Cyclone III BLVDS transceivers (lub npe U1 txog U10).Lub tsheb npav kis tau tus mob yog xav tias muaj cov yam ntxwv hauv qab no:

•  Ib kab kab
•  Yam ntxwv impedance ntawm 50 Ω
• Tus yam ntxwv capacitance ntawm 3.6 pF ib nti
•  Ntev ntawm 10 ntiv tes
• Intel Arria 10 IBIS qauv yog ua ntej thiab tsis muaj nyob rau ntawm Intel IBIS qauv web nplooj. Yog tias koj xav tau cov qauv ua ntej Intel Arria 10 IBIS, hu rau Intel.
• Bus sib txawv tus yam ntxwv impedance ntawm kwv yees li 100 Ω
•  Qhov sib nrug ntawm txhua qhov transceiver ntawm 1 nti
• Lub tsheb npav raug txiav ntawm ob qho kawg nrog kev txiav tawm RT

• Default tsav zog ntawm 12 mA
• Slow slew nqi nqis los ntawm lub neej ntawd
• Pin capacitance ntawm txhua tus transceiver ntawm 6 pF
•  Stub ntawm txhua BLVDS transceiver yog 1-nti microstrip ntawm tus yam ntxwv impedance ntawm 50 Ω thiab tus yam ntxwv capacitance ntawm 3 pF ib nti
•  Capacitance ntawm kev sib txuas (connector, ncoo, thiab ntawm hauv PCB) ntawm txhua lub transceiver rau lub npav yog suav tias yog 2 pF
• Tag nrho capacitance ntawm txhua qhov load yog kwv yees li 11 pF

Rau 1-nti load spacing, qhov kev faib tawm yog sib npaug rau 11 pF ib nti. Txhawm rau txo qhov kev xav tau tshwm sim los ntawm cov stubs, thiab tseem kom txo qis cov teeb liab tawm ntawm
tus tsav tsheb, ib qho impedance txuam 50 Ω resistor RS yog muab tso rau ntawm qhov tso zis ntawm txhua lub transceiver.

Chaw nres tsheb npav
Qhov zoo impedance ntawm lub tsheb thauj khoom tag nrho yog 52 Ω yog ​​tias koj hloov lub tsheb npav tus yam ntxwv capacitance thiab cov kev faib tawm ntawm ib chav tsev ntev ntawm kev teeb tsa rau hauv qhov sib txawv impedance sib npaug. Rau qhov zoo tshaj plaws teeb liab kev ncaj ncees, koj yuav tsum phim RT rau 52 Ω. Cov duab hauv qab no qhia txog qhov cuam tshuam ntawm kev sib tw-, hauv qab-, thiab tshaj-tawm ntawm qhov sib txawv waveform (VID) ntawm tus receiver input pins. Cov ntaub ntawv tus nqi yog 100 Mbps. Hauv cov duab no, kev txiav tawm qis (RT = 25 Ω) ua rau muaj kev cuam tshuam thiab txo qis ntawm cov suab nrov nrov. Qee qhov xwm txheej, nyob rau hauv kev txiav tawm txawm ua txhaum tus neeg txais qhov pib (VTH = ± 100 mV). Thaum RT hloov mus rau 50 Ω, muaj lub suab nrov nrov nrog rau VTH thiab qhov kev xav tsis zoo.

Qhov cuam tshuam ntawm kev caij npav npav (Tsav tsheb hauv U1, Txais hauv U2)
Nyob rau hauv daim duab no, U1 ua tus transmitter thiab U2 rau U10 yog tus txais.

Qhov cuam tshuam ntawm kev caij npav npav (Tsav tsheb hauv U1, Txais hauv U10)
Nyob rau hauv daim duab no, U1 ua tus transmitter thiab U2 rau U10 yog tus txais.

Qhov cuam tshuam ntawm kev caij npav npav (Tsav tsheb hauv U5, Txais hauv U6)
Nyob rau hauv daim duab no, U5 yog lub transmitter thiab tus so yog txais.

Qhov cuam tshuam ntawm kev caij npav npav (Tsav tsheb hauv U5, Txais hauv U10)
Nyob rau hauv daim duab no, U5 yog lub transmitter thiab tus so yog txais.Tus txheeb ze txoj hauj lwm ntawm tus neeg tsav tsheb thiab tus neeg txais xov tooj ntawm lub tsheb npav kuj cuam tshuam rau qhov tau txais cov teeb liab zoo. Tus neeg txais xov tooj ze tshaj plaws rau tus neeg tsav tsheb tau ntsib qhov kev sib kis kab mob phem tshaj plaws vim tias ntawm qhov chaw no, tus nqi ntug yog qhov ceev tshaj plaws. Qhov no yog ua phem dua thaum tus tsav tsheb nyob nruab nrab ntawm lub npav.
Rau example, piv rau daim duab 16 ntawm nplooj ntawv 20 thiab daim duab 18 ntawm nplooj ntawv 21. VID ntawm receiver U6 (tus tsav tsheb ntawm U5) qhia tau hais tias lub suab nrov dua li ntawm tus txais U2 (tus tsav tsheb ntawm U1). Ntawm qhov tod tes, tus nqi ntug yog qeeb qeeb thaum lub receiver nyob deb ntawm tus neeg tsav tsheb. Lub sijhawm nce siab tshaj plaws tau sau tseg yog 1.14 ns nrog tus neeg tsav tsheb nyob ntawm ib kawg ntawm lub npav (U1) thiab tus txais ntawm qhov kawg (U10).

Stub Length
Ntev stub ntev tsis tsuas yog nce lub sij hawm davhlau ntawm tus neeg tsav tsheb mus rau lub receiver, tab sis kuj ua rau ib tug loj load capacitance, uas ua rau loj xav txog.

Qhov cuam tshuam ntawm Kev Tshaj Tawm Ntev Ntev (Tsav Tsheb hauv U1, Txais hauv U10)
Daim duab no piv rau VID ntawm U10 thaum lub qhov ntev ntawm tus ncej yog nce los ntawm ib nti mus rau ob nti thiab tus tsav tsheb nyob ntawm U1.

Stub Termination
Koj yuav tsum phim tus neeg tsav tsheb impedance rau lub stub yam ntxwv impedance. Muab ib tug series termination resistor RS ntawm tus neeg tsav tsheb tso zis zoo heev txo qhov tsis zoo kis kab mob tshwm sim los ntawm ntev stub thiab ceev ntug tus nqi. Tsis tas li ntawd, RS tuaj yeem hloov pauv kom txo qis VID kom ua tau raws li qhov tshwj xeeb ntawm tus txais.

Qhov cuam tshuam ntawm Stub Termination (Driver in U1, Receiver in U2 and U10)
Daim duab no piv VID ntawm U2 thiab U10 thaum U1 kis tau.

Tus Tsav Tsheb Slew Rate
Tus nqi nrawm nrawm pab txhim kho lub sijhawm nce, tshwj xeeb tshaj yog nyob rau ntawm tus neeg txais kev pom zoo tshaj plaws ntawm tus neeg tsav tsheb. Txawm li cas los xij, tus nqi nrawm dua kuj tseem ua kom nrov nrov vim yog kev xav.

Cov nyhuv ntawm Tus Tsav Tsheb Edge Rate (Tsav Tsheb hauv U1, Txais hauv U2 thiab U10)
Daim duab no qhia txog tus neeg tsav tsheb slew npaum li cas. Kev sib piv yog tsim los ntawm qhov qeeb thiab nrawm nrawm nrog 12 mA tsav lub zog. Tus tsav tsheb yog nyob ntawm U1 thiab qhov sib txawv waveforms ntawm U2 thiab U10 raug tshuaj xyuas.

Zuag qhia tag nrho System Performance

Cov ntaub ntawv siab tshaj plaws uas txhawb nqa los ntawm multipoint BLVDS yog txiav txim siab los ntawm kev saib daim duab lub qhov muag ntawm tus neeg tau txais deb tshaj plaws los ntawm tus tsav tsheb. Ntawm qhov chaw no, cov teeb liab kis tau tus nqi qis tshaj plaws thiab cuam tshuam rau qhov muag qhib. Txawm hais tias qhov zoo ntawm cov teeb liab tau txais thiab lub suab nrov lub hom phiaj yog nyob ntawm cov ntawv thov, qhov dav ntawm qhov muag qhib, qhov zoo dua. Txawm li cas los xij, koj yuav tsum tau kuaj xyuas lub receiver ze tshaj plaws rau tus neeg tsav tsheb, vim tias cov kab sib kis tau zoo dua yog tias tus txais yuav nyob ze rau tus tsav tsheb.
Daim duab 23. Daim duab qhov muag ntawm 400 Mbps (Tus Tsav Tsheb hauv U1, Tus Txais hauv U2 thiab U10)
Daim duab no qhia txog daim duab qhov muag ntawm U2 (liab nkhaus) thiab U10 (xiav nkhaus) rau cov ntaub ntawv tus nqi ntawm 400 Mbps. Random jitter ntawm 1% chav nyob ib ntus yog xav hauv qhov simulation. Tus neeg tsav tsheb yog nyob ntawm U1 nrog lub zog tam sim no thiab cov nqi sib tw. Lub tsheb npav yog tag nrho loaded nrog optimum RT = 50 Ω. Qhov qhib qhov muag tsawg tshaj plaws yog nyob ntawm U10, uas yog nyob deb tshaj ntawm U1. Qhov muag qhov siab sampcoj ntawm 0.5 chav nyob ib ntus yog 692 mV thiab 543 mV rau U2 thiab U10, feem. Muaj lub suab nrov nrov nrog rau VTH = ± 100 mV rau ob qho tib si.

Cov Ntaub Ntawv Hloov Kho Keeb Kwm rau AN 522: Siv Tsheb Npav LVDS Interface hauv Kev Txhawb Intel FPGA Cov Tsev Neeg

Cov ntaub ntawv / Cov ntaub ntawv

intel AN 522 Kev Siv Tsheb Npav LVDS Interface hauv Kev Txhawb FPGA Cov Tsev Neeg [ua pdf] Cov neeg siv phau ntawv qhia AN 522 Kev Siv Tsheb Npav LVDS Interface hauv Kev Txhawb FPGA Cov Tsev Neeg, AN 522, Kev Siv Tsheb Npav LVDS Interface hauv Kev Txhawb FPGA Cov Tsev Neeg, Kev Sib Tham hauv Kev Txhawb FPGA Cov Tsev Neeg, FPGA Cov Tsev Neeg

Cov ntaub ntawv

• Cov neeg siv phau ntawv