intel AN 522 Kuita Bhazi LVDS Interface mune Inotsigirwa FPGA Chishandiso Mhuri

Bhazi LVDS (BLVDS) rinowedzera kugona kweLVDS point-to-point kutaurirana kune multipoint kumisikidza. Multipoint BLVDS inopa mhinduro inoshanda kune multipoint backplane application.

BLVDS Implementation Tsigiro muIntel FPGA Zvishandiso

Unogona kushandisa BLVDS interfaces mune idzi Intel zvishandiso uchishandisa yakanyorwa I/O zviyero.

Cherechedza:
Iyo programmable dhiraivha simba uye akauraya chiyero maficha mumidziyo iyi inobvumidza iwe kugadzirisa yako multipoint sisitimu yekushanda kwakanyanya. Kuti uone huwandu hwehuwandu hwe data hunotsigirwa, ita simulation kana kuyerwa zvichibva pane yako chaiyo sisitimu yekuseta uye kushandisa.
BLVDS Pamusoroview papeji 4
BLVDS Tekinoroji muIntel Zvishandiso pane peji 6
BLVDS Simba Kushandisa pane peji 9
BLVDS Dhizaini Exampiri papeji 10
Performance Ongororo iri papeji 17
Gwaro Rekudzokorora Nhoroondo yeAN 522: Kuita Bhazi LVDS Interface muInotsigirwa Intel FPGA Chishandiso Mhuri pane peji 25.
Related Information
I/O Mayero eBLVDS Interface muIntel FPGA Zvishandiso pane peji 7

BLVDS Pamusoroview

Yakajairika multipoint BLVDS system ine akati wandei ekutumira uye anogamuchira maviri maviri (transceivers) akabatana nebhazi.
Multipoint BLVDSIyo gadziriso mumufananidzo wapfuura inopa bidirectional hafu-duplex kutaurirana uku ichideredza kubatanidza density. Chero transceiver inogona kutora basa rekutapurirana, nematransceivers asara achiita sevanogamuchira (mupepeti mumwe chete anogona kushanda panguva). Bus traffic control, kungave kuburikidza neprotocol kana hardware mhinduro inowanzodiwa kudzivirira kukakavara kwemutyairi mubhazi. Kuita kwemultipoint BLVDS kunokanganisa zvakanyanya ne capacitive kurodha uye kupera mubhazi.
Kufunga Kwekugadzira
Iyo yakanaka multipoint dhizaini inofanirwa kufunga nezve capacitive mutoro uye kumisa mubhazi kuti uwane zvirinani chiratidzo chekuvimbika. Iwe unogona kuderedza mutoro wekutakura nekusarudza transceiver ine yakaderera pini capacitance, yekubatanidza ine yakaderera capacitance, uye kuchengeta iyo stub kureba kupfupi. Imwe yemultipoint BLVDS dhizaini yekutarisisa ndiyo inoshanda mutsauko webhazi rakazara rakazara, rinonzi rinoshanda impedance, uye kunonoka kuparadzira kuburikidza nebhazi. Dzimwe multipoint BLVDS dhizaini yekutarisisa inosanganisira kutadza-kuchengetedza kurerekera, yekubatanidza mhando uye pini-kunze, PCB bhazi trace marongero, uye mutyairi mupendero chiyero.
Inoshanda Impedance
Iyo impedance inoshanda inoenderana nebhazi trace hunhu impedance Zo uye capacitive kurodha mubhazi. Izvo zvinobatanidza, iyo stub pane plug-in kadhi, iyo yekurongedza, uye inogamuchira yekuisa capacitance zvese zvinopa capacitive kurodha, izvo zvinoderedza bhazi rinoshanda impedance.
Equation 1. Effective Differential Impedance Equation
Shandisa iyi equation kufungidzira mutsauko unoshanda webhazi rakatakura (Zeff).Kupi:

• Zdiff (Ω) ≈ 2 × Zo = iyo inosiyanisa hunhu impedance yebhazi
•  Co (pF/inch) = hunhu capacitance per unit urefu hwebhazi
• CL (pF) = capacitance yemutoro wega wega
•  N = nhamba yemitoro mubhazi
•  H (inch) = d × N = kureba kwebhazi
•  d (inch) = nzvimbo pakati pekadhi yega yega plug-in
•  Cd (pF/inch) = CL/d = capacitance yakagoverwa paurefu hweyuniti mubhazi

Iyo increment mukuremerwa capacitance kana padyo nzvimbo pakati pe-plug-in makadhi inoderedza iyo inoshanda impedance. Kuti uwedzere kushanda kwehurongwa, zvakakosha kusarudza yakaderera capacitance transceiver uye connector. Chengetedza hurefu hwega hwega hwekugamuchira pakati pechibatanidza uye transceiver I/O pini ipfupi sezvinobvira.
Normalized Inoshanda Impedance Versus Cd/Co
Iyi nhamba inoratidza mhedzisiro yekugoverwa capacitance pane yakajairwa inoshanda impedance.Kubviswa kunodiwa pamagumo ebhazi, nepo data ichiyerera munzira mbiri. Kuti udzikise kutarisisa uye kurira mubhazi, iwe unofanirwa kuenzanisa iyo yekumisa resistor kune inoshanda impedance. Kune system ine Cd/Co = 3, iyo impedance inoshanda ndeye 0.5 nguva dzeZdiff. Nekugumisa kaviri pabhazi, mutyairi anoona mutoro wakaenzana we0.25 nguva dzeZdiff; uye nekudaro inoderedza masiginecha anozununguka uye mutsauko weruzha margin pane anogashira mapikisi (kana yakajairwa LVDS mutyairi akashandiswa). Mutyairi weBLVDS anogadzirisa nyaya iyi nekuwedzera dhiraivha iripo kuti iwane yakafanana voltage swing pazvigadziro zvekugamuchira.
Propagation Kunonoka
Kunonoka kuparadzira (tPD = Zo × Co) ndiyo nguva yekunonoka kuburikidza netambo yekutapurirana pakureba kweyuniti. Izvo zvinoenderana nehunhu impedance uye hunhu
kugona kwebhazi.
Kubudirira Kunonoka Kuparadzira
Kune bhazi rakatakura, unogona kuverenga kunonoka kushambadza kunoshanda neiyi equation. Unogona kuverenga nguva yekuti chiratidzo chipararire kubva kumutyairi A kuenda kunogamuchira B se tPDEFF × kureba kwemutsara pakati pemutyairi A uye anogamuchira B.

BLVDS Technology muIntel Devices

Mumidziyo yeIntel inotsigirwa, iyo BLVDS interface inotsigirwa mune chero mutsara kana koramu I/ mabhangi anofambiswa neVCCIO ye1.8 V (Intel Arria 10 uye Intel Cyclone 10 GX zvishandiso) kana 2.5 V (zvimwe zvinotsigirwa zvinoshandiswa). Mune aya mabhangi eI/O, iyo interface inotsigirwa pamapini eI/O akasiyana asi kwete pane yakatsaurirwa wachi yekuisa kana mapini ekubuda kwewachi. Nekudaro, muIntel Arria 10 uye Intel Cyclone 10 GX zvishandiso, iyo BLVDS interface inotsigirwa pamapini ewachi akazvitsaurira anoshandiswa senge maI/Os.

•  Iyo BLVDS transmitter inoshandisa maviri-apera-inogumira kuburitsa buffer neyechipiri inobuda buffer yakarongwa seyakapinzwa.
•  Iyo BLVDS inogamuchira inoshandisa yakatsaurirwa LVDS yekuisa buffer.

BLVDS I/O Buffers muMidziyo InotsigirwaShandisa akasiyana ekuisa kana anobuda mabuffer zvichienderana nerudzi rwekushandisa:

• Multidrop application - shandisa iyo yekuisa kana inoburitsa buffer zvichienderana nekuti mudziyo wakagadzirirwa mutyairi kana unogamuchira kushanda.
• Multipoint application-iyo inoburitsa buffer uye yekuisa buffer inogovera zvakafanana I/O pini. Iwe unoda chinobuda chinogonesa (oe) chiratidzo chetatu-kutaura iyo LVDS inobuda buffer kana isiri kutumira masaini.
•  Usagone kugonesa iyo-chip-yakatevedzana kumisa (RS OCT) kune inobuda buffer.
• Shandisa zvekunze zvinopikisa pane zvinobuda mabuffers kupa impedance inoenderana neiyo stub pane plug-in kadhi.
• Usagonese iyo on-chip differential kumisa (RD OCT) yemusiyano wekuisa buffer nekuti kumisa bhazi kunowanzo itwa uchishandisa ekunze ekumisa anopikisa kumigumo yese yebhazi.

I/O Zviyero zveBLVDS Interface muIntel FPGA Zvishandiso
Iwe unogona kuita iyo BLVDS interface uchishandisa yakakodzera I / O zviyero uye zvazvino simba zvinodiwa kune inotsigirwa Intel zvishandiso.
I/O Yakajairwa uye Zvimiro Tsigiro yeBLVDS Interface muInotsigirwa Intel Devices

1.  DIFFIO_TX pini haitsigire yechokwadi LVDS mutsauko vanogamuchira.

Kuti uwane rumwe ruzivo, tarisa kune anoenderana magwaro emudziyo sezvakarongwa mune inoenderana ruzivo chikamu:

• Kuti uwane ruzivo rwemapini ebasa, tarisa kune pin-out yemudziyo files.
• Nezvezviyero zveI/O, tarisa kubhuku rekushandisa I/O chitsauko.
•  Nezvezvakatemwa zvemagetsi, tarisa kune dhatabheti remudziyo kana DC uye nekuchinja maitiro gwaro.

Related Information

•  Intel Stratix 10 Pin-Out Files
•  Stratix V Pin-Out Files
• Stratix IV Pin-Out Files
•  Stratix III Chishandiso Pin-Out Files
•  Intel Arria 10 Chidimbu Pin-Out Files
•  Arria V Device Pin-Out Files
•  Arria II GX Device Pin-Out Files
• Intel Cyclone 10 GX Device Pin-Out Files
• Intel Cyclone 10 LP Chishandiso Pin-Out Files
• Cyclone V Device Pin-Out Files
•  Cyclone IV Device Pin-Out Files
• Cyclone III Device Pin-Out Files
• Intel MAX 10 Chishandiso Pin-Out Files
• Intel Stratix 10 General Chinangwa I/O User Guide
•  I/O Zvimiro muStratix V Zvishandiso
•  I/O Zvimiro muStratix IV Chishandiso
•  Stratix III Chishandiso I/O Zvimiro
• I/O Zvimiro muStratix V Zvishandiso
•  I/O Zvimiro muStratix IV Chishandiso
•  Stratix III Chishandiso I/O Zvimiro
•  I/O uye High Speed ​​I/O muIntel Arria 10 Devices
•  I/O Zvimiro muArria V Devices
• I/O Zvimiro muArria II Devices
•  I/O uye High Speed ​​I/O muIntel Cyclone 10 GX Devices
•  I/O uye High Speed ​​I/O muIntel Cyclone 10 LP Devices
• I/O Zvimiro muCyclone V Devices
• I/O Zvimiro muCyclone IV Devices
•  I/O Zvimiro muCyclone III Chishandiso Mhuri
• Intel MAX 10 General Chinangwa I/O Mushandisi Gwaro
•  Intel Stratix 10 Device Datasheet
• Stratix V Device Datasheet
•  DC uye Kuchinja Hunhu hweStratix IV Zvishandiso
•  Stratix III Device Datasheet: DC uye Kuchinja Hunhu
•  Intel Arria 10 Device Datasheet
•  Arria V Device Datasheet
• Device Datasheet yeArria II Devices
• Intel Cyclone 10 GX Device Datasheet
•  Intel Cyclone 10 LP Device Datasheet
•  Cyclone V Device Datasheet
•  Cyclone IV Device Datasheet
• Cyclone III Device Datasheet
• Intel MAX 10 Device Datasheet

BLVDS Simba Kushandisa

• Usati waita dhizaini yako mumudziyo, shandisa iyo Excel-based EPE yechishandiso chinotsigirwa chaunoshandisa kuti uwane fungidziro yehukuru hweBLVDS I/O mashandisiro emagetsi.
•  Kune mapini ekupinza uye maviri, iyo BLVDS yekuisa buffer inogara ichigoneswa. Iyo BLVDS yekupinza buffer inoshandisa simba kana paine switching chiitiko mubhazi (yeexampuye, mamwe matransceivers ari kutumira uye kugamuchira data, asi Cyclone III mudziyo hausi iwo waanoda kugamuchira).
•  Kana iwe ukashandisa BLVDS senge yekuisa buffer mune multidrop kana se bidirectional buffer mune multipoint application, Intel inokurudzira kupinda muyero wekuchinja unosanganisira zvese zviitiko mubhazi, kwete chete zviitiko zvakaitirwa Intel mudziyo BLVDS yekupinza buffer.

Example yeBLVDS I/O Kupinda kweData muEPE
Iyi nhamba inoratidza BLVDS I/O kupinda muCyclone III EPE. Kune maI/O zviyero zvekusarudza muEPE yezvimwe zvinotsigirwa zveIntel zvishandiso, tarisa kune ruzivo rwakabatana.Intel inokurudzira kuti ushandise Intel Quartus Prime Power Analyzer Tool kuita chaiyo BLVDS I/O simba rekuongorora mushure mekunge wapedza dhizaini yako. Iyo Power Analyzer Tool inofungidzira simba zvichienderana neiyo chaiyo dhizaini mushure menzvimbo-uye-nzira yapera. Iyo Power Analyzer Turusi inoshandisa musanganiswa weakapinda-mushandisi, simulation-yakatorwa, uye inofungidzirwa zviitwa zvechiratidzo izvo, zvakasanganiswa neakadzama edunhu modhi, zvinopa fungidziro yesimba chaiyo.
Related Information

• Power Analysis chitsauko, Intel Quartus Prime Pro Edition Handbook
  Inopa rumwe ruzivo nezve Intel Quartus Prime Pro Edition Power Analyzer chishandiso cheIntel Stratix 10, Intel Arria 10, uye Intel Cyclone 10 GX mudziyo mhuri.
• Power Analysis chitsauko, Intel Quartus Prime Standard Edition Handbook
  Inopa rumwe ruzivo nezve Intel Quartus Prime Standard Edition Power Analyzer chishandiso cheStratix V, Stratix IV, Stratix III, Arria V, Arria II, Intel Cyclone 10 LP, Cyclone V, Cyclone IV, Cyclone III LS, Cyclone III, uye Intel. MAX 10 mudziyo mhuri.
• Early Power Estimators (EPE) uye Power Analyzer peji
  Inopa rumwe ruzivo nezve EPE uye Intel Quartus Prime Power Analyzer chishandiso.
• Kuita Bhazi LVDS Interface muInotsigirwa Intel FPGA Chishandiso Mhuri pane peji 3
  Inonyora zviyero zveI/O zvekusarudza muEPE kufungidzira mashandisirwo emagetsi eBLVDS.

BLVDS Dhizaini Example
Iyo yakagadzirwa example inokuratidza maitiro ekumisikidza iyo BLVDS I/O buffer mumidziyo inotsigirwa ine yakakosha chinangwa I/O (GPIO) IP cores muIntel Quartus Prime software.

•  Intel Stratix 10, Intel Arria 10, uye Intel Cyclone 10 GX zvishandiso-shandisa iyo GPIO Intel FPGA IP musimboti.
•  Intel MAX 10 zvishandiso-shandisa iyo GPIO Lite Intel FPGA IP musimboti.
•  Zvimwe zvese zvinotsigirwa-shandisa iyo ALTIOBUF IP musimboti.

Unogona kudhawunirodha dhizaini example kubva pane chinongedzo mune ruzivo rwakabatana. Kune iyo BLVDS I / O buffer muenzaniso, Intel inokurudzira zvinotevera zvinhu:

•  Shandisa iyo GPIO IP musimboti mune bidirectional modhi ine yekusiyanisa modhi yakabatidzwa.
•  Ipa iyo I/O chiyero kune bidirectional pini:
•  BLVDS-Intel Cyclone 10 LP, Cyclone IV, Cyclone III, uye Intel MAX 10 zvishandiso.
•  Yakasiyana SSTL-2 Kirasi I kana Kirasi II—Stratix V, Stratix IV, Stratix III, Arria V, Arria II, uye Cyclone V zvishandiso.
• Yakasiyana SSTL-18 Kirasi I kana Kirasi II-Intel Stratix 10, Intel Arria 10, uye Intel Cyclone 10 GX zvishandiso.

Input kana Output Buffers Operation Panguva Yekunyora uye Kuverenga Mashandiro

• Iyo oe port inogamuchira iyo oe chiratidzo kubva kumudziyo wemudziyo kugonesa kana kudzima iyo-inopera-inobuda mabuffers.
•  Chengetedza chiratidzo che oe chakaderera kuti utaure-zvinobuda mabhafa panguva yekuverenga kushanda.
•  Basa reiyo AND gedhi nderekumisa iyo inofambiswa chiratidzo kubva pakudzokera mumudziyo wemudziyo. Musiyano wekuisa bhafa unogara uchigoneswa.

Related Information

•  I/O Buffer (ALTIOBUF) IP Core User Guide
•  GPIO IP Core User Guide
•  Intel MAX 10 I/O Implementation Guides
• Nhanganyaya kuIntel FPGA IP Cores
• Design Exampzvishoma zve AN 522

Inopa iyo Intel Quartus Prime dhizaini exampmashoma anoshandiswa mune ino application note.
Design Example Nhungamiro yeIntel Stratix 10 Devices
Aya matanho anoshanda kune Intel Stratix 10 zvishandiso chete. Ita shuwa kuti unoshandisa iyo GPIO Intel FPGA IP musimboti.

1. Gadzira iyo GPIO Intel FPGA IP musimboti inogona kutsigira bidirectional yekupinda uye inobuda buffer:
   • a. Isa iyo GPIO Intel FPGA IP musimboti.
   • b. MuDaidhi yeData, sarudza Bidir.
   • c. MuData upamhi, isa 1.
   • d. Batidza Shandisa musiyano bhafa.
   • e. MuRejista mode, sarudza hapana.
2. Batanidza mamodule uye yekupinza uye yekubuda ports sezvakaratidzwa mumufananidzo unotevera:
   Input uye Output Ports Connection Example yeIntel Stratix 10 Devices
3. MuMupepeti Wekutumwa, govera iyo yakakodzera I/O mwero sezvakaratidzwa mumufananidzo unotevera. Iwe unogona zvakare kuseta yazvino simba uye akauraya chiyero sarudzo. Zvikasadaro, iyo Intel Quartus Prime software inotora iyo default marongero.
   BLVDS I/O Basa muIntel Quartus Prime Assignment Edhita yeIntel Stratix 10 Devices.
4. Unganidza uye ita mashandiro ekuenzanisa neModelSim* - Intel FPGA Edition software.

Related Information

• ModelSim - Intel FPGA Edition Software Tsigiro
  Inopa rumwe ruzivo nezve ModelSim - Intel FPGA Edition software uye ine akasiyana-siyana ekubatanidza kumisoro senge kuisirwa, kushandiswa, uye kugadzirisa matambudziko.
• I/O Mayero eBLVDS Interface muIntel FPGA Zvishandiso pane peji 7
  Inonyora mapini uye I/O zviyero zvaunogona kugovera nemaoko mune inotsigirwa Intel FPGA zvishandiso zveBLVDS application.
• Design Exampzvishoma zve AN 522
  Inopa iyo Intel Quartus Prime dhizaini exampmashoma anoshandiswa mune ino application note.

Design Example Nhungamiro yeIntel Arria 10 Devices
Aya matanho anoshanda kune Intel Arria 10 zvishandiso uchishandisa Intel Quartus Prime Standard Edition chete. Ita shuwa kuti unoshandisa iyo GPIO Intel FPGA IP musimboti.

1. Vhura iyo StratixV_blvds.qar file kuunza kunze iyo Stratix V dhizaini exampuye muIntel Quartus Prime Standard Edition software.
2. Kutama dhizaini example kushandisa GPIO Intel FPGA IP musimboti:
   • a. Pamenu, sarudza Chirongwa ➤ Simudzira IP Zvikamu.
   • b. Dzvanya kaviri chikamu che "ALIOBUF".
     Iyo MegaWizard Plug-In Manager hwindo reALTIOBUF IP musimboti rinoonekwa.
   • c. Dzima Match project/default.
   • d. Mumhuri yemudziyo yakasarudzwa parizvino, sarudza Arria 10.
   • e. Dzvanya Finish wobva wadzvanya Finish zvakare.
   • f. Mubhokisi renhaurirano rinoonekwa, tinya OK.
     Iyo Intel Quartus Prime Pro Edition software inoita maitiro ekufambisa uye yobva yaratidza iyo GPIO IP parameter mupepeti.
3. Gadzirisa iyo GPIO Intel FPGA IP musimboti kutsigira bidirectional yekupinda uye inobuda buffer:
   • a. MuDaidhi yeData, sarudza Bidir.
   • b. MuData upamhi, isa 1.
   • c. Batidza Shandisa musiyano bhafa.
   • d. Dzvanya Pedzisa uye gadzira iyo IP musimboti.
4. Batanidza mamodule uye yekupinza uye yekubuda ports sezvakaratidzwa mumufananidzo unotevera:
   Input uye Output Ports Connection Example yeIntel Arria 10 Devices
5. MuMupepeti Wekutumwa, govera iyo yakakodzera I/O mwero sezvakaratidzwa mumufananidzo unotevera. Iwe unogona zvakare kuseta yazvino simba uye akauraya chiyero sarudzo. Zvikasadaro, iyo Intel Quartus Prime Standard Edition software inotora zvigadziriso zveIntel Arria gumi zvishandiso-Musiyano SSTL-10 Kirasi I kana Kirasi II I/O yakajairwa.
   BLVDS I/O Basa muIntel Quartus Prime Assignment Mharidzo yeIntel Arria 10 Devices.Cherechedza:
   YeIntel Arria 10 zvishandiso, unogona kugovera manyore p uye n pini nzvimbo dzeLVDS pini neAssignment Edhiyo.
6. Unganidza uye ita mashandiro ekuenzanisa neModelSim - Intel FPGA Edition software.

Related Information

• ModelSim - Intel FPGA Edition Software Tsigiro
  Inopa rumwe ruzivo nezve ModelSim - Intel FPGA Edition software uye ine akasiyana-siyana ekubatanidza kumisoro senge kuisirwa, kushandiswa, uye kugadzirisa matambudziko.
• I/O Mayero eBLVDS Interface muIntel FPGA Zvishandiso pane peji 7
  Inonyora mapini uye I/O zviyero zvaunogona kugovera nemaoko mune inotsigirwa Intel FPGA zvishandiso zveBLVDS application.
• Design Exampzvishoma zve AN 522
  Inopa iyo Intel Quartus Prime dhizaini exampmashoma anoshandiswa mune ino application note.

Design Example Nhungamiro yeIntel MAX 10 Devices
Aya matanho anoshanda kune Intel MAX 10 zvishandiso chete. Ita shuwa kuti unoshandisa iyo GPIO Lite Intel FPGA IP musimboti.

1. Gadzira iyo GPIO Lite Intel FPGA IP musimboti iyo inogona kutsigira bidirectional yekupinda uye inobuda buffer:
   • a. Isa iyo GPIO Lite Intel FPGA IP musimboti.
   • b. MuDaidhi yeData, sarudza Bidir.
   • c. MuData upamhi, isa 1.
   • d. Batidza Shandisa pseudo differential buffer.
   • e. MuRejista mode, sarudza Bypass.
2. Batanidza mamodule uye yekupinza uye yekubuda ports sezvakaratidzwa mumufananidzo unotevera:
    Input uye Output Ports Connection Example yeIntel MAX 10 Devices
3. MuMupepeti Wekutumwa, govera iyo yakakodzera I/O mwero sezvakaratidzwa mumufananidzo unotevera. Iwe unogona zvakare kuseta yazvino simba uye akauraya chiyero sarudzo. Zvikasadaro, iyo Intel Quartus Prime software inotora iyo default marongero.
   BLVDS I/O Basa muIntel Quartus Prime Assignment Mharidzo yeIntel MAX 10 Devices.
4. Unganidza uye ita mashandiro ekuenzanisa neModelSim - Intel FPGA Edition software.

Related Information

• ModelSim - Intel FPGA Edition Software Tsigiro
  Inopa rumwe ruzivo nezve ModelSim - Intel FPGA Edition software uye ine akasiyana-siyana ekubatanidza kumisoro senge kuisirwa, kushandiswa, uye kugadzirisa matambudziko.
• I/O Mayero eBLVDS Interface muIntel FPGA Zvishandiso pane peji 7
  Inonyora mapini uye I/O zviyero zvaunogona kugovera nemaoko mune inotsigirwa Intel FPGA zvishandiso zveBLVDS application.
• Design Exampzvishoma zve AN 522
  Inopa iyo Intel Quartus Prime dhizaini exampmashoma anoshandiswa mune ino application note.

Design Example Nhungamiro Yese Anotsigirwa Zvishandiso Kunze kweIntel Arria 10, Intel Cyclone 10 GX, uye Intel MAX 10

Matanho aya anoshanda kumidziyo yese inotsigirwa kunze kweIntel Arria 10, Intel Cyclone 10 GX, uye Intel MAX 10. Iva nechokwadi chekuti unoshandisa ALTIOBUF IP core.

1.  Gadzira iyo ALTIOBUF IP musimboti inogona kutsigira bidirectional yekupinda uye inobuda buffer:
   • a. Isa iyo ALTIOBUF IP musimboti.
   • b. Gadzirisa iyo module Se bidirectional buffer.
   • c. In Ndeipi nhamba yebhafa yekumisikidzwa, isa 1.
   • d. Batidza Shandisa differential mode.
2. Batanidza mamodule uye yekupinza uye yekubuda ports sezvakaratidzwa mumufananidzo unotevera:
    Input uye Output Ports Connection Example kune Yese Anotsigirwa Zvishandiso Kunze kweIntel Arria 10, Intel Cyclone 10 GX, uye Intel MAX 10 Devices.
3. MuIyo Yekugovera Edhita, govera iyo yakakodzera I/O chiyero sezvakaratidzwa mumufananidzo unotevera maererano nemudziyo wako. Iwe unogona zvakare kuseta yazvino simba uye akauraya chiyero sarudzo. Zvikasadaro, iyo Intel Quartus Prime software inotora iyo default marongero.
   • Intel Cyclone 10 LP, Cyclone IV, Cyclone III, uye Cyclone III LS zvishandiso-BLVDS I/O yakajairwa kune bidirectional p uye n pini sezvakaratidzwa mumufananidzo unotevera.
   • Stratix V, Stratix IV, Stratix III, Arria V, Arria II, uye Cyclone V zvishandiso—Differential SSTL-2 Kirasi I kana Kirasi II I/O mwero.
     BLVDS I/O Basa muIntel Quartus Prime Assignment EdhitaCherechedza: Iwe unogona kugovera pamaoko ese p uye n pini nzvimbo kune yega yega inotsigirwa mudziyo neAssignment Edhita. Kune zvishandiso zvinotsigirwa uye mapini aunogona kugovera iwe pachako, tarisa kune ruzivo rwakabatana.
4. Unganidza uye ita mashandiro ekuenzanisa neModelSim - Intel FPGA Edition software.

Example ye Functional Simulation Results
Kana iyo oe chiratidzo ichisimbiswa, iyo BLVDS iri mukunyora maitiro ekushanda. Kana iyo oe chiratidzo ichibviswa, iyo BLVDS iri mukuverenga maitiro ekushanda.Cherechedza:
Nekufananidza uchishandisa Verilog HDL, unogona kushandisa blvds_tb.v testbench, iyo inosanganisirwa mune yakasarudzika dhizaini ex.ample.
Related Information

• ModelSim - Intel FPGA Edition Software Tsigiro
  Inopa rumwe ruzivo nezve ModelSim - Intel FPGA Edition software uye ine akasiyana-siyana ekubatanidza kumisoro senge kuisirwa, kushandiswa, uye kugadzirisa matambudziko.
• I/O Mayero eBLVDS Interface muIntel FPGA Zvishandiso pane peji 7
  Inonyora mapini uye I/O zviyero zvaunogona kugovera nemaoko mune inotsigirwa Intel FPGA zvishandiso zveBLVDS application.
• Design Exampzvishoma zve AN 522
  Inopa iyo Intel Quartus Prime dhizaini exampmashoma anoshandiswa mune ino application note.

Performance Analysis

Iyo multipoint BLVDS performance performance inoratidza kukanganisa kwekumisa bhazi, kurodha, mutyairi uye anogamuchira maitiro, uye nzvimbo yeanogamuchira kubva kumutyairi pane system. Iwe unogona kushandisa inosanganisirwa BLVDS dhizaini examples kuongorora kushanda kwemultipoint application:

•  Cyclone III BLVDS dhizaini example-iyi dhizaini example inoshanda kune ese anotsigirwa Stratix, Arria, uye Cyclone mudziyo wakatevedzana. Kune Intel Arria 10 kana Intel Cyclone 10 GX mudziyo mhuri, unofanira kutamisa dhizaini ex.ample kumhuri yemudziyo wakafanira kutanga usati waishandisa.
• Intel MAX 10 BLVDS dhizaini example-iyi dhizaini example inoshanda kune Intel MAX 10 mudziyo mhuri.
• Intel Stratix 10 BLVDS dhizaini example-iyi dhizaini exampiyo inoshanda kuneIntel Stratix 10 mudziyo mhuri.

Cherechedza:
Ongororo yekushanda kwemultipoint BLVDS muchikamu chino yakavakirwa paCyclone III BLVDS yekupinza/output buffer information specification (IBIS) modhi yekutevedzera muHyperLynx*.
Intel inokurudzira kuti ushandise idzi Intel IBIS modhi yekufananidza:

• Stratix III, Stratix IV, uye Stratix V zvishandiso-chaiyo-chaiyo Differential SSTL-2 IBIS modhi
• Intel Stratix 10, Intel Arria 10(2) uye Intel Cyclone 10 GX zvishandiso:
  •  Bafa yekubuda—Musiyano weSSTL-18 IBIS modhi
  • Input bafa-LVDS IBIS modhi

Related Information

• Intel FPGA IBIS Model peji
  Inopa kurodha pasi kweIntel FPGA mudziyo modhi.
•  Design Exampzvishoma zve AN 522
  Inopa iyo Intel Quartus Prime dhizaini exampmashoma anoshandiswa mune ino application note.

System Setup

 Multipoint BLVDS ine Cyclone III BLVDS Transceivers
Huwandu uhu hunoratidza hurongwa hwemultipoint topology ine gumi reCyclone III BLVDS transceivers (inonzi U1 kusvika kuU10).Mutsetse wekutakura bhazi unofungidzirwa kuve neanotevera maitiro:

•  Mutsara wemutsetse
•  Hunhu impedance ye50 Ω
• Hunhu capacitance ye3.6 pF pa inch
•  Kureba kwe10 inches
• Iyo Intel Arria 10 IBIS modhi ndeyekutanga uye haiwanikwe paIntel IBIS modhi web peji. Kana iwe uchida aya ekutanga Intel Arria 10 IBIS modhi, bata Intel.
• Bhazi mutsauko hunhu impedance inosvika 100 Ω
•  Kupatsanura pakati pega yega transceiver ye1 inch
• Bhazi rakamiswa kumativi ese nekumisa resistor RT

• Default drive simba re12 mA
• Slow slaw rate settings by default
• Pin capacitance yega yega transceiver ye6 pF
•  Stub pane yega yega BLVDS transceiver ndeye 1-inch microstrip yehunhu impedance ye50 Ω uye hunhu hwekugona kwe3 pF pa inch.
•  Kugona kwekubatanidza (chibatanidza, pad, uye kuburikidza nePCB) yetransceiver yega yega kubhazi inofungidzirwa kuve 2 pF.
• Yese capacitance yemutoro wega wega inosvika gumi nerimwe pF

Kune 1-inch load spacing, iyo yakagoverwa capacitance yakaenzana ne11 pF pa inch. Kuderedza kufungisisa kunokonzerwa ne stubs, uye zvakare kuderedza zviratidzo zvinobuda
mutyairi, iyo impedance inoenderana ne50 Ω resistor RS inoiswa pane inobuda yega yega transceiver.

Kumiswa kweBhazi
Iyo impedance inoshanda yebhazi rakazara yakazara 52 Ω kana iwe ukatsiva iyo bhazi hunhu capacitance uye yakagoverwa capacitance pahurefu hweyuniti yekuseta mune inoshanda mutsauko impedance equation. Kuti uwane kutendeseka kwechiratidzo, unofanirwa kufananidza RT ne52 Ω. Nhamba dzinotevera dzinoratidza mhedzisiro yekufananidza-, pasi-, uye kudarika-kugumisa pane musiyano waveform (VID) pane inogamuchira pini yekupinza. Nhamba yedata ndeye 100 Mbps. Mune aya manhamba, pasi-kugumisa (RT = 25 Ω) inoguma nekufungidzira uye zvakanyanya kuderedzwa kweiyo ruzha margin. Mune zvimwe zviitiko, pasi pekugumiswa kunotyora chikumbaridzo chekugamuchira (VTH = ± 100 mV). Kana RT ichishandurwa kuita 50 Ω, pane ruzha rwakakura muganho neruremekedzo kuVTH uye ratidziro haina basa.

Mhedzisiro Yekumisa Bhazi (Mutyairi muU1, Receiver muU2)
Muchiverengero ichi, U1 inoita seanotapurirana uye U2 kuenda kuU10 ndivo vanogamuchira.

Mhedzisiro Yekumisa Bhazi (Mutyairi muU1, Receiver muU10)
Muchiverengero ichi, U1 inoita seanotapurirana uye U2 kuenda kuU10 ndivo vanogamuchira.

Mhedzisiro Yekumisa Bhazi (Mutyairi muU5, Receiver muU6)
Mumufananidzo uyu, U5 ndiyo inotumira uye vamwe vese vanogamuchira.

Mhedzisiro Yekumisa Bhazi (Mutyairi muU5, Receiver muU10)
Mumufananidzo uyu, U5 ndiyo inotumira uye vamwe vese vanogamuchira.Nzvimbo yehukama yemutyairi uye inogamuchira mubhazi inobatawo kugamuchirwa kwechiratidzo chemhando. Iye anogamuchira ari padyo kumutyairi anoona yakaipisisa yekufambisa mutsara mhedzisiro nekuti panzvimbo ino, mupendero wemupendero ndiwo unokurumidza. Izvi zvinotonyanya kuipa kana mutyairi ari pakati pebhazi.
For example, enzanisa Mufananidzo 16 uri papeji 20 neMufananidzo 18 uri papeji 21. VID painogamuchira U6 (mutyairi ari paU5) inoratidza kurira kwakakura kupfuura kuya kuringire U2 (mutyairi ari paU1). Kune rumwe rutivi, chiyero chemupendero chinoderedzwa pasi apo mugamuchiri ari kure kure nemutyairi. Nguva huru yekusimuka yakanyorwa ndeye 1.14 ns nemutyairi ari kune imwe mugumo webhazi (U1) uye anogamuchira kune imwe mugumo (U10).

Stub Length
Kureba kwenguva refu hakungowedzere nguva yekubhururuka kubva kumutyairi kuenda kune anogamuchira, asi zvakare inokonzeresa yakakura mutoro capacitance, izvo zvinokonzeresa kufungisisa kukuru.

Mhedzisiro yeKuwedzera Kureba kweStub (Mutyairi muU1, Receiver muU10)
Huwandu uhu hunoenzanisa VID paU10 apo hurefu hwe stub hunowedzerwa kubva painji imwe kusvika pamainji maviri uye mutyairi ari paU1.

Stub Termination
Iwe unofanirwa kuenzanisa mutyairi impedance kune stub hunhu impedance. Kuisa akatevedzana kumisa resistor RS pamutyairi anobuda kunoderedza zvakanyanya yakashata yekufambisa mutsara mhedzisiro inokonzerwa neakareba stub uye inokurumidza kumucheto mitengo. Mukuwedzera, RS inogona kuchinjwa kuti iite kuti VID isangane nezvinodiwa zveanogamuchira.

Mhedzisiro yeStub Kumisa (Mutyairi muU1, Receiver muU2 uye U10)
Huwandu uhu hunofananidza iyo VID paU2 neU10 apo U1 iri kufambisa.

Mutyairi Akauraya Mwero
Kukurumidza kuuraya mwero unobatsira kuvandudza nguva yekusimuka, kunyanya kune anogamuchira ari kure nemutyairi. Nekudaro, kukurumidza kuuraya mwero zvakare inokudza kurira nekuda kwekufungisisa.

Mhedzisiro yeDriver Edge Rate (Mutyairi muU1, Receiver muU2 uye U10)
Iyi nhamba inoratidza mutyairi akauraya mwero maitiro. Kuenzanisa kunoitwa pakati peyero inononoka uye inokurumidza kuuraya ine 12 mA drive simba. Mutyairi ari paU1 uye akasiyana mafungu eU2 uye U10 anoongororwa.

Yakazara System Performance

Nhamba yepamusoro yedata inotsigirwa nemultipoint BLVDS inotarirwa nekutarisa dhayagiramu yeziso reanogamuchira kure kwazvo kubva kumutyairi. Panzvimbo iyi, chiratidzo chinofambiswa chine chiyero chinononoka uye chinokanganisa kuvhura kweziso. Kunyangwe iyo mhando yechiratidzo chakagamuchirwa uye chinangwa cheruzha rwekumisikidza zvinoenderana nemashandisirwo, iyo yakakura kuvhura kweziso, zviri nani. Nekudaro, iwe unofanirwawo kutarisa mugamuchiri ari padyo nemutyairi, nekuti iyo yekutapurirana mitsara mhedzisiro inowanzoipa kana mugamuchiri ari padyo nemutyairi.
Mufananidzo 23. Diyagiramu Yeziso pa400 Mbps (Mutyairi muU1, Receiver muU2 uye U10)
Ichi chifananidzo chinoratidza dhayagiramu yeziso paU2 (red curve) uye U10 (blue curve) ye data rate pa400 Mbps. Random jitter ye1% unit interval inofungidzirwa mukuenzanisa. Mutyairi ari paU1 ane simba remazuva ano uye akauraya zvigadziriso. Bhazi rakazara ne optimum RT = 50 Ω. Diki kuvhura ziso riri paU10, iri kure kure neU1. Kureba kweziso sampinotungamirwa pa0.5 unit interval i692 mV uye 543 mV yeU2 neU10, zvichiteerana. Kune ruzha rwakakura rwemuganho maererano neVTH = ± 100 mV kune ese ari maviri kesi.

Gwaro Rekudzokorora Nhoroondo yeAN 522: Kuita Bhazi LVDS Interface muInotsigirwa Intel FPGA Chishandiso Mhuri.

Zvinyorwa / Zvishandiso

intel AN 522 Kuita Bhazi LVDS Interface mune Inotsigirwa FPGA Chishandiso Mhuri [pdf] Bhuku reMushandisi AN 522 Kumisikidza Bhazi LVDS Interface muInotsigirwa FPGA Chishandiso Mhuri, AN 522, Ichiita Bhazi LVDS Interface muInotsigirwa FPGA Chishandiso Mhuri, Interface muInotsigirwa FPGA Chishandiso Mhuri, FPGA Chishandiso Mhuri.

References

• User Manual