Intel Interlaken 2nd Gen FPGA IP Release Notes
Interlaken (2nd Generation) Intel® FPGA IP Release Notes
Ngati cholembera sichikupezeka pamtundu wina wa IP, IP core sichisintha mtunduwo. Kuti mumve zambiri zakusintha kwa IP kutulutsa mpaka v18.1, onani Intel Quartus Prime Design Suite Update Release Notes. Mitundu ya Intel® FPGA IP imafanana ndi mitundu ya Intel Quartus® Prime Design Suite mpaka v19.1. Kuyambira mu Intel Quartus Prime Design Suite software version 19.2, Intel FPGA IP ili ndi ndondomeko yatsopano yomasulira. Nambala ya Intel FPGA IP (XYZ) imatha kusintha ndi mtundu uliwonse wa pulogalamu ya Intel Quartus Prime. Kusintha kwa:
- X ikuwonetsa kukonzanso kwakukulu kwa IP. Mukasintha pulogalamu ya Intel Quartus Prime, muyenera kukonzanso IP.
- Y akuwonetsa kuti IP ili ndi zatsopano. Panganinso IP yanu kuti muphatikizepo zatsopanozi.
- Z ikuwonetsa kuti IP imaphatikizapo zosintha zazing'ono. Panganinso IP yanu kuti ikhale ndi zosinthazi.
- Intel Quartus Prime Design Suite Update Release Notes
- Interlaken (2nd Generation) Intel FPGA IP User Guide
- Errata for Interlaken (2nd Generation) Intel FPGA IP mu Knowledge Base
- Interlaken (2nd Generation) Intel Stratix 10 FPGA IP Design Exampndi User Guide
- Interlaken (2nd Generation) Intel Agilex FPGA IP Design Exampndi User Guide
- Chiyambi cha Intel FPGA IP Cores
Interlaken (2nd Generation) Intel FPGA IP v20.0.0
Gulu 1. v20.0.0 2020.10.05
| Intel Quartus Prime Version | Kufotokozera | Zotsatira |
|
20.3 |
Thandizo lowonjezera la data ya 25.78125 Gbps. | - |
| Adasintha ma data kuchokera ku 25.3 Gbps kupita ku 25.28 Gbps ndi 25.8 Gbps kupita ku 25.78125 Gbps. |
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Malingaliro a kampani Intel Corporation Maumwini onse ndi otetezedwa. Intel, logo ya Intel, ndi zizindikiro zina za Intel ndi zizindikiro za Intel Corporation kapena mabungwe ake. Intel imatsimikizira kugwira ntchito kwa FPGA yake ndi zida za semiconductor malinga ndi zomwe zili pano malinga ndi chitsimikizo cha Intel, koma ili ndi ufulu wosintha zinthu ndi ntchito zilizonse nthawi iliyonse popanda kuzindikira. Intel sakhala ndi udindo kapena udindo chifukwa chakugwiritsa ntchito kapena kugwiritsa ntchito zidziwitso zilizonse, malonda, kapena ntchito zomwe zafotokozedwa pano kupatula monga momwe Intel adavomerezera momveka bwino. Makasitomala a Intel amalangizidwa kuti apeze mtundu waposachedwa kwambiri wamakina a chipangizocho asanadalire zidziwitso zilizonse zosindikizidwa komanso asanayike maoda azinthu kapena ntchito.
Mayina ena ndi mtundu zitha kunenedwa kuti ndi za ena.
Interlaken (2nd Generation) Intel FPGA IP v19.3.0
Gulu 2. v19.3.0 2020.06.22
| Intel Quartus Prime Version | Kufotokozera | Zotsatira |
|
19.3.0 |
IP tsopano imathandizira mawonekedwe a Interlaken Look-aside. | - |
| Wowonjezera watsopano Yambitsani mawonekedwe a Interlaken Look-aside parameter mu IP parameter editor. | Mutha kusintha IP munjira ya Interlaken Look-aside. | |
| Kusamutsa mode parameter imachotsedwa pamtundu waposachedwa wa Intel Quartus Prime software. |
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| Kuwonjezedwa kwa 12.5 Gbps mlingo wa data pa chiwerengero cha misewu 10 mu H- tile ndi E-tile (NRZ mode) kusiyana kwakukulu kwa IP. |
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| Yachotsa zizindikiro zotsatirazi pa IP:
• rx_pma_data • tx_pma_data • ine_njala • ine_njala |
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| Onjezani zizindikiro zatsopano zotsatirazi:
• sop_cntr_inc1 • eop_cntr_inc1 • rx_xcoder_uncor_feccw • itx_ch0_xon • irx_ch0_xon • itx_ch1_xon • irx_ch1_xon • itx_valid • irx_valid • itx_idle • irx_idle • itx_ctrl • itx_credit • irx_credit |
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| Zachotsedwa pazotsatira ziwiri pamapu olembetsa:
• 16'h40- TX_READY_XCVR • 16'h41- RX_READY_XCVR |
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| Kuyesa kwa Hardware kwa kapangidwe kakaleample tsopano ikupezeka pazida za Intel Agilex™. | Mutha kuyesa zojambula zakaleample pa Intel Agilex F-mndandanda wa Transceiver-SoC Development Kit. | |
| Mutha kusintha kuchuluka kwa data ndi ma frequency a wotchi ya transceiver kukhala yosiyana pang'ono pamwambo wanu wa Interlaken (2nd Generation) IP womwe umalunjika pa chipangizo cha Intel Stratix® 10 H-tile kapena E-tile. Onani ku KDB iyi kuti mudziwe zambiri zamomwe mungasinthire kuchuluka kwa data. |
Mutha kusintha mitengo ya data kutengera matailosi. |
Interlaken (2nd Generation) Intel FPGA IP v19.2.1
Gulu 3. v19.2.1 2019.09.27
| Intel Quartus Prime Version | Kufotokozera | Zotsatira |
|
19.3 |
Kutulutsidwa kwapagulu kwa zida za Intel Agilex zokhala ndi ma transceivers a E-tile. | - |
| Adasinthidwanso Interlaken (2nd Generation) Intel Stratix 10 FPGA IP kupita ku Interlaken (2nd Generation) Intel FPGA IP |
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Interlaken (2nd Generation) Intel Stratix 10 FPGA IP v18.1 Kusintha 1
Gulu 4. Mtundu wa 18.1 Kusintha 1 2019.03.15
| Kufotokozera | Zotsatira |
| Thandizo lowonjezera la magawo ambiri. | - |
| Zowonjezedwa Chiwerengero cha Magawo parameter. | - |
| Thandizo lowonjezera la kanjira ndi kuphatikizika kwa ma data motere:
- Pazida za Intel Stratix 10 L-tile: • Misewu 4 yokhala ndi mayendedwe a 12.5/25.3/25.8 Gbps • Misewu ya 8 yokhala ndi mitengo ya 12.5 Gbps - Pazida za Intel Stratix 10 H-tile: • Misewu 4 yokhala ndi mayendedwe a 12.5/25.3/25.8 Gbps • Misewu 8 yokhala ndi mayendedwe a 12.5/25.3/25.8 Gbps • Misewu ya 10 yokhala ndi mitengo ya 25.3 / 25.8 Gbps - Pazida za Intel Stratix 10 E-tile (NRZ): • Misewu 4 yokhala ndi 6.25/12.5/25.3/25.8 Gbps mizere • Misewu 8 yokhala ndi mayendedwe a 12.5/25.3/25.8 Gbps • Misewu ya 10 yokhala ndi mitengo ya 25.3 / 25.8 Gbps • Misewu ya 12 yokhala ndi mtunda wa 10.3125 Gbps |
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| • Anawonjeza zizindikiro zotsatirazi:
— izo_eob1 -itx_eopbits1 -itx_chan1 |
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| • Anawonjeza zizindikiro zotsatirazi za wolandila:
— irx_eob1 - irx_eopbits1 — irx_chan1 — irx_err1 - irx_err |
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Interlaken (2nd Generation) Intel Stratix 10 FPGA IP v18.1
Gulu 5. Mtundu 18.1 2018.09.10
| Kufotokozera | Zotsatira | Zolemba |
| Adatcha dzina lachikalata ngati Interlaken (2nd Generation) Intel Stratix 10 FPGA IP User Guide |
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| Chowonjezera choyerekeza cha VHDL ndi chithandizo cha testbench cha Interlaken (2nd Generation) IP core. |
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| Onjezani zolembetsa zatsopano ku IP core: | ||
| • TX_READY_XCVR | ||
| • RX_READY_XCVR
• ILKN_FEC_XCODER_TX_ILLEGAL_ STATE |
- | Zolembera izi zimangopezeka mumitundu yazida za Intel Stratix 10 E-Tile. |
| • ILKN_FEC_XCODER_RX_ILLEGAL_ STATE |
Interlaken (2nd Generation) Intel FPGA IP v18.0.1
Gulu 6. Mtundu wa 18.0.1 July 2018
| Kufotokozera | Zotsatira | Zolemba |
| Thandizo lowonjezera la zida za Intel Stratix 10 zokhala ndi ma transceivers a E-Tile. |
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| Adawonjezera 53.125 Gbps data rate rate pazida za Intel Stratix 10 E-Tile mu PAM4 mode. |
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| Wowonjezera wotchi mac_clkin pazida za Intel Stratix 10 E-Tile mu PAM4 mode |
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Interlaken (2nd Generation) Intel FPGA IP v18.0
Gulu 7. Mtundu wa 18.0 May 2018
| Kufotokozera | Zotsatira | Zolemba |
| Adatchedwanso Interlaken IP core (2nd Generation) kukhala Interlaken (2nd Generation) Intel FPGA IP monga momwe Intel idasinthira. |
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| Thandizo la 25.8 Gbps pa chiwerengero cha misewu 6 ndi 12. |
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| Thandizo lowonjezera la Cadence Xcelium * Parallel simulator. |
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Interlaken IP Core (2nd Generation) v17.1
Table 8. Version 17.1 November 2017
| Kufotokozera | Zotsatira | Zolemba |
| Kutulutsidwa koyamba mu Intel FPGA IP Library. | - | - |
Zambiri Zogwirizana
Interlaken IP Core (2nd Generation) User Guide
Interlaken (2nd Generation) Intel FPGA IP User Guide Archives
| Mtundu wa Quartus | IP Core Version | Wogwiritsa Ntchito |
| 20.2 | 19.3.0 | Interlaken (2nd Generation) FPGA IP User Guide |
| 19.3 | 19.2.1 | Interlaken (2nd Generation) FPGA IP User Guide |
| 19.2 | 19.2 | Interlaken (2nd Generation) FPGA IP User Guide |
| 18.1.1 | 18.1.1 | Interlaken (2nd Generation) Intel Stratix 10 FPGA IP User Guide |
| 18.1 | 18.1 | Interlaken (2nd Generation) Intel Stratix 10 FPGA IP User Guide |
| 18.0.1 | 18.0.1 | Interlaken (2nd Generation) FPGA IP User Guide |
| 18.0 | 18.0 | Interlaken (2nd Generation) Intel FPGA IP User Guide |
| 17.1 | 17.1 | Interlaken IP Core (2nd Generation) User Guide |
Mitundu ya IP ndi yofanana ndi mitundu ya Intel Quartus Prime Design Suite mpaka v19.1. Kuchokera ku Intel Quartus Prime Design Suite software version 19.2 kapena mtsogolo, ma IP cores ali ndi dongosolo latsopano la IP. Ngati mtundu wa IP core sunatchulidwe, chiwongolero cha ogwiritsa ntchito pamtundu wakale wa IP akugwira ntchito.
Zolemba / Zothandizira
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Intel Interlaken 2nd Gen FPGA IP Release Notes [pdf] Malangizo Interlaken 2nd Gen FPGA IP Release Notes, Interlaken 2nd Gen, FPGA IP Release Notes |
