Imixholo fihla
1 Intel 750856 Ibhodi yoPhuhliso lwe-Agilex FPGA
2 Ulwazi lweMveliso
3 Imiyalelo yokusetyenziswa kwemveliso
4 Uyilo lweReferensi ngaphezuluview
5 Uqwalaselo lomamkeli wangaphandle
6 IiMfuno zoYilo lweReferensi
7 I-Reference Design Walkthrough
8 Ukudala iSahlulo soYilo
9 Ukudala uHlaziyo
10 Amagama ohlaziyo kunye neentlobo
11 Ukucwangcisa i-Intel Agilex F-Series FPGA Development Board Hardware Testing Flow
12 Amaxwebhu / Izibonelelo
12.1 Iimbekiselo

intel-LOGO

Intel 750856 Ibhodi yoPhuhliso lwe-Agilex FPGA

intel-750856-Agilex-FPGA-Development-Board-PRODUCT

Ulwazi lweMveliso

Olu yilo lwereferensi lweBhodi yoPhuhliso lwe-Intel Agilex F-Series FPGA. Isebenzisa uMlawuli woLungiselelo lwaNgaphandle lokuLungiselela i-Intel FPGA IP kwaye unommandla we-PR olula. Isixhobo se-Intel Agilex Isixhobo sangaphandle se-Hardware se-Hardware Setup siqulathe isixhobo sangaphandle (Umncedisi weFPGA), i-DUT FPGA, kunye noyilo lwakho lwangaphandle lomkhosi. Uyilo lomkhosi kwisixhobo sangaphandle sinoxanduva lokusingatha inkqubo yePR. Izikhonkwane zePR zisetyenziselwa ukudibanisa zombini izixhobo kwaye zinokuba nawuphi na umsebenzisi okhoyo we-I / Os.

Imiyalelo yokusetyenziswa kwemveliso

Uqwalaselo lomamkeli wangaphandle

Ukwenza uqwalaselo lomamkeli wangaphandle, landela la manyathelo:

  1. Yenza uyilo lwenginginya kwisixhobo sangaphandle ukusingatha inkqubo yePR.
  2. Qhagamshela izikhonkwane ze-PR ukusuka kwisixhobo sangaphandle ukuya kuLungiselelo lweNxalenye yoLungiselelo lwaNgaphandle koMlawuli we-Intel FPGA IP kwi-DUT FPGA.
  3. Ukusasaza idatha yokucwangcisa ukusuka kwi-design host ukuya kwi-Intel Agilex Avalon ye-interface ye-interface pins ehambelana neempawu ze-PR zokubamba ngesandla ezivela kwi-IP.

Uqwalaselo ngokutsha oluyinxenye ngokuSebenza kwezikhonkwane zoLungiselelo

Olu landelelwano lulandelayo luchaza ukusebenza koqwalaselo ngokutsha olungaphelelanga ngezikhonkwane zoqwalaselo:

  1. Cela i-pr_request yephini eqhagamshelwe kuLungiselelo Olungaphelelanga loLawulo loLungiselelo lwaNgaphandle lwe-Intel FPGA IP.
  2. I-IP ibeka uphawu oluxakekileyo ukubonisa ukuba inkqubo ye-PR iyaqhubeka (ukhetho).
  3. Ukuba inkqubo yoqwalaselo ilungele ukusebenza kwe-PR, i-avst_ready pin iqinisekisiwe, ebonisa ukuba ilungele ukwamkela idatha.
  4. Ukusasaza idatha yoqwalaselo lwe-PR phezu kwe-avst_data pins kunye ne-avst_valid pin, ngokulandela i-Avalon yokusasazwa kwenkcazo yokudluliselwa kwedatha ngoxinzelelo lwangasemva.
  5. Umsinga uyayeka xa i-avst_ready pin ingafunwa.
  6. De-assert i-avst_ready pin ukubonisa ukuba akukho datha ifunekayo kumsebenzi wePR.
  7. Uqwalaselo Olungagqibelelanga Loqwalaselo lwaNgaphandle UMlawuli we-Intel FPGA IP ukhupha umqondiso oxakekileyo ukubonisa isiphelo senkqubo (ukhetho).

Uqwalaselo ngokutsha oluyinxenye ngokusebenzisa izikhonkwane zoLungiselelo (umamkeli wangaphandle) uyilo lweReferensi

Eli nqaku lesicelo libonisa uhlengahlengiso oluyinxenye ngokusebenzisa izikhonkwane zoqwalaselo (umamkeli wangaphandle) kwibhodi yophuhliso ye-Intel® Agilex® F-Series FPGA.

Uyilo lweReferensi ngaphezuluview

Uqwalaselo ngokutsha olungaphelelanga (PR) uphawu likuvumela ukuba uqwalasele kwakhona inxalenye yeFPGA ngamandla, ngelixa uyilo olushiyekileyo lweFPGA luqhubeka nokusebenza. Unokwenza abantu abaninzi bommandla othile kuyilo lwakho olungachaphazeliyo ukusebenza kwiindawo ezingaphandle kwalo mmandla. Le ndlela yokusebenza iyasebenza kwiinkqubo apho imisebenzi emininzi ngexesha-yabelana ngezixhobo ezifanayo zesixhobo seFPGA. Uguqulelo lwangoku lwesoftware ye-Intel Quartus® Prime Pro Edition yazisa ukuqukuqela okutsha nokwenziwa lula kohlengahlengiso oluyinxenye. Olu yilo lwesalathiso lwe-Intel Agilex lusebenzisa uLawulo lweNdlela yoBulungisa obuNgaphandle lwe-Intel FPGA IP kwaye inommandla we-PR olula.

Isixhobo se-Intel Agilex sokuSeta i-Hardware ye-Host yangaphandlei-intel-750856-Agilex-FPGA-iBhodi yoPhuhliso-FIG-1 (1)

Uqwalaselo lomamkeli wangaphandle

Kuqwalaselo lomkhosi wangaphandle, kufuneka uqale udale uyilo lomkhosi kwisixhobo sangaphandle ukubamba inkqubo yePR, njengoko i-Intel Agilex Isixhobo sangaphandle se-Host Hardware Setup ibonisa. I-design host ihambisa idatha yoqwalaselo kwi-Intel Agilex Avalon ye-interface ye-interface pins ehambelana neempawu ze-PR zokubamba ngesandla ezivela kwi-Paternal Reconfiguration Controller External Configuration Controller Intel FPGA IP. Izikhonkwane zePR ozisebenzisayo ukuqhagamshela izixhobo zombini zinokuba nawuphi na umsebenzisi okhoyo we-I/Os.

Olu landelelwano lulandelayo luchaza uqwalaselo ngokutsha olungaphelelanga ngokusebenzisa izikhonkwane zoqwalaselo:

  1. Okokuqala faka i-pr_request yephini eqhagamshelwe kuLungiselelo oluNgaphandle loLawulo loLungiselelo lwaNgaphandle lwe-Intel FPGA IP.
  2. I-IP ibeka uphawu oluxakekileyo ukubonisa ukuba inkqubo ye-PR iyaqhubeka (ukhetho).
  3. Ukuba inkqubo yoqwalaselo ikulungele ukwenza umsebenzi wePR, i-avst_ready pin iqinisekisiwe ebonisa ukuba ikulungele ukwamkela idatha.
  4. Qalisa ukusasaza idatha yoqwalaselo lwe-PR ngaphezulu kwe-avst_data pins kunye ne-avst_valid pin, ngelixa uqwalasela i-Avalon yostrimisho lwenkcazo yokudluliselwa kwedatha ngoxinzelelo lwangasemva.
  5. Umsinga uyayeka nanini na xa i-avst_ready pin ingafunwa.
  6. Emva kokusasaza yonke idatha yoqwalaselo, i-avst_ready pin ayiqinisekiswanga ukubonisa ukuba akukho datha ifunekayo ekusebenzeni kwePR.
  7. Uqwalaselo Olungagqibelelanga Loqwalaselo Lwangaphandle UMlawuli we-Intel FPGA IP desserts umqondiso oxakekileyo ukubonisa isiphelo senkqubo (ukhetho).
  8. Ungajonga i-pr_done kunye ne-pr_error pins ukuze uqinisekise ukuba umsebenzi wePR ugqitywe ngempumelelo. Ukuba kukho imposiso, njengokungaphumeleli kuqwalaselo loguqulelo kunye noqwalaselo logunyaziso, umsebenzi wePR uyayekiswa.

Ulwazi olunxulumeneyo

  • Intel Agilex F-Series FPGA Development Kit Web Iphepha
  • Intel Agilex F-Series FPGA Development Kit Isikhokelo somsebenzisi
  • Intel Quartus Prime Pro Edition Isikhokelo somsebenzisi: Uhlengahlengiso oluyinxenye

Uqwalaselo ngokutsha oluyinxenye Umlawuli wobumbeko lwangaphandle Intel FPGA IP
ULungiselelo Olungaphelelanga loLawulo lokuLungiselela lwaNgaphandle lufuneka ukuba lusebenzise izikhonkwane zoqwalaselo ukusasaza idatha yePR yokusebenza kwePR. Kufuneka uqhagamshele onke amazibuko omgangatho ophezulu woqwalaselo ngokutsha oluyinxenye Isilawuli soqwalaselo lwangaphandle Intel FPGA IP ukuya kwi-pr_request pin ukuvumela ukuxhawulana kwenginginya kunye nomphathi wesixhobo esikhuselekileyo (SDM) ukusuka embindini. I-SDM imisela ukuba zeziphi iintlobo zezikhonkwane zoqwalaselo eziza kusetyenziswa, ngokuhambelana nelungiselelo lakho le-MSEL.

Uqwalaselo ngokutsha oluyinxenye Umlawuli wobumbeko lwangaphandle Intel FPGA IPi-intel-750856-Agilex-FPGA-iBhodi yoPhuhliso-FIG-1 (2)

Uhlengahlengiso Olungagqibelelanga loLungiselelo lwaNgaphandle Useto lweParameter

Ipharamitha Ixabiso Inkcazo
Vulela iBusy Interface Vulela or

Khubaza

 Ikuvumela ukuba wenze okanye uKhubaze ujongano oluxakekileyo, olubanga uphawu lokubonisa ukuba inkqubo yePR iyaqhubeka ngexesha loqwalaselo lwangaphandle.

Useto oluhlala lukhona lu Khubaza.

Ulungelelwaniso ngokutsha lweZibuko zoLawulo lwaNgaphandle

Igama lePort Ububanzi Isalathiso Umsebenzi
pr_sicelo 1 Igalelo Ibonisa ukuba inkqubo yePR ikulungele ukuqalisa. Isignali yiconduit engangqamanisi kuyo nayiphi na isignali yewotshi.
pr_impazamo 2 Isiphumo Ibonisa impazamo yoqwalaselo ngokutsha.

• 2'b01—impazamo yePR ngokubanzi

• 2'b11—impazamo ye-bitstream engahambelaniyo

Le miqondiso ziiconduits ezingangqamanisi kuwo nawuphi na umthombo wewotshi.
pr_kwenziwe 1 Isiphumo Ibonisa ukuba inkqubo yePR igqityiwe. Isignali yiconduit engangqamanisi kuyo nayiphi na isignali yewotshi.
qala_yongeza 1 Igalelo Ixela idilesi yokuqala yedatha yePR kwiFlash eSebenzayo yothotho. Unika olu phawu ngokukhetha nokuba kukuphi Avalon®-ST or Uthotho olusebenzayo ukwenzela i Yenza izikhonkwane ze-Avalon-ST okanye izikhonkwane zeSeriya ezisebenzayo ipharamitha. Isignali yiconduit engangqamanisi kuyo nayiphi na isignali yewotshi.
seta kwakhona 1 Igalelo Isiginali yokusetha ngokutsha esebenzayo ephezulu, ehambelanayo.
phandle_clk 1 Isiphumo Umthombo wewotshi ovelisa kwi-oscillator yangaphakathi.
ndixakekile 1 Isiphumo I-IP iqinisekisa lo mqondiso ukubonisa ugqithiso lwedatha ye-PR oluqhubekayo. Unika olu phawu ngokukhetha Vulela ukwenzela i Vula ujongano oluxakekileyo ipharamitha.

IiMfuno zoYilo lweReferensi

Ukusetyenziswa kolu yilo lwereferensi kufuna oku kulandelayo:

  • Ukufakwa kwe-Intel Quartus Prime Pro Edition version 22.3 ngenkxaso yosapho lwesixhobo se-Intel Agilex.
  • Uqhagamshelo kwibhodi yophuhliso lwe-Intel Agilex F-Series FPGA kwibhentshi.
  • Ukhuphelo loyilo exampiyafumaneka kule ndawo ilandelayo: https://github.com/intel/fpga-partial-reconfig.

Ukukhuphela uyilo example:

  1. Cofa i-Clone okanye ukhuphele.
  2. Cofa Khuphela ZIP. Vula i-fpga-partial-reconfig-master.zip file.
  3. Yiya kwii-tutorials/agilex_external_pr_configuration isiqulathi seefayili ukufikelela kuyilo lwereferensi.

I-Reference Design Walkthrough

La manyathelo alandelayo achaza ukuphunyezwa kohlengahlengiso oluyinxenye ngokusebenzisa izikhonkwane zoqwalaselo (umamkeli wangaphandle) kwibhodi yophuhliso ye-Intel Agilex F-Series FPGA:

  • Inyathelo loku-1: Ndiyaqalisa
  • Inyathelo loku-2: Ukudala iSahlulo soYilo
  • Inyathelo loku-3: Ukwabiwa kweMimandla yokuBeka kunye neNdlela
  • Inyathelo loku-4: Ukongeza i-IP yoLawulo lokuLungiselela iNdawo yaNgaphandle
  • Inyathelo loku-5: Ukuchaza Abantu
  • Inyathelo loku-6: Ukudala uHlaziyo
  • Inyathelo loku-7: Ukuqulunqa uHlaziyo lweSiseko
  • Inyathelo loku-8: Ukulungiselela uHlaziyo lokuPhunyezwa kwePR
  • Inyathelo loku-9: Ukucwangcisa iBhodi

Inyathelo 1: Ukuqalisa
Ukukopa uyilo lwereferensi files kwindawo yakho yokusebenza kwaye uqokelele uyilo lweflethi blinking_led:

  1. Yenza uvimba weefayili kwindawo yakho yokusebenza, agilex_pcie_devkit_blinking_led_pr.
  2. Khuphela izifundo ezikhutshelweyo/agilex_pcie_devkit_blinking_led/flat sub-folder kulawulo, agilex_pcie_devkit_blinking_led_pr.
  3. Kwisoftware ye-Intel Quartus Prime Pro Edition, cofa File ➤ Vula iProjekthi kwaye ukhethe blinking_led.qpf.
  4. Ukucacisa uluhlu lwemigangatho yoyilo olusicaba, cofa uKusetyenzwa ➤ Qala ➤ Qala uHlahlelo & neNdibanisela. Kungenjalo, kumgca womyalelo, sebenzisa lo myalelo ulandelayo: quartus_syn blinking_led -c blinking_led

Ukudala iSahlulo soYilo

Kuya kufuneka udale izahlulo zoyilo kwindawo nganye yePR ofuna ukuyiqwalasela kwakhona ngokuyinxenye. La manyathelo alandelayo enza isahlulelo soyilo lomzekelo u_blinking_led.

Ukudala izahlulo zoYiloi-intel-750856-Agilex-FPGA-iBhodi yoPhuhliso-FIG-1 (3)

  1. Cofa ekunene kumzekelo u_blinking_led kwiNavigator yeProjekthi kwaye ucofe iSahlulo soYilo ➤ Inokuphinda iqwalaselwe. I-icon yesahlulelo soyilo siyavela ecaleni kwendlela nganye esetwe njengesahlulelo.
  2. Cofa izabelo ➤ Ifestile yezahlulo zoyilo. Ifestile ibonisa zonke izahlulelo zoyilo kwiprojekthi.
  3. Hlela igama lesahlulelo kwifestile yezahlulo zoYilo ngokucofa kabini igama. Kolu yilo lwereferensi, yithiya ngokutsha igama lesahlulelo kwi-pr_partition
    • Phawula: Xa udala ulwahlulo, isoftware ye-Intel Quartus Prime ivelisa ngokuzenzekelayo igama lokwahlula, ngokusekwe kwigama lomzekelo kunye nendlela yolawulo. Eli gama lesahlulelo sinokwahluka ngokomzekelo ngamnye.
  4. Ukuthumela ngaphandle ummandla ongatshintshiyo ogqityiweyo ukusuka kwisiseko sohlaziyo, cofa kabini ungene kwingcambu_ yokwahlula kwiPosi yokuThumela ngaphandle File ikholamu, kwaye uchwetheze blinking_led_static. gdb.

Ukuthunyelwa ngaphandle kweSifinyezo sokuGqibela kwiVenkile yezahlulo zoYiloi-intel-750856-Agilex-FPGA-iBhodi yoPhuhliso-FIG-1 (4)Qinisekisa ukuba i blinking_led.qsf iqulathe izabelo ezilandelayo, ezihambelana nesahlulelo sakho soyilo oluphinda luqwalaselwe:i-intel-750856-Agilex-FPGA-iBhodi yoPhuhliso-FIG-1 (5)

Ulwazi olunxulumeneyo
"Yenza iZahlulo zoYilo" kwi-Intel Quartus Prime Pro Edition IsiKhokelo soMsebenzisi: Uhlengahlengiso oluyinxenye

Ukwabiwa kweNdawo yokuBeka kunye neNdlela yoMmandla kwiSahlulo sePR
Kulo lonke uhlaziyo olusisiseko olwenzileyo, ukuhamba koyilo lwePR kubeka undoqo wobuntu ohambelanayo kwingingqi yakho ye-PR. Ukufumana kunye nokwabela ummandla we-PR kwiplani yomgangatho wesixhobo sohlaziyo lwakho olusisiseko:

  1. Cofa ekunene kumzekelo u_blinking_led kwiProjekthi yeNavigator kwaye ucofe iNgingqi yokutshixa iNgcaciso ➤ Yila iNgingqi eNtsha yokutshixa iNgcaciso. Ummandla uvela kwi-Logic Lock Regions Window.
  2. Indawo yakho mayivale i-blinking_led logic. Khetha ummandla wokubekwa ngokufumana indawo yokudibanisa kwiChip Planner. Cofa ekunene igama lengingqi u_blinking_led kwiLogic Lock Regions Window kwaye ucofe

Fumana iNdawo yoMmandla ➤ Fumana kwiChip Planner. Indawo u_blinking_led inekhowudi yombala

Indawo Yendawo Yokucwangcisa iChip yokublinking_ledi-intel-750856-Agilex-FPGA-iBhodi yoPhuhliso-FIG-1 (6)

  1. Kwi-Logic yeNgingqi yeNgingqi yefestile, khankanya ulungelelwaniso lommandla wokubekwa kwi Imvelaphi ikholamu. Imvelaphi ihambelana nekona esezantsi ekhohlo yommandla. Umzekeloample, ukuseta ummandla wobeko nge (X1 Y1) ulungelelwaniso njenge (163 4), khankanya iMvelaphi njenge X163_Y4. I-Intel Quartus Prime isoftwe ibala ngokuzenzekelayo i (X2 Y2) ulungelelwaniso (phezulu-ekunene) kwindawo yokubeka, ngokusekelwe kubude kunye nobubanzi obalulayo.
    • Phawula: Esi sifundo sisebenzisa (X1 Y1) ulungelelwaniso - (163 4), kunye nobude kunye nobubanzi be-20 yendawo yokubeka. Chaza naliphi na ixabiso lendawo yokubeka. Qinisekisa ukuba ummandla ugubungela i-blinking_led logic.
  2. Yenza iinketho ezigciniweyo kunye nezingundoqo kuphela.
  3. Cofa kabini kwiNgingqi yokuJonga. Ibhokisi yencoko yababini yebhokisi yencoko yababini yokuTshixa indlela yokuHambisa iyavela.
  4. Khetha Fixed nolwandiso lohlobo loNdlela. Ukukhetha olu khetho ngokuzenzekelayo kwabela ubude bolwandiso lwe-2.
    • Phawula: Ummandla womzila kufuneka ube mkhulu kunommandla obekwe kuwo, ukunika uguqulo olongezelelweyo lweFitter xa injini ihambisa abantu abohlukeneyo.

Ifestile yeNgingqi yokutshixa yeeNgingqii-intel-750856-Agilex-FPGA-iBhodi yoPhuhliso-FIG-1 (7)Qinisekisa ukuba i blinking_led.qsf iqulathe izabelo ezilandelayo, ezihambelana neplani yomgangatho wakho:i-intel-750856-Agilex-FPGA-iBhodi yoPhuhliso-FIG-1 (8)i-intel-750856-Agilex-FPGA-iBhodi yoPhuhliso-FIG-1 (9)

Ulwazi olunxulumeneyo
"Floorplan uYilo lokuLungiselela iNxalenye" ​​kwi-Intel Quartus Prime Pro Edition IsiKhokelo somsebenzisi: Uhlengahlengiso oluyinxenye

Ukongeza iNgxelo yoLungiselelo lwaNgaphandle koLawulo loLungiso lwe-Intel FPGA IP
Uqwalaselo Oluyinxenye Lolawulo lwangaphandle lwe-Intel FPGA IP interfaces kunye ne-Intel Agilex PR ibhloko yokulawula ukulawula umthombo we-bitstream. Kuya kufuneka wongeze le IP kuyilo lwakho ukuphumeza uqwalaselo lwangaphandle. Landela la manyathelo ukongeza iNdlela yoBulungisa obungaphelelanga boLawulo loBumbeko lwaNgaphandle
Intel FPGA IP kwiprojekthi yakho:

  1. Chwetheza Uhlengahlengiso Olungaphelelanga kwindawo yokukhangela kwiKhathalogi ye-IP (Izixhobo ➤ Ikhathalogu ye-IP).
  2. Cofa kabini Uqwalaselo ngokutsha Loqwalaselo lwaNgaphandle Umlawuli we-Intel FPGA IP.
  3. Kwi-Yenza i-IP yebhokisi yencoko yababini, chwetheza external_host_pr_ip njenge File igama, kwaye emva koko ucofe Yenza. Umhleli weparameter uyavela.
  4. Kwi Yenza ipharamitha yojongano oluxakekileyo, khetha Khubaza (ulungiselelo olungagqibekanga). Xa ufuna ukusebenzisa lo mqondiso, ungatshintsha useto uye kuVumela.

Nika amandla iParameter yeNdibaniselwano eBusy kuMhleli weParameteri-intel-750856-Agilex-FPGA-iBhodi yoPhuhliso-FIG-1 (10)

  1. Cofa File ➤ Gcina kwaye uphume kumhleli weparameter ngaphandle kokuvelisa inkqubo. Umhleli weparameter wenza i-IP yangaphandle_host_pr_ip.ip ukwahluka file kwaye yongeza i file kwiprojekthi ekhokelweyo_eqhwanyazayo. AN 991: Ulungelelwaniso ngokutsha oluyinxenye ngokusebenzisa izikhonkwane zoLungiselelo (Inginginya yaNgaphandle) iReference Design 750856 | 2022.11.14 AN 991:
    • Phawula:
    • a. Ukuba ukhuphela i external_host_pr_ip.ip file ukusuka kulawulo lwe-pr, hlela ngesandla i blinking_led.qsf file ukubandakanya lo mgca ulandelayo: set_global_assignment -igama IP_FILE pr_ip.ip
    • b. Beka i-IP_FILE Isabelo emva kweSDC_FILE izabelo (blinking_led. dc) kweyakho blinking_led.qsf file. Olu cwangco luqinisekisa uthintelo olufanelekileyo lweNqanaba yoLawulo lokuLungiselela kwakhona i-IP engundoqo.
    • Phawula: Ukubona iiwotshi, i.sdc file ye PR IP kufuneka ilandele nayiphi na .sdc eyenza iiwotshi ezisetyenziswa ngundoqo we IP. Uququzelela lo myalelo ngokuqinisekisa ukuba i-.ip file kuba i-PR IP core ibonakala emva kwayo nayiphi na i-.ip files okanye .sdc fileozisebenzisayo ukuchaza ezi wotshi kwi .qsf file kuhlaziyo lweprojekthi yakho ye-Intel Quartus Prime. Ngolwazi oluthe kratya, jonga kwiSikhokelo soMsebenzisi weSisombululo se-IP esingaphelelanga.

Ukuhlaziya uyilo olukwiNqanaba eliphezulu

Ukuhlaziya i-top.sv file ngomzekelo we PR_IP:

  1. Ukongeza_external_host_pr_ip umzekelo kuyilo lomgangatho ophezulu, sucomment le code blocks ilandelayo kwi top.sv file:i-intel-750856-Agilex-FPGA-iBhodi yoPhuhliso-FIG-1 (11)

Ukuchaza Abantu
Olu yilo lwereferensi luchaza abantu abathathu abahlukeneyo kwisahlulelo esinye sePR. Ukuchaza kunye nokubandakanya abantu kwiprojekthi yakho:

  1. Yenza ezintathu SystemVerilog files, blinking_led.sv, blinking_led_slow.sv, kunye blinking_led_empty.sv kwincwadi yakho yokusebenza yabantu abathathu.

Reference Design Personasi-intel-750856-Agilex-FPGA-iBhodi yoPhuhliso-FIG-1 (12) i-intel-750856-Agilex-FPGA-iBhodi yoPhuhliso-FIG-1 (13)

Phawula:

  • blinking_led.sv sele ikhona njengenxalenye ye files ukhuphela kwiflethi/ uvimba weefayili onganeno. Ungaphinda usebenzise oku file.
  • Ukuba wenza iSystemVerilog files ukusuka kwi-Intel Quartus Prime Text Editor, khubaza ukongeza file kukhetho lweprojekthi yangoku, xa ugcina i files.

Ukudala uHlaziyo

Ukuhamba koyilo lwePR kusebenzisa inqaku lohlaziyo lweprojekthi kwi-Intel Quartus Prime software. Uyilo lwakho lokuqala luhlengahlengiso olusisiseko, apho uchaza imida yengingqi emileyo kunye nemimandla enokuphinda iqwalaselwe kwiFPGA. Ukusuka kwisiseko sohlaziyo, udala uhlaziyo oluninzi. Olu hlaziyo luqulathe umiliselo olwahlukeneyo lwemimandla ye-PR. Nangona kunjalo, lonke uhlaziyo lokuphunyezwa kwePR lusebenzisa ukubekwa kwinqanaba eliphezulu kunye neziphumo zomzila ukusuka kwisiseko sohlaziyo. Ukuqulunqa uyilo lwePR, kufuneka wenze uhlaziyo lokuphunyezwa kwePR kumntu ngamnye. Ukongeza, kufuneka unike iindidi zohlaziyo kuhlaziyo ngalunye. Iindidi zohlaziyo ezikhoyo zezi:

  • Uhlengahlengiso oluyinxenye – Isiseko
  • Uhlengahlengiso oluyinxenye – ukuPhunyezwa koMntu

Le theyibhile ilandelayo idwelisa igama lohlaziyo kunye nodidi lohlaziyo kuhlaziyo ngalunye:

Amagama ohlaziyo kunye neentlobo

Igama lohlaziyo Uhlobo lohlaziyo
blinking_led.qsf Uhlengahlengiso oluyinxenye – Isiseko
blinking_led_default.qsf Uhlengahlengiso oluyinxenye – ukuPhunyezwa koMntu
blinking_led_slow.qsf Uhlengahlengiso oluyinxenye – ukuPhunyezwa koMntu
blinking_led_empty.qsf Uhlengahlengiso oluyinxenye – ukuPhunyezwa koMntu

Ukuseta iSiseko soHlolo lweSiseko

  1. Cofa iProjekthi ➤ Uhlaziyo.
  2. KwiGama loHlaziyo, khetha uhlaziyo lwe-blinking_led, kwaye emva koko ucofe uSeta okwangoku.
  3. Cofa Faka. Ukuqhwanyaza_okukhokelwayo kuboniswa njengohlaziyo lwangoku.
  4. Ukuseta Uhlobo Lohlaziyo lwe-blinking_led, cofa izabelo ➤ Useto ➤ Ngokubanzi.
  5. Kuhlobo loHlaziyo, khetha uhlengahlengiso oluyinxenye-Isiseko, emva koko ucofe u-Kulungile.
  6. Qinisekisa ukuba i blinking_led.qsf ngoku iqulathe esi sabelo silandelayo: ##blinking_led.qsf set_global_assignment -igama REVISION_TYPE PR_BASE

Ukudala uHlaziyo loPhumezo

  1. Ukuvula uHlaziyo lwebhokisi yencoko yababini, cofa iProjekthi ➤ Uhlaziyo.
  2. Ukwenza uhlaziyo olutsha, cofa kabini < >.
  3. Kwigama lohlaziyo, khankanya blinking_led_default kwaye ukhethe blinking_led for Ngokusekwe kuhlaziyo.
  4. Kuhlobo loHlaziyo, khetha Uhlengahlengiso Olungaphelelanga -Ukwenziwa Komntu.

Ukudala uHlaziyoi-intel-750856-Agilex-FPGA-iBhodi yoPhuhliso-FIG-1 (14)

  1. Ngokufanayo, seta uhlobo loHlaziyo lwe-blinking_led_slow kunye nohlaziyo olungenanto lwe-blinking_led_empty.
  2. Qinisekisa ukuba nganye .qsf file ngoku iqulathe esi sabelo silandelayo: set_global_assignment -igama REVISION_TYPE PR_IMPL set_instance_assignment -igama ENTITY_REBINDING \ place_holder -to u_blinking_led apho, place_holder ligama lequmrhu elihlala likhona kuhlaziyo olutsha lokuphunyezwa kwePR.

Uhlaziyo lweProjekthii-intel-750856-Agilex-FPGA-iBhodi yoPhuhliso-FIG-1 (16)

Ukuqulunqa uHlaziyo lweSiseko

  1. Ukuqulunqa uhlaziyo olusisiseko, cofa Ukuqhuba ➤ Qalisa ukuHlanganisa. Kungenjalo, lo myalelo ulandelayo uqulunqa isiseko sohlaziyo: quartus_sh –flow compile blinking_led -c blinking_led
  2. Jonga i-bitstream fileezivelisa kwimveliso_files ulawulo.

Yenziwe Files

Igama Uhlobo Inkcazo
blinking_led.sof Inkqubo yesiseko file Isetyenziselwa uqwalaselo lwesiseko setshiphu epheleleyo
blinking_led.pr_partition.rbf PR bitstream file kwisiseko sobuntu Isetyenziselwa uhlengahlengiso oluyinxenye lwesiseko sobuntu.
blinking_led_static.qdb .qdb idatabase file Ugcino lwedatha olugqityiweyo file isetyenziselwa ukungenisa ngaphandle ummandla ongatshintshiyo.

Ulwazi olunxulumeneyo

  • "Floorplan uYilo lokuLungiselela iNxalenye" ​​kwi-Intel Quartus Prime Pro Edition IsiKhokelo somsebenzisi: Uhlengahlengiso oluyinxenye
  • "Ukusebenzisa izithintelo zeFloorplan ngokunyukayo" kwi-Intel Quartus Prime Pro Edition Isikhokelo somsebenzisi: Uhlengahlengiso oluyinxenye

Ukulungiselela uHlaziyo lokuPhunyezwa kwePR
Kufuneka ulungiselele uhlaziyo lokuphunyezwa kwePR phambi kokuba uqokelele kwaye uvelise i-bitstream yePR yenkqubo yesixhobo. Olu seto luquka ukongeza ummandla ongatshintshiyo .qdb file njengomthombo file kuhlaziyo ngalunye lokuphumeza. Ukongeza, kufuneka ucacise iqumrhu elihambelanayo lengingqi ye-PR.

  1. Ukuseta uhlaziyo lwangoku, cofa iProjekthi ➤ Uhlaziyo, khetha blinking_led_default njengegama loHlaziyo, uze ucofe uSeta okwangoku.
  2. Ukuqinisekisa umthombo ochanekileyo wohlaziyo ngalunye lokuphunyezwa, cofa iProjekthi ➤Yongeza/Susa Files kwiProjekthi. I blinking_led.sv file ibonakala kwi file uluhlu.

Files Iphephai-intel-750856-Agilex-FPGA-iBhodi yoPhuhliso-FIG-1 (17)

  1. Phinda amanyathelo oku-1 ukuya ku-2 ukuqinisekisa omnye umthombo wohlaziyo wokuphunyezwa files:
Ukuphunyezwa kweGama loHlaziyo Umthombo File
blinking_led_default blinking_led.sv
ukuqhwanyaza_kukhokelela_akunanto blinking_led_empty.sv
blinking_led_slow blinking_led_slow.sv
  1. Ukuqinisekisa i.qdb file ehambelana nesahlulelo seengcambu, cofa izabelo ➤ Ifestile yezahlulo zoyilo. Qinisekisa ukuba iDatabase yeSahlulo File ixela i blinking_led_static.qdb file, okanye nqakraza kabini iNdawo yeNkxaso yeSahlulo File iseli ukukhankanya oku file. Kungenjalo, lo myalelo ulandelayo wabela oku file: set_instance_assignment -igama QDB_FILE_ICANDELO \ blinking_led_static.qdb -ukuya |
  2. Kwiseli yokuBophelela kwakhona kweZiko, khankanya igama lequmrhu lesahlulelo ngasinye sePR ositshintshayo kuhlaziyo lophumezo. Kublinking_led_default uhlengahlengiso lomiliselo, igama lequmrhu liyaqhwanyaza. Kule tutorial, ubhala ngaphezulu u_blinking_led umzekelo ukusuka kuhlaziyo olusisiseko oluqokelelweyo kunye nequmrhu elitsha elikhohliweyo.

Phawula: Isabelo esiphinda sibophelele iqumrhu lesibambeli songezwa kuhlaziyo lophumezo ngokuzenzekelayo. Nangona kunjalo, kufuneka utshintshe igama lequmrhu elingagqibekanga kwisabelo kwigama lequmrhu elifanelekileyo kuyilo lwakho.

Ukuphunyezwa kweGama loHlaziyo Ukubophelela kwakhona kweQumrhu
blinking_led_default blinking_led
blinking_led_slow blinking_led_slow
ukuqhwanyaza_kukhokelela_akunanto ukuqhwanyaza_kukhokelela_akunanto

Ukubophelela kwakhona kweZikoi-intel-750856-Agilex-FPGA-iBhodi yoPhuhliso-FIG-1 (18)

  1. Ukuqokelela uyilo, cofa uKuqhubekisa ➤ Qalisa ukuHlanganisa. Kungenjalo, lo myalelo ulandelayo uqulunqa le projekthi: quartus_sh –flow compile blinking_led –c blinking_led_default
  2. Phinda la manyathelo angasentla ukulungiselela blinking_led_slow and blinking_led_empty revisions: quartus_sh –flow compile blinking_led –c blinking_led_slow quartus_sh –flow compile blinking_led –c blinking_led_empt

Phawula: Ungakhankanya naziphi na iisetingi ezithile zeFitter ofuna ukuzisebenzisa ngexesha lokuqulunqwa kwePR. Iisetingi ezichanekileyo zichaphazela kuphela ukufaneleka komntu, ngaphandle kokuchaphazela ummandla ongatshintshiyo ongenisiweyo.

Ukucwangcisa iBhodi
Esi sifundo sisebenzisa ibhodi yophuhliso ye-Intel Agilex F-Series FPGA kwibhentshi, ngaphandle kwe-PCIe * slot kumatshini wakho wokubamba. Ngaphambi kokuba ucwangcise ibhodi, qinisekisa ukuba uwagqibile la manyathelo alandelayo:

  1. Xhuma unikezelo lwamandla kwibhodi yophuhliso lwe-Intel Agilex F-Series FPGA.
  2. Qhagamshela i-Intel FPGA Download Cable phakathi kwe-PC USB port yakho kunye ne-Intel FPGA Khuphela iCable port kwibhodi yophuhliso.

Ukuqhuba uyilo kwibhodi yophuhliso ye-Intel Agilex F-Series FPGA:

  1. Vula isoftware yeIntel Quartus Prime kwaye ucofe iziXhobo ➤ uMdwelisi.
  2. KuMdwelisi, cofa ukuseta izixhobo kwaye ukhethe i-USB-Blaster.
  3. Cofa ukufumanisa ngokuzenzekela kwaye ukhethe isixhobo, AGFB014R24AR0.
  4. Cofa u-Kulungile. Isoftware ye-Intel Quartus Prime ibona kwaye ihlaziye uMdwelisi ngezixhobo ezintathu zeFPGA ebhodini.
  5. Khetha isixhobo se-AGFB014R24AR0, cofa Guqula File kwaye ulayishe i blinking_led_default.sof file.
  6. Yenza iNkqubo/uLungiselelo lwe blinking_led_default.sof file.
  7. Cofa uQalisa kwaye ulinde ukuba ibha yenkqubela phambili ifike kwi-100%.
  8. Jonga ii-LEDs ebhodini zidanyaza ngamaxesha afanayo noyilo lweflethi lokuqala.
  9. Ukucwangcisa kuphela ummandla wePR, cofa ekunene kwi blinking_led_default.sof file kwiNkqubo kwaye nqakraza Yongeza iNkqubo yePR File.
  10. Khetha i blinking_led_slow.pr_partition.rbf file.
  11. Khubaza iNkqubo/uLungiselelo lwe blinking_led_default.sof file.
  12. Yenza iNkqubo/uLungiselelo lwe blinking_led_slow.pr_partition.rbf file kwaye ucofe Qala. Ebhodini, jonga i-LED[0] kunye ne-LED[1] ziqhubeka ukuqhwanyaza. Xa ibha yenkqubela phambili ifikelela kwi-100%, i-LED[2] kunye ne-LED[3] iyaqhwanyaza kancinci.
  13. Ukucwangcisa ngokutsha ummandla wePR, cofa ekunene kwi .rbf file kuMdwelisi kwaye nqakraza Guqula iNkqubo yePR File.
  14. Khetha i.rbf fileukuba abanye abantu ababini bajonge indlela yokuziphatha ebhodini. Ilayisha i-blinking_led_default.rbf file ibangela ukuba ii-LED ziqhwanyaze ngamaxesha athile, kwaye ilayishwe blinking_led_empty.rbf file ibangela ukuba ii-LEDs zihlale ZIVULIWE.

Ukucwangcisa iBhodi yoPhuhliso lwe-Intel Agilex F-Series FPGAi-intel-750856-Agilex-FPGA-iBhodi yoPhuhliso-FIG-1 (19)Hardware Testing Flow

Olu landelelwano lulandelayo luchaza ireferensi yoyilo lokuhamba kovavanyo lwehardware.
Isixhobo se-Intel Agilex sokuSeta i-Hardware ye-Host yangaphandlei-intel-750856-Agilex-FPGA-iBhodi yoPhuhliso-FIG-1 (20)

Inkqubo uMncedi FPGA (umamkeli wangaphandle)
Olu landelelwano lulandelayo luchaza udweliso lwenkqubo umncedisi weFPGA esebenza njengenkqubo yePR umamkeli wangaphandle:

  1. Chaza isethingi yojongano lostrimisho lwe-Avalon oluhambelana nendlela oyikhethayo (x8, x16, okanye x32).
  2. Qalisa iqonga ngokucwangcisa umncedisi weFPGA usebenzisa i-Intel Quartus Prime Programmer kunye nentambo yoqwalaselo eqhagamshelweyo.
  3. Usebenzisa umncedisi we-FPGA, funda i-CONF_DONE kunye ne-AVST_READY iimpawu. CONF_DONE kufuneka ibe ngu-0, AVST_READY kufuneka ibe ngu-1. Ingqiqo ephezulu kule pin ibonisa ukuba iSDM ikulungele ukwamkela idatha evela kumamkeli wangaphandle. Le mveliso yinxalenye yeSDM I/O.

Phawula: I-CONF_DONE iphini ibonisa umamkeli wangaphandle ukuba ugqithiso lwe-bitstream luphumelele. Sebenzisa le miqondiso kuphela ukujonga inkqubo epheleleyo yoqwalaselo lwetshiphu. Jonga kwi-Intel Agilex Configuration User Guide ngolwazi olungakumbi kule pin.

Inkqubo iDUT FPGA ngeFull Chip SOF ngeMamkeli waNgaphandle Olu landelelwano lulandelayo luchaza inkqubo yeDUT FPGA ngetshiphu epheleleyo yeSRAM Object File (.sof) usebenzisa umamkeli Avalon ujongano lostrimisho:

  1. Bhala i-bitstream epheleleyo ye-chip kwi-DDR4 imemori yangaphandle yomncedisi we-FPGA (umamkeli wangaphandle).
  2. Qwalasela iDUT FPGA ngetshiphu epheleleyo .sof usebenzisa ujongano lostrimisho lweAvalon (x8, x16, x32).
  3. Funda isimo seDUT FPGA iimpawu zoqwalaselo. CONF_DONE kufuneka abe ngu-1, AVST_READY kufuneka abe ngu-0.

Iingcaciso zexesha: Uhlengahlengiso Olungaphelelanga UMlawuli Wangaphandle we-Intel FPGA IPi-intel-750856-Agilex-FPGA-iBhodi yoPhuhliso-FIG-1 (21)

Cwangcisa i-DUT FPGA ngoMntu wokuQala ngokusebenzisa umamkeli waNgaphandle

  1. Faka umkhenkce kwindawo ekujoliswe kuyo yePR kwi-DUT FPGA.
  2. Ukusebenzisa i-Intel Quartus Prime System Console, qinisekisa ukuba pr_request ukuqalisa uhlengahlengiso oluyinxenye. AVST_READY kufuneka ibeyi-1.
  3. Bhala i-PR persona bitstream yokuqala kwi-DDR4 inkumbulo yangaphandle yomncedisi weFPGA (umamkeli wangaphandle).
  4. Usebenzisa ujongano lostrimisho lwe-Avalon (x8, x16, x32), qwalasela kwakhona i-DUT FPGA nge-bitstream yokuqala yomntu.
  5. Ukujonga ubume bePR, cofa iziXhobo ➤ Ikhonsoli yeSixokelelwano ukumisela iConsole yeNkqubo. KwiConsole yeNkqubo, jonga ubume bePR:
    • pr_impazamo yi-2-uhlengahlengiso lusaqhubeka.
    • pr_impazamo ngu-3-uhlengahlengiso lugqityiwe.
  6. Faka isicelo sokungakhexisi kwingingqi yePR kwi-DUT FPGA.

Phawula: Ukuba kukho imposiso ngexesha lokusebenza kwePR, njengokungaphumeleli kuqwalaselo loguqulelo okanye uqwalaselo logunyaziso, umsebenzi wePR uyayekiswa.

Ulwazi olunxulumeneyo

  • Intel Agilex Configuration User Guide
  • Intel Quartus Prime Pro Edition Isikhokelo somsebenzisi: Izixhobo zokulungisa iimpazamo

IMbali yoHlaziyo loXwebhu lwe-AN 991: Uhlengahlengiso oluyinxenye ngokusebenzisa izikhonkwane zoLungiselelo (Umsingathi waNgaphandle) Uyilo lweReferensi ye-Intel Agilex F-Series FPGA Development Board

Inguqulelo yoXwebhu Intel Quartus Prime Version Iinguqu
2022.11.14 22.3 • Ukukhululwa kokuqala.

AN 991: Uqwalaselo ngokutsha oluyinxenye ngokusebenzisa izikhonkwane zoLungiselelo (Inginginya yaNgaphandle) Uyilo lweReferensi: ye-Intel Agilex F-Series FPGA Development Board

Iimpendulo kwii-FAQ eziphezulu:

  • Q Yintoni i-PR ngokusebenzisa izikhonkwane zoqwalaselo?
  • A Ulungelelwaniso lomamkeli wangaphandle kwiphepha lesi-3
  • Q Ndidinga ntoni kolu yilo lwereferensi?
  • A IiMfuno zoYilo lwezalathiso kwiphepha lesi-6
  • Q Ndingalufumana phi uyilo lwereferensi?
  • A IiMfuno zoYilo lwezalathiso kwiphepha lesi-6
  • Q Ndiyenza njani iPR ngolungelelwaniso lwangaphandle?
  • A Ubuchule boYilo lweReferensi kwiphepha lesi-6
  • Q Yintoni i-PR persona?
  • A Ukuchaza Abantu kwiphepha 11
  • Q Ndiyicwangcisa njani ibhodi?
  • A Inkqubo yeBhodi kwiphepha le-17
  • Q Yeyiphi imiba ye-PR eyaziwayo kunye nemida?
  • A IiForam zeNkxaso ze-Intel FPGA: PR
  • Q Ngaba unalo uqeqesho kwi-PR?
  • A Intel FPGA Ikhathalogu yoQeqesho lobuGcisa

Online Version Thumela Impendulo

  • Isazisi: 750856
  • Inguqulelo: 2022.11.14

Amaxwebhu / Izibonelelo

Intel 750856 Ibhodi yoPhuhliso lwe-Agilex FPGA [pdf] Isikhokelo somsebenzisi
750856, 750857, 750856 Ibhodi yoPhuhliso ye-Agilex FPGA, iBhodi yoPhuhliso ye-Agilex FPGA, iBhodi yoPhuhliso yeFPGA, iBhodi yoPhuhliso, iBhodi

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