Intel 750856 Agilex FPGA Board Development

Tlhahisoleseding ya Sehlahiswa

Moralo ona oa litšupiso ke oa Intel Agilex F-Series FPGA Development Board. E sebelisa Molaoli oa Phetoho e Ntle ea Kantle ea Intel FPGA IP mme e na le sebaka se bonolo sa PR. Intel Agilex Device External Host Hardware Setup e na le sesebelisoa sa kantle (Helper FPGA), DUT FPGA, le moralo oa hau oa kantle oa moamoheli. Moralo oa moamoheli sesebelisoa sa kantle o ikarabella bakeng sa ho amohela ts'ebetso ea PR. Lipini tsa PR li sebelisoa ho hokahanya lisebelisoa ka bobeli mme e ka ba li-I/O tsa mosebelisi ofe kapa ofe.

Litaelo tsa Tšebeliso ea Sehlahisoa

Tlhophiso ea Moamoheli oa Kantle

Ho etsa tlhophiso ea moamoheli oa kantle, latela mehato ena:

1. Etsa moralo oa moamoheli sesebelisoa sa kantle ho amohela ts'ebetso ea PR.
2. Hokela lithakhisa tsa PR ho tloha sesebelisoa sa kantle ho Setaolo sa Phethahatso e Ntle sa Kantle sa Intel FPGA IP ho DUT FPGA.
3. Phatlalatso ea tlhophiso ea data ho tloha ho moralo oa moamoheli ho ea ho likhoele tsa sehokelo sa Intel Agilex Avalon tse tsamaellanang le matšoao a ho ts'oarana ka matsoho ho tsoa ho IP.

Phetoho e sa Feleng ka Ts'ebetso ea Li-Configuration Pins

Tatelano e latelang e hlalosa ts'ebetso ea tlhophiso e sa fellang ka likhoele tsa tlhophiso:

1. Etsa pini ea pr_request e hokahantsoeng le Selaoli sa Phethahatso sa Kantle sa Sebopeho sa Kantle sa Intel FPGA IP.
2. IP e fana ka letšoao le phathahaneng ho bontša hore ts'ebetso ea PR e ntse e tsoela pele (ho ikhethela).
3. Haeba tsamaiso ea tlhophiso e se e loketse ts'ebetso ea PR, pin ea avst_ready e tiisitsoe, e bontšang hore e se e loketse ho amohela data.
4. Tsamaisa lintlha tsa tlhophiso ea PR holim'a li-avst_data pin le avst_valid pin, ho latela tlhaloso ea Avalon ea ho phallela bakeng sa phetisetso ea data ka khatello ea morao-rao.
5. E emisa ho phallela ha avst_ready pin e tlosoa.
6. Tlosa phini ea avst_ready ho bontša hore ha ho na data e hlokahalang bakeng sa ts'ebetso ea PR.
7. Taolo ea Phetoho e Ntle ea Kantle Intel FPGA IP e hlakola lets'oao le phathahaneng ho bonts'a pheletso ea ts'ebetso (ka boikhethelo).

Phetoho e 'ngoe e sa Feleng ka Lithakhisa tsa Tlhophiso (Moamoheli oa Kantle) Moralo oa Litšupiso

Tlhahisoleseling ena ea ts'ebeliso e bonts'a ntlafatso e sa lekanyetsoang ka likhoele tsa tlhophiso (moamoheli oa kantle) ho boto ea nts'etsopele ea Intel® Agilex® F-Series FPGA.

Reference Design Overview

Karolo ea PR) e u lumella ho hlophisa karolo ea FPGA ka matla, ha moralo o setseng oa FPGA o ntse o tsoela pele ho sebetsa. U ka theha batho ba bangata bakeng sa sebaka se itseng ka moralo oa hau se sa ameng ts'ebetso libakeng tse kantle ho sebaka sena. Mokhoa ona o sebetsa hantle lits'ebetsong moo mesebetsi e mengata e arolelanang lisebelisoa tse tšoanang tsa FPGA. Mofuta oa hajoale oa software ea Intel Quartus® Prime Pro Edition e hlahisa phallo e ncha le e nolofalitsoeng ea pokello bakeng sa phetisetso e itseng. Moralo ona oa litšupiso oa Intel Agilex o sebelisa Setsi sa Ts'ebetso ea Kantle ea Configuration Intel FPGA IP mme e na le sebaka se bonolo sa PR.

Sesebelisoa sa Intel Agilex Sesebelisoa sa Kantle sa Host Hardware Seta

Tlhophiso ea Moamoheli oa Kantle

Ka tlhophiso ea moamoheli oa kantle, o tlameha ho qala ka ho theha moralo oa moamoheli sesebelisoa sa kantle ho amohela ts'ebetso ea PR, joalo ka ha Intel Agilex Device External Host Hardware Setup e bonts'a. Moralo oa moamoheli o fana ka lintlha tsa tlhophiso ho li-pin tsa Intel Agilex Avalon tse tsamaisanang le matšoao a ho ts'oarana ka matsoho a PR a tsoang ho Setsi sa Ts'ebetso sa Kantle sa Configuration Controller Intel FPGA IP. Lipini tsa PR tseo u li sebelisang ho hokahanya lisebelisoa ka bobeli e ka ba li-I/O tsa mosebelisi ofe kapa ofe.

Tatelano e latelang e hlalosa tlhophiso e sa fellang ka ts'ebetso ea likhoele tsa tlhophiso:

1. Ntlha ea pele, fana ka pini ea pr_request e hokahaneng le Selaoli sa Sebopeho sa Kantle sa Configuration Intel FPGA IP.
2. IP e fana ka letšoao le phathahaneng ho bontša hore ts'ebetso ea PR e ntse e tsoela pele (ho ikhethela).
3. Haeba tsamaiso ea tlhophiso e se e loketse ho kena ts'ebetsong ea PR, avst_ready pin e tiisitsoe e bontšang hore e se e loketse ho amohela data.
4. Qala ho tsamaisa lintlha tsa tlhophiso ea PR holim'a li-avst_data pins le avst_valid pin, ha u ntse u shebeletse litlhaloso tsa Avalon bakeng sa phetiso ea data ka khatello ea morao-rao.
5. E emisa ho phallela ha avst_ready pin e hlakisoa.
6. Ka mor'a ho phallela lintlha tsohle tsa tlhophiso, avst_ready pin ha e khothalletsoe ho bontša hore ha ho sa hlokahala data bakeng sa ts'ebetso ea PR.
7. Taolo ea Phetoho e Ntle ea Kantle ea Intel FPGA IP e theola lets'oao le phathahaneng ho bonts'a pheletso ea ts'ebetso (ka boikhethelo).
8. U ka sheba li-pr_done le pr_error ho netefatsa hore na ts'ebetso ea PR e phethiloe ka katleho. Haeba phoso e etsahala, joalo ka ho hloleha ha tlhahlobo ea mofuta le ho hlahloba tumello, ts'ebetso ea PR e emisa.

Lintlha Tse Amanang

• Intel Agilex F-Series FPGA Development Kit Web Leqephe
• Intel Agilex F-Series FPGA Development Kit User Guide
• Tataiso ea Mosebelisi ea Intel Quartus Prime Pro Edition: Phetoho e sa Feleng

Taolo ea Phetoho e Ntle ea Kantle Intel FPGA IP
Selaoli sa Litlhophiso sa Kantle sa Litlhophiso sea hlokahala ho sebelisa likhoele tsa tlhophiso ho tsamaisa data ea PR bakeng sa ts'ebetso ea PR. U tlameha ho hokela likou tsohle tsa boemo bo holimo tsa Selaoli se Seng sa Litlhophiso tsa Kantle sa Intel FPGA IP ho pr_request pin ho lumella ho ts'oarana ka letsoho ha moamoheli le molaoli oa sesebelisoa se sireletsehileng (SDM) ho tloha bohareng. SDM e etsa qeto ea hore na u ka sebelisa mefuta efe ea likhoele tsa tlhophiso, ho latela maemo a hau a MSEL.

Taolo ea Phetoho e Ntle ea Kantle Intel FPGA IP

Litlhophiso tsa Parameter ea Litlhophiso tse sa Feleng tsa Kantle

Paramethara	Boleng	Tlhaloso
Numella Interface e Busy	Thusa or Thibela	E o dumella ho Nolofatsa kapa ho Thibela Sehokelo se Busy, se fanang ka letshwao le bontshang hore ts'ebetso ea PR e ntse e tsoela pele nakong ea litlhophiso tsa kantle. Default setting ke Thibela.

Karolo e 'ngoe ea Maemeli a Taolo ea Litlhophiso tsa Kantle

Lebitso la Port	Bophara	Tataiso	Mosebetsi
pr_kopo	1	Kenyeletso	E bontša hore ts'ebetso ea PR e se e loketse ho qala. Letšoao ke kotopo e sa lumellaneng le lets'oao la oache efe kapa efe.
pr_error	2	Sephetho	E bontša phoso e sa fellang ea tlhophiso.: • 2'b01—phoso e akaretsang ea PR • 2'b11—phoso ea bitstream e sa lumellaneng Lipontšo tsena ke li-conduits tse sa lumellaneng le mohloli ofe kapa ofe oa oache.
pr_etsa	1	Sephetho	E bontša hore ts'ebetso ea PR e felile. Letšoao ke kotopo e sa lumellaneng le lets'oao la oache efe kapa efe.
qala_addr	1	Kenyeletso	E totobatsa aterese ea ho qala ea data ea PR ho Active Serial Flash. O nolofalletsa letšoao lena ka ho khetha leha e le efe Avalon®-ST or Active Serial bakeng sa Numella Avalon-ST Pins kapa Active Serial Pins paramethara. Letšoao ke kotopo e sa lumellaneng le lets'oao la oache efe kapa efe.
tsosolosa	1	Kenyeletso	Lets'oao la ho seta botjha le hodimo e sebetsang.
tsoa_clk	1	Sephetho	Mohloli oa oache o hlahisang ho tsoa ho oscillator e ka hare.
phathahane	1	Sephetho	IP e fana ka lets'oao lena ho bonts'a phetiso ea data ea PR e ntse e tsoela pele. O nolofalletsa lets'oao lena ka ho khetha Thusa bakeng sa Dumella interface e phathahaneng paramethara.

Litlhoko tsa Moralo oa Reference

Tšebeliso ea sesebelisoa sena e hloka lintlha tse latelang:

• Ho kenya mofuta oa Intel Quartus Prime Pro Edition 22.3 ka tšehetso bakeng sa lelapa la sesebelisoa sa Intel Agilex.
• Khokahano le boto ea nts'etsopele ea Intel Agilex F-Series FPGA bencheng.
• Download ea moralo exampe fumaneha sebakeng se latelang: https://github.com/intel/fpga-partial-reconfig.

Ho khoasolla moralo exampLe:

1. Tobetsa Clone kapa download.
2. Tobetsa Download ZIP. Unzip ea fpga-partial-reconfig-master.zip file.
3. Tsamaea ho li-tutorials/agilex_external_pr_configuration subfolder ho fumana moralo oa litšupiso.

Reference Design Walkthrough

Mehato e latelang e hlalosa ts'ebetsong ea ntlafatso e sa fellang ka lithapo tsa tlhophiso (moamoheli oa kantle) ho boto ea nts'etsopele ea Intel Agilex F-Series FPGA:

• Mohato oa 1: Rea qala
• Mohato oa 2: Ho theha Karolo ea Moqapi
• Mohato oa 3: Ho Abela Libaka tsa ho Bea le ho Tsamaisa Litsela
• Mohato oa 4: Ho eketsa IP ea Setsi sa Tlhophiso ea Kantle ea Sebopeho sa Kantle
• Mohato oa 5: Ho Hlalosa Batho
• Mohato oa 6: Ho theha Liphetoho
• Mohato oa 7: Ho bokella Base Revision
• Mohato oa 8: Ho Lokisetsa Liphetoho tsa Phethahatso ea PR
• Mohato oa 9: Lenaneo la Boto

Mohato oa 1: Ho Qala
Ho kopitsa moralo oa litšupiso files sebakeng sa hau sa ts'ebetso 'me u hlophise moralo oa sephara sa blinking_led:

1. Theha bukana sebakeng seo u sebetsang ho sona, agilex_pcie_devkit_blinking_led_pr.
2. Kopitsa lithupelo tse jarollotsoeng/agilex_pcie_devkit_blinking_led/flat sub-folders ho directory, agilex_pcie_devkit_blinking_led_pr.
3. Ho software ea Intel Quartus Prime Pro Edition, tobetsa File ➤ Open Project ebe u khetha blinking_led.qpf.
4. Ho hlakisa boemo ba maemo a moralo o bataletseng, tobetsa Ts'ebetso ➤ Qala ➤ Qala Tlhahlobo & Synthesis. Ntle le moo, molaong oa taelo, tsamaisa taelo e latelang: quartus_syn blinking_led -c blinking_led

Ho theha Karolo ea Moqapi

U tlameha ho theha likarolo tsa moralo bakeng sa sebaka se seng le se seng sa PR seo u batlang ho se hlophisa bocha. Mehato e latelang e theha karohano ea moralo bakeng sa mohlala oa u_blinking_led.

Ho theha Partitions Design

1. Tobetsa ka ho le letona u_blinking_led mohlala ho Project Navigator ebe o tobetsa Design Partition ➤ Reconfigurable. Letšoao la karohano ea moralo le hlaha haufi le ketsahalo ka 'ngoe e behiloeng joalo ka karohano.
2. Tobetsa Mosebetsi ➤ Fesetere ea Likarolo tsa Moralo. Fesetere e bonts'a likarolo tsohle tsa moralo oa projeke.
3. Fetola lebitso la karohano Fesetereng ea Likaroloana tsa Moralo ka ho tobetsa lebitso habeli. Bakeng sa moralo ona oa litšupiso, reha lebitso la karohano ho pr_partition
   • Hlokomela: Ha o theha karohano, software ea Intel Quartus Prime e iketsetsa lebitso la karohano, ho latela lebitso la mohlala le tsela ea maemo. Lebitso lena la karohano la kamehla le ka fapana ho latela mohlala ka mong.
4. Ho romela kantle sebaka se phethiloeng se tsitsitseng ho tsoa pokellong ea tlhahlobo ea mantlha, tobetsa habeli ho kenya bakeng sa root_partition ho Post Final Export. File kholomo, 'me u thaepe blinking_led_static. gdb.

Ho Romella Snapshot ea ho Qetela ho Fensetere ea Likarolo tsa MoqapiNetefatsa hore blinking_led.qsf e na le mesebetsi e latelang, e tsamaellanang le karohano ea hau ea moralo e ka lokisoang bocha:

Lintlha Tse Amanang
"Theha Likarolo tsa Moralo" ho Intel Quartus Prime Pro Edition Tataiso ea Mosebelisi: Phetoho e sa Feleng

Ho Abela Sebaka le Sebaka sa Tsela bakeng sa Karohano ea PR
Bakeng sa ntlafatso e 'ngoe le e' ngoe eo u e etsang, moralo oa PR o phalla o beha motho oa mantlha sebakeng sa hau sa PR. Ho fumana le ho abela sebaka sa PR sebakeng sa meralo ea lisebelisoa bakeng sa tlhahlobo ea hau ea mantlha:

1. Tobetsa ka ho le letona u_blinking_led mohlala ho Project Navigator ebe o tobetsa Logic Lock Sebaka ➤ Theha Sebaka se Secha sa Lock Lock. Sebaka sena se hlaha fensetereng ea Logic Lock Regions.
2. Sebaka seo u leng ho sona se tlameha ho kenyeletsa le blinking_led logic. Khetha sebaka seo u se behileng ka ho fumana node ho Chip Planner. Tobetsa ka ho le letona lebitso la sebaka sa u_blinking_led ho Logic Lock Regions Window ebe o tobetsa

Fumana Node ➤ Fumana ka Chip Planner. Sebaka sa u_blinking_led se na le mebala

Sebaka sa Node ea Chip Planner bakeng sa blinking_led

1. Fensetereng ea Logic Lock Regions, hlakisa lihokahanyo tsa sebaka sa sebaka sa Origin. Tšimoloho e lumellana le sekhutlo se ka tlaase ho le letšehali la sebaka seo. Bakeng sa mohlalaample, ho beha sebaka sa sebaka se nang le (X1 Y1) likhokahano joalo ka (163 4), hlalosa Origin joalo ka X163_Y4. Software ea Intel Quartus Prime e ipabola ka bo eona (X2 Y2) likhokahano (holimo ka ho le letona) bakeng sa sebaka sa sebaka, ho ipapisitse le bolelele le bophara boo u bo boletseng.
   • Hlokomela: Thupelo ena e sebelisa likhokahano tsa (X1 Y1) - (163 4), le bolelele le bophara ba 20 bakeng sa sebaka sa ho beoa. Hlalosa boleng bofe kapa bofe bakeng sa sebaka seo ho beoang ho sona. Netefatsa hore sebaka se akaretsa blinking_led logic.
2. Numella likhetho tsa Reserved le tsa Core-Feela.
3. Tobetsa habeli khetho ea Sebaka sa Routing. Lebokose la puisano la Litlhophiso tsa Sebaka sa Logic Lock Routing lea hlaha.
4. Kgetha E tsitsitseng le katoloso bakeng sa mofuta wa Routing. Ho khetha khetho ena ho fana ka bolelele ba katoloso ea 2.
   • Hlokomela: Sebaka sa litsela se tlameha ho ba seholo ho feta sebaka seo ho behoang ho sona, ho fana ka maemo a eketsehileng bakeng sa Fitter ha enjene e tsamaisa batho ba fapaneng.

Logic Lock Libaka FesetereNetefatsa hore blinking_led.qsf e na le mesebetsi e latelang, e tsamaellanang le floorplanning ea hau:

Lintlha Tse Amanang
"Floorplan the Partial Reconfiguration Design" ho Intel Quartus Prime Pro Edition Tataiso ea mosebelisi: Phetoho e 'Ngoe

Eketsa Selaoli sa Sebopeho sa Kantle sa Sebopeho sa Kantle sa Intel FPGA IP
The Partial Reconfiguration External Configuration Controller Intel FPGA IP interfaces le Intel Agilex PR thibela thibela ho laola mohloli oa bitstream. U tlameha ho kenya IP ena ho moralo oa hau ho kenya ts'ebetsong tlhophiso ea kantle. Latela mehato ena ho kenya Selaoli sa Tlhophiso ea Kantle ea Litlhophiso tse sa Feleng
Intel FPGA IP ho projeke ea hau:

1. Tlanya Phetoho e sa Feleng sebakeng sa ho batla Khataloji ea IP (Lisebelisoa ➤ IP Catalog).
2. Tobetsa habeli Taolo ea Tlhophiso e Ntle ea Kantle ea Intel FPGA IP.
3. Ka lebokoseng la puisano la Create IP Variant, thaepa outside_host_pr_ip joalo ka File lebitso, ebe o tobetsa Create. Mohlophisi oa parameter oa hlaha.
4. Bakeng sa Enable busy interface parameter, khetha Disable (setting ea kamehla). Ha o hloka ho sebelisa lets'oao lena, o ka fetolela litlhophiso ho Enable.

Numella Paramethara ea Sehokelo se Busy ho Parameter Editor

1. Tobetsa File ➤ Boloka le ho tsoa ho sebali sa paramente ntle le ho hlahisa sistimi. Mohlophisi oa parameter o hlahisa phapang ea IP ea kantle_host_pr_ip.ip file and adds the file ho morero oa blinking_led. AN 991: Phetoho e 'Ngoe e sa Feleng ka Lithakhisa tsa Tlhophiso (Moamoheli oa Kantle) Reference Design 750856 | 2022.11.14 AN 991:
   • Hlokomela:
   • a. Haeba u kopitsa kantle_host_pr_ip.ip file ho tsoa bukeng ea pr, edita ka bowena blinking_led.qsf file ho kenyelletsa mola o latelang: set_global_assignment -name IP_FILE pr_ip.ip
   • b. Beha IP_FILE mosebetsi ka mora SDC_FILE likabelo (blinking_led. dc) ho blinking_led.qsf ea hau file. Taelo ena e netefatsa tšitiso e nepahetseng ea mantlha ea IP ea Selaoli sa Phethahatso ea Karolo.
   • Hlokomela: Ho lemoha lioache, .sdc file bakeng sa PR IP e tlameha ho latela leha e le efe .sdc e etsang lioache tseo IP core e li sebelisang. U tsamaisa taelo ena ka ho etsa bonnete ba hore .ip file bakeng sa PR IP core e hlaha ka mor'a leha e le efe .ip files kapa .sdc filetseo u li sebelisang ho hlalosa lioache tsena ho .qsf file bakeng sa ntlafatso ea projeke ea hau ea Intel Quartus Prime. Bakeng sa tlhaiso-leseling e batsi, sheba Tataiso ea Mosebelisi ea Litharollo tsa IP tsa Karolo e Ntle.

Ho Nchafatsa Moralo oa Boemo bo Phahameng

Ho nchafatsa top.sv file ka mohlala oa PR_IP:

1. Ho kenya mohlala oa external_host_pr_ip ho moralo oa boemo bo holimo, hlakola likhoutu tse latelang top.sv file:

Ho Hlalosa Batho
Moralo ona oa litšupiso o hlalosa batho ba bararo ba arohaneng bakeng sa karohano e le 'ngoe ea PR. Ho hlalosa le ho kenyelletsa batho ba projeke ea hau:

1. Theha tse tharo SystemVerilog files, blinking_led.sv, blinking_led_slow.sv, le blinking_led_empty.sv bukeng ea hau ea ho sebetsa bakeng sa batho ba bararo.

Reference Design Personas

Hlokomela:

• blinking_led.sv e se e fumaneha joalo ka karolo ea files o kopitsa ho tsoa foleteng/ bukana e nyane. U ka sebelisa sena hape file.
• Haeba u theha SystemVerilog files ho tsoa ho Intel Quartus Prime Text Editor, thibela Add file ho ea hona joale morero kgetho, ha ho boloka le files.

Ho theha Liphetoho

Phallo ea moralo oa PR e sebelisa karolo ea ntlafatso ea projeke ho software ea Intel Quartus Prime. Moralo oa hau oa pele ke ntlafatso ea mantlha, moo o hlalosang meeli ea sebaka se sa fetoheng le libaka tse ka lokisoang bocha ho FPGA. Ho tsoa tlhahlobong ea mantlha, u theha lintlafatso tse ngata. Lintlafatso tsena li na le ts'ebetsong e fapaneng bakeng sa libaka tsa PR. Leha ho le joalo, lintlafatso tsohle tsa ts'ebetso ea PR li sebelisa liphetho tse tšoanang tsa boemo bo holimo le liphetho tsa tlhahlobo ea mantlha. Ho bokella moralo oa PR, o tlameha ho theha tlhahlobo ea ts'ebetsong ea PR bakeng sa motho ka mong. Ho feta moo, o tlameha ho fana ka mefuta ea ntlafatso bakeng sa lintlafatso ka 'ngoe. Mefuta e fumanehang ea ntlafatso ke:

• Phetoho e sa Feleng - Motheo
• Phetoho e sa Lekaneng - Phethahatso ea Motho

Lethathamo le latelang le thathamisa lebitso la ntlafatso le mofuta oa ntlafatso bakeng sa lintlafatso ka 'ngoe:

Mabitso a Phethahatso le Mefuta

Lebitso la Phetoho	Mofuta oa ntlafatso
blinking_led.qsf	Phetoho e sa Feleng - Motheo
blinking_led_default.qsf	Phetoho e sa Lekaneng - Phethahatso ea Motho
blinking_led_slow.qsf	Phetoho e sa Lekaneng - Phethahatso ea Motho
blinking_led_empty.qsf	Phetoho e sa Lekaneng - Phethahatso ea Motho

Ho beha mofuta oa Base Revision

1. Tobetsa Morero ➤ Liphetoho.
2. Ka Lebitso la Phetoho, khetha blinking_led revision, ebe o tobetsa Set Current.
3. Tobetsa Etsa kopo. Blinking_led revision e hlaha e le ntlafatso ea hajoale.
4. Ho seta Mofuta oa Phetoho bakeng sa blinking_led, tobetsa Mosebetsi ➤ Litlhophiso ➤ Kakaretso.
5. Bakeng sa Mofuta oa Phetoho, khetha Phetoho e sa Feleng - Base, ebe o tobetsa OK.
6. Netefatsa hore blinking_led.qsf hona joale e na le mosebetsi o latelang: ##blinking_led.qsf set_global_assignment -name REVISION_TYPE PR_BASE

Ho theha Liphetoho tsa Phethahatso

1. Ho bula lebokose la lipuisano la Revisions, tobetsa Morero ➤ Liphetoho.
2. Ho theha phetolelo e ncha, tobetsa habeli < >.
3. Lebitsong la Tokiso, hlakisa blinking_led_default ebe u khetha blinking_led bakeng sa Ho ipapisitsoe le ntlafatso.
4. Bakeng sa mofuta oa Phetoho, khetha Phetoho e sa Feleng - Ts'ebetso ea Motho.

Ho theha Liphetoho

1. Ka mokhoa o ts'oanang, seta mofuta oa Revision bakeng sa blinking_led_slow and blinking_led_empty revisions.
2. Netefatsa hore e 'ngoe le e 'ngoe .qsf file joale e na le mosebetsi o latelang: set_global_assignment -name REVISION_TYPE PR_IMPL set_instance_assignment -name ENTITY_REBINDING \ place_holder -ho u_blinking_led moo, place_holder ke lebitso la setheo sa kamehla bakeng sa tokiso e ncha ea ts'ebetso ea PR.

Liphetoho tsa morero

Ho bokella Base Revision

1. Ho hlophisa tlhahlobo ea motheo, tobetsa Ho sebetsa ➤ Qala ho Kopanya. Ntle le moo, taelo e latelang e bokella ntlafatso ea motheo: quartus_sh -flow compile blinking_led -c blinking_led
2. Hlahloba bitstream files tse hlahisang tlhahiso_files directory.

E hlahisitsoe Files

Lebitso	Mofuta	Tlhaloso
blinking_led.sof	Mananeo a motheo file	E sebelisoa bakeng sa tlhophiso e felletseng ea li-chip
blinking_led.pr_partition.rbf	PR bitstream file bakeng sa motho oa motheo	E sebelisoa bakeng sa phetisetso e itseng ea base persona.
blinking_led_static.qdb	.qdb database file	Database e phethiloeng file se sebedisoang ho tlisa sebaka se sa fetoheng.

Lintlha Tse Amanang

• "Floorplan the Partial Reconfiguration Design" ho Intel Quartus Prime Pro Edition Tataiso ea mosebelisi: Phetoho e 'Ngoe
• "Ho Sebelisa Lithibelo tsa Floorplan Haholo" ho Intel Quartus Prime Pro Edition Tataiso ea Mosebelisi: Phetoho e 'Ngoe

Ho Lokisetsa Liphetoho tsa Phethahatso ea PR
U tlameha ho lokisa lintlafatso tsa ts'ebetsong ea PR pele u ka bokella le ho hlahisa PR bitstream bakeng sa lisebelisoa tsa lisebelisoa. Seta sena se kenyelletsa ho kenya sebaka se sa fetoheng .qdb file joalo ka mohloli file bakeng sa ntlafatso e 'ngoe le e 'ngoe ea ts'ebetsong. Ntle le moo, o tlameha ho hlakisa setheo se tsamaisanang le sebaka sa PR.

1. Ho seta phetolelo ea hajoale, tobetsa Morero ➤ Liphetoho, khetha blinking_led_default e le lebitso la Phetolelo, ebe u tobetsa Set Current.
2. Ho netefatsa mohloli o nepahetseng bakeng sa ntlafatso e 'ngoe le e 'ngoe ea ts'ebetsong, tobetsa Morero ➤Eketsa/Tlosa Files ho Project. The blinking_led.sv file e hlaha ho file lethathamo.

Files Leqephe

1. Pheta mehato ea 1 ho isa ho ea 2 ho netefatsa mohloli o mong oa ntlafatso ea ts'ebetsong files:

Lebitso la Phethahatso ea Phethahatso	Mohloli File
blinking_led_default	blinking_led.sv
blinking_led_letho	blinking_led_empty.sv
blinking_led_butle	blinking_led_slow.sv

1. Ho netefatsa .qdb file e amanang le karohano ea metso, tobetsa Mosebetsi ➤ Fesetere ea Likarolo tsa Moqapi. Netefatsa hore Database ea Partition File e totobatsa blinking_led_static.qdb file, kapa o tobetse habeli ho Partition Database File cell ho hlakisa sena file. Ntle le moo, taelo e latelang e fana ka sena file: set_instance_assignment -name QDB_FILE_KAROLO \ blinking_led_static.qdb -to |
2. Ho Sela e Tlamang Setheo, bolela lebitso la setheo la karolo e 'ngoe le e 'ngoe ea PR eo u e fetolang tokisong ea ts'ebetso. Bakeng sa ntlafatso ea blinking_led_default, lebitso la mokhatlo le blinking_led. Thutong ena, o hlakola mohlala oa u_blinking_led ho tsoa ho "base revision completion" ka setheo se secha sa blinking_led.

Hlokomela: Mosebetsi o tlamang sets'oants'o sa sebaka o kengoa tokisong ea ts'ebetsong ka bohona. Leha ho le joalo, o tlameha ho fetola lebitso la setheo la kamehla ho la kabelo ho lebitso le loketseng la setheo bakeng sa moralo oa hau.

Lebitso la Phethahatso ea Phethahatso	Ho tlama Setheo hape
blinking_led_default	blinking_led
blinking_led_butle	blinking_led_butle
blinking_led_letho	blinking_led_letho

Ho Kopanya Setheo hape

1. Ho hlophisa moralo, tobetsa Ho sebetsa ➤ Qala ho Kopanya. Ntle le moo, taelo e latelang e bokella morero ona: quartus_sh -flow compile blinking_led -c blinking_led_default
2. Pheta mehato e ka holimo ho lokisa blinking_led_slow and blinking_led_empty revisions: quartus_sh -flow compile blinking_led -c blinking_led_slow quartus_sh -flow compile blinking_led -c blinking_led_empt

Hlokomela: U ka hlakisa litlhophiso life kapa life tse ikhethileng tsa Fitter tseo u batlang ho li sebelisa nakong ea ho kopanya ts'ebetsong ea PR. Litlhophiso tse ikhethang li ama feela ho lekana ha motho, ntle le ho ama sebaka se sa fetoheng se tsoang kantle ho naha.

Lenaneo la Boto
Thupelo ena e sebelisa boto ea nts'etsopele ea Intel Agilex F-Series FPGA bencheng, kantle ho slot ea PCIe * mochining oa hau o amohelang. Pele o hlophisa boto, etsa bonnete ba hore o phethetse mehato e latelang:

1. Hokela phepelo ea motlakase ho boto ea nts'etsopele ea Intel Agilex F-Series FPGA.
2. Hokela Intel FPGA Download Cable lipakeng tsa koung ea USB ea PC ea hau le boema-kepe ba Intel FPGA Download Cable botong ea nts'etsopele.

Ho tsamaisa moralo ho boto ea nts'etsopele ea Intel Agilex F-Series FPGA:

1. Bula software ea Intel Quartus Prime ebe o tobetsa Tools ➤ Programmer.
2. Ho Programmer, tobetsa Setupo sa Hardware ebe u khetha USB-Blaster.
3. Tobetsa Auto Detect ebe u khetha sesebelisoa, AGFB014R24AR0.
4. Tobetsa OK. Software ea Intel Quartus Prime e lemoha le ho nchafatsa Lenaneo ka lisebelisoa tse tharo tsa FPGA tse botong.
5. Khetha sesebelisoa sa AGFB014R24AR0, tobetsa Fetola File le ho laela blinking_led_default.sof file.
6. Numella Lenaneo/Configure bakeng sa blinking_led_default.sof file.
7. Tobetsa Qala 'me u emetse hore sebaka sa tsoelo-pele se fihle ho 100%.
8. Sheba li-LED tse botong li ntse li panya ka makhetlo a tšoanang le a moralo oa pele o bataletseng.
9. Ho hlophisa sebaka sa PR feela, tlanya konopo e nepahetseng ea blinking_led_default.sof file ho Programmer ebe o tobetsa Add PR Programming File.
10. Khetha blinking_led_slow.pr_partition.rbf file.
11. Thibela Lenaneo/Configure bakeng sa blinking_led_default.sof file.
12. Numella Lenaneo/Configure bakeng sa blinking_led_slow.pr_partition.rbf file ebe o tobetsa Qala. Holima boto, sheba LED[0] le LED[1] li tsoela pele ho panya. Ha sebaka sa tsoelopele se fihla ho 100%, LED[2] le LED[3] li panya butle.
13. Ho hlophisa bocha sebaka sa PR, tobetsa ka ho le letona ho .rbf file ho Programmer ebe o tobetsa Change PR Programing File.
14. Khetha .rbf files hore batho ba bang ba babeli ba shebe boitšoaro botong. E kenya blinking_led_default.rbf file e etsa hore li-LED li panye ka makhetlo a itseng, le ho kenya blinking_led_empty.rbf file e etsa hore li-LED li lule li ON.

Lenaneo la Intel Agilex F-Series FPGA Development BoardPhallo ea Tlhahlobo ea Hardware

Tatelano e latelang e hlalosa phallo ea tlhahlobo ea hardware ea moralo oa litšupiso.
Sesebelisoa sa Intel Agilex Sesebelisoa sa Kantle sa Host Hardware Seta

Lenaneo Mothusi FPGA (Moamoheli oa Kantle)
Tatelano e latelang e hlalosa ho hlophisa mothusi FPGA e sebetsang e le moamoheli oa kantle oa PR:

1. Hlalosa litlhophiso tsa Avalon streaming interface tse tsamaellanang le mokhoa oo u o khethileng (x8, x16, kapa x32).
2. Qala sethala ka ho hlophisa mothusi FPGA o sebelisa Intel Quartus Prime Programmer le thapo ea tlhophiso e hokahaneng.
3. U sebelisa FPGA ea mothusi, bala matšoao a CONF_DONE le AVST_READY. CONF_DONE e lokela ho ba 0, AVST_READY e be 1. Maikutlo a holimo ho phini ena a bontša hore SDM e se e loketse ho amohela boitsebiso bo tsoang ho moamoheli oa kantle. Sephetho sena ke karolo ea SDM I/O.

Hlokomela: Pin ea CONF_DONE e bontša moamoheli oa kantle hore phetisetso ea bitstream e atlehile. Sebelisa matšoao ana feela ho beha leihlo ts'ebetso e felletseng ea tlhophiso ea chip. Sheba ho Intel Agilex Configuration User Guide bakeng sa boitsebiso bo eketsehileng mabapi le pini ena.

Lenaneo la DUT FPGA ka Full Chip SOF ka Moamoheli oa Kantle Tatelano e latelang e hlalosa ho hlophisa DUT FPGA ka chip e felletseng ea SRAM Object File (.sof) u sebelisa sebatli sa sebatli sa Avalon:

1. Ngola chip bitstream e felletseng mohopolong oa kantle oa DDR4 oa mothusi FPGA (moamoheli oa kantle).
2. Lokisa DUT FPGA ka chip e felletseng .sof o sebelisa sebopeho sa Avalon (x8, x16, x32).
3. Bala boemo ba matšoao a tlhophiso a DUT FPGA. CONF_DONE e be 1, AVST_READY e be 0.

Litlhaloso tsa Nako: Phetoho e sa Feleng Taolo ea Kantle Intel FPGA IP

Rulahanya DUT FPGA le Motho oa Pele ka Moamoheli oa Kantle

1. Etsa kopo ea leqhoa sebakeng se lebeletsoeng sa PR ho DUT FPGA.
2. U sebelisa Intel Quartus Prime System Console, tiisa pr_request ho qala tlhophiso e sa fellang. AVST_READY e lokela ho ba 1.
3. Ngola PR persona bitstream ea pele mohopolong oa kantle oa DDR4 oa mothusi FPGA (moamoheli oa kantle).
4. U sebelisa segokanyimmediamentsi sa Avalon (x8, x16, x32), lokisa hape DUT FPGA ka "bitstream" ea pele.
5. Ho beha leihlo boemo ba PR, tobetsa Lisebelisoa ➤ System Console ho qala System Console. Ho System Console, beha leihlo boemo ba PR:
   • pr_error ke 2-reconfiguration e ntse e sebetsa.
   • pr_error ke 3 - tlhophiso e ncha e felile.
6. Etsa kopo ea ho se be leqhoa sebakeng sa PR ho DUT FPGA.

Hlokomela: Haeba phoso e etsahala nakong ea ts'ebetso ea PR, joalo ka ho hloleha ha tlhahlobo ea mofuta kapa tlhahlobo ea tumello, ts'ebetso ea PR e emisa.

Lintlha Tse Amanang

• Intel Agilex Configuration User Guide
• Tataiso ea Mosebelisi ea Intel Quartus Prime Pro Edition: Lisebelisoa tsa Debug

Nalane ea Tokomane ea Tokomane bakeng sa AN 991: Phetoho e sa Feleng ka Lithakhisa tsa Tlhophiso (Moamoheli oa Kantle) Reference Design bakeng sa Intel Agilex F-Series FPGA Development Board

Tokomane Version	Intel Quartus Prime Version	Liphetoho
2022.11.14	22.3	• Tokollo ea pele.

AN 991: Phetoho e sa Feleng ka Lithako tsa Tlhophiso (Moamoheli oa Kantle) Moralo oa Reference: bakeng sa Intel Agilex F-Series FPGA Development Board

Likarabo ho Lipotso Tse Tsoang Pele:

• Q PR ke eng ka likhoele tsa tlhophiso?
• A Tlhophiso ea Moamoheli oa Kantle leqepheng la 3
• Q Ke hloka eng bakeng sa moralo ona oa litšupiso?
• A Litlhoko tsa Moralo oa Reference leqepheng la 6
• Q Nka fumana moralo oa litšupiso hokae?
• A Litlhoko tsa Moralo oa Reference leqepheng la 6
• Q Ke etsa PR joang ka tlhophiso ea kantle?
• A Reference Design Walkthrough leqepheng la 6
• Q Motho oa PR ke eng?
• A Ho Hlalosa Batho leqepheng la 11
• Q Ke etsa lenaneo la boto joang?
• A Lenaneo la Boto leqepheng la 17
• Q Litaba le mefokolo ea PR ke life?
• A Intel FPGA Support Forums: PR
• Q O na le koetliso ka PR?
• A Intel FPGA Technical Training Catalog

Online Version Romella Maikutlo

• ID: 750856
• Mofuta: 2022.11.14

Litokomane / Lisebelisoa

Intel 750856 Agilex FPGA Board Development [pdf] Bukana ea Mosebelisi 750856, 750857, 750856 Agilex FPGA Development Board, Agilex FPGA Development Board, FPGA Development Board, Development Board, Board

Litšupiso

• Bukana ea Mosebelisi