Zviri mukati hide
1 Intel 750856 Agilex FPGA Development Board
2 Product Information
3 Mirayiridzo Yekushandiswa Kwechigadzirwa
4 Reference Dhizaini Pamusoroview
5 External Host Configuration
6 Reference Design Zvinodiwa
7 Reference Design Walkthrough
8 Kugadzira Chikamu Chekugadzira
9 Kugadzira Ongororo
10 Mazita ekudzokorora uye Marudzi
11 Kuronga iyo Intel Agilex F-Series FPGA Development BoardHardware Testing Flow
12 Zvinyorwa / Zvishandiso
12.1 References

Intel-LOGO

Intel 750856 Agilex FPGA Development Board

intel-750856-Agilex-FPGA-Development-Board-PRODUCT

Product Information

Iyi referensi dhizaini ndeyeIntel Agilex F-Series FPGA Development Board. Iyo inoshandisa iyo Partial Reconfiguration Yekunze Configuration Controller Intel FPGA IP uye ine iri nyore PR dunhu. Iyo Intel Agilex Chishandiso Chekunze Host Hardware Setup ine yekunze mudziyo (Mubatsiri FPGA), DUT FPGA, uye yako yekunze dhizaini dhizaini. Iyo dhizaini yedhizaini mune yekunze chishandiso ine basa rekutambira iyo PR maitiro. Iyo PR mapini anoshandiswa kubatanidza ese maturusi uye anogona kuve chero anowanikwa mushandisi I/Os.

Mirayiridzo Yekushandiswa Kwechigadzirwa

External Host Configuration

Kuti uite yekunze host configuration, tevera matanho aya:

  1. Gadzira dhizaini yekugamuchira mune yekunze mudziyo kuti utore iyo PR maitiro.
  2. Batanidza iyo PR mapini kubva kune yekunze mudziyo kuenda kune Partial Reconfiguration Yekunze Configuration Controller Intel FPGA IP muDUT FPGA.
  3. Simbisa data yekumisikidza kubva kumugadziri dhizaini kuenda kuIntel Agilex Avalon yekufambisa interface mapini anoenderana nePR masaini ekubata maoko kubva kuIP.

Chikamu Reconfiguration kuburikidza neKugadzirisa Pini Kushanda

Kutevedzana kunotevera kunotsanangura kushanda kwechikamu chekugadzirisa kuburikidza nemapini ekugadzirisa:

  1. Rongedza pr_request pini yakabatana nePatial Reconfiguration Yekunze Configuration Controller Intel FPGA IP.
  2. Iyo IP inosimbisa chiratidzo chakabatikana kuratidza kuti iyo PR maitiro ari kuenderera mberi (sarudzo).
  3. Kana iyo gadziriro yegadziriro yakagadzirira kushanda kwePR, pini ye avst_ready inosimbiswa, ichiratidza kuti yakagadzirira kugamuchira data.
  4. Tambanudza iyo PR yekumisikidza data pamusoro peavst_data pini uye avst_valid pini, uchitevera iyo Avalon yekushambadzira yakatarwa yekuchinjisa data nebackpressure.
  5. Kutenderera kunomira kana avst_ready pin yabviswa.
  6. De-assert iyo avst_ready pini kuratidza kuti hapana imwe data inodiwa pakushanda kwePR.
  7. The Partial Reconfiguration External Configuration Controller Intel FPGA IP de-assers iyo yakabatikana chiratidzo kuratidza kupera kwemaitiro (sarudzo).

Partial Reconfiguration kuburikidza neConfiguration Pini (External Host) Reference Dhizaini

Ichi chinyorwa chekushandisa chinoratidza kugadziridzwa kwechikamu kuburikidza nepini yekumisikidza (yekunze muenzi) pane Intel® Agilex® F-Series FPGA bhodhi yekuvandudza.

Reference Dhizaini Pamusoroview

Iyo chikamu chekugadzirisazve (PR) chimiro chinokutendera kuti ugadzirise zvakare chikamu cheFPGA zvine simba, nepo yasara FPGA dhizaini inoramba ichishanda. Iwe unogona kugadzira akawanda personas eimwe dunhu mune yako dhizaini iyo isingakanganise kushanda munzvimbo dziri kunze kwedunhu rino. Iyi nzira inoshanda mumasisitimu ayo akawanda mabasa nguva-anogovera yakafanana FPGA mudziyo zviwanikwa. Iyo yazvino vhezheni yeIntel Quartus® Prime Pro Edition software inosuma nyowani uye yakapfava yekubatanidza kuyerera kwechikamu chekugadzirisa. Iyi Intel Agilex referensi dhizaini inoshandisa iyo Partial Reconfiguration Yekunze Configuration Controller Intel FPGA IP uye ine iri nyore PR dunhu.

Intel Agilex Chishandiso Chekunze Host Hardware Setupintel-750856-Agilex-FPGA-Development-Board-FIG-1 (1)

External Host Configuration

Mukugadzirisa kwekunze kwemuenzi, iwe unofanirwa kutanga wagadzira dhizaini yedhizaini mune yekunze mudziyo kuti utore iyo PR maitiro, seIntel Agilex Chishandiso Chekunze Host Hardware Setup inoratidza. Iyo dhizaini dhizaini inoyerera data yekumisikidza kuIntel Agilex Avalon yekufambisa interface mapini anoenderana nePR masaini ekubata maoko anouya kubva kune Partial Reconfiguration External Configuration Controller Intel FPGA IP. Iyo PR mapini aunoshandisa kubatanidza ese maturusi anogona kuve chero anowanikwa mushandisi I/Os.

Iyo inotevera inoteedzana inotsanangura iyo chikamu chekugadzirisa kuburikidza nekugadzirisa pini kushanda:

  1. Chekutanga taura pr_request pini iyo yakabatana kune Partial Reconfiguration External Configuration Controller Intel FPGA IP.
  2. Iyo IP inosimbisa chiratidzo chakabatikana kuratidza kuti iyo PR maitiro ari kuenderera mberi (sarudzo).
  3. Kana iyo yekumisikidza yakagadzirira kuita PR oparesheni, iyo avst_ready pini inosimbiswa ichiratidza kuti yakagadzirira kugamuchira data.
  4. Tanga kufambisa iyo PR yekumisikidza data pamusoro peavst_data pini uye avst_valid pini, uchitarisa iyo Avalon yekushambadzira yakatarwa yekuchinjisa data nebackpressure.
  5. Kutenderera kunomira pese apo avst_ready pin yabviswa.
  6. Mushure mekushambadzira data rese rekumisikidza, iyo avst_ready pini inosimbiswa kuratidza kuti hapana imwe data inodiwa pakushanda kwePR.
  7. Iyo Partial Reconfiguration Yekunze Configuration Controller Intel FPGA IP dhizari chiratidzo chakabatikana kuratidza kupera kwemaitiro (sarudzo).
  8. Unogona kutarisa pr_done uye pr_error mapini kuti uone kana PR yakapedza zvinobudirira. Kana kukanganisa kukaitika, sekutadza kwekutarisa vhezheni uye kutariswa kwemvumo, PR inoshanda inopera.

Related Information

  • Intel Agilex F-Series FPGA Development Kit Web Page
  • Intel Agilex F-Series FPGA Development Kit User Guide
  • Intel Quartus Prime Pro Edition Mushandisi Wekushandisa: Chikamu Reconfiguration

Partial Reconfiguration Yekunze Configuration Controller Intel FPGA IP
Iyo Partial Reconfiguration Yekunze Configuration Controller inodiwa kushandisa mapini ekumisikidza kufambisa PR data yePR mashandiro. Iwe unofanirwa kubatanidza ese epamusoro-level zviteshi zvePartial Reconfiguration External Configuration Controller Intel FPGA IP kune pr_request pini kuti ubvumire kubata maoko kweanotambira neakachengeteka mudziyo maneja (SDM) kubva pakati. Iyo SDM inosarudza kuti ndeapi marudzi emapini ekugadzirisa ekushandisa, zvinoenderana neMSEL yako yekumisikidza.

Partial Reconfiguration Yekunze Configuration Controller Intel FPGA IPintel-750856-Agilex-FPGA-Development-Board-FIG-1 (2)

Partial Reconfiguration External Configuration Controller Parameter Settings

Parameter Value Tsanangudzo
Gonesa Busy Interface Enable or

Disable

 Inokutendera iwe Kugonesa kana Kudzima iyo Busy interface, iyo inomiririra chiratidzo kuratidza kuti PR kugadzirisa kuri kuitika panguva yekumisikidzwa kwekunze.

Default setting ndeye Disable.

Partial Reconfiguration External Configuration Controller Ports

Port Name Upamhi Direction Function
pr_request 1 Input Inoratidza kuti maitiro ePR agadzirira kutanga. Chiratidzo iconduit isingaenderani kune chero chiratidzo chewachi.
pr_error 2 Output Inoratidza kukanganisa kwekugadzirisa.:

• 2'b01—general PR kukanganisa

• 2'b11— bitstream kukanganisa

Aya masaini maconduits asingaenderane kune chero wachi sosi.
pr_done 1 Output Inoratidza kuti maitiro ePR apera. Chiratidzo iconduit isingaenderani kune chero chiratidzo chewachi.
kutanga_addr 1 Input Inotsanangura kero yekutanga yePR data muActive Serial Flash. Iwe unogonesa chiratidzo ichi nekusarudza chero Avalon®-ST or Active seri zve Gonesa Avalon-ST Pini kana Active seri Pini parameter. Chiratidzo iconduit isingaenderani kune chero chiratidzo chewachi.
reset 1 Input Active yakakwirira, synchronous reset chiratidzo.
kunze_clk 1 Output Wachi sosi inogadzira kubva kune yemukati oscillator.
busy 1 Output Iyo IP inomiririra chiratidzo ichi kuratidza PR data kufambiswa kuri kuitika. Iwe unogonesa chiratidzo ichi nekusarudza Enable zve Gonesa yakabatikana interface parameter.

Reference Design Zvinodiwa

Kushandisa iyi referensi dhizaini inoda zvinotevera:

  • Kuiswa kweIntel Quartus Prime Pro Edition vhezheni 22.3 nerutsigiro rweIntel Agilex mudziyo mhuri.
  • Kubatanidza kune Intel Agilex F-Series FPGA yekuvandudza bhodhi pabhenji.
  • Dhawunirodha yedhizaini exampinowanikwa munzvimbo inotevera: https://github.com/intel/fpga-partial-reconfig.

Kurodha dhizaini example:

  1. Dzvanya Clone kana dhawunirodha.
  2. Dzvanya Dhawunirodha ZIP. Unzip iyo fpga-partial-reconfig-master.zip file.
  3. Enda kune tutorials/agilex_external_pr_configuration subfolder kuti uwane referensi dhizaini.

Reference Design Walkthrough

Matanho anotevera anotsanangura kuitwa kwechikamu chekugadzirisa zvakare kuburikidza nepini yekumisikidza (yekunze muenzi) pane Intel Agilex F-Series FPGA yekuvandudza bhodhi:

  • Danho 1: Kutanga
  • Danho 2: Kugadzira Chikamu Chekugadzira
  • Danho 3: Kugovera Nzvimbo dzeKuisa uye Kufambisa Matunhu
  • Danho 4: Kuwedzera iyo Partial Reconfiguration Yekunze Configuration Controller IP
  • Danho 5: Kutsanangura Vanhu
  • Danho 6: Kugadzira Ongororo
  • Danho 7: Kugadzira iyo Base Revision
  • Danho 8: Kugadzirira PR Implementation Revisions
  • Danho 9: Kuronga Bhodhi

Danho 1: Kutanga
Kukopa referensi dhizaini files kunzvimbo yako yekushanda uye gadzira iyo blinking_led flat dhizaini:

  1. Gadzira dhairekitori munzvimbo yako yekushanda, agilex_pcie_devkit_blinking_led_pr.
  2. Kopa zvidzidzo zvakatorwa/agilex_pcie_devkit_blinking_led/flat sub-folder kudhairekitori, agilex_pcie_devkit_blinking_led_pr.
  3. MuIntel Quartus Prime Pro Edition software, tinya File ➤ Vhura Project uye sarudza blinking_led.qpf.
  4. Kuti utsanangure huwandu hwemagadzirirwo eflat, tinya Kugadzirisa ➤ Tanga ➤ Tanga Ongororo & Synthesis. Neimwe nzira, pamutsetse wekuraira, mhanyisa unotevera kuraira: quartus_syn blinking_led -c blinking_led

Kugadzira Chikamu Chekugadzira

Iwe unofanirwa kugadzira zvikamu zvekugadzira kune yega yega PR dunhu raunoda kugadzirisa zvishoma. Aya matanho anotevera anogadzira dhizaini yekugovera iyo u_blinking_led muenzaniso.

Kugadzira Zvikamu Zvikamuintel-750856-Agilex-FPGA-Development-Board-FIG-1 (3)

  1. Tinya-kurudyi u_blinking_led muenzaniso muProjekti Navigator uye tinya Dhizaini Partition ➤ Reconfigurable. Iyo dhizaini yekuparadzanisa icon inoonekwa padivi peimwe neimwe muenzaniso iyo yakaiswa sechikamu.
  2. Dzvanya Basa ➤ Dhizaini yeZvikamu Zvikamu. Iwindo rinoratidza zvikamu zvose zvekugadzira mupurojekiti.
  3. Rongedza zita rechikamu muDhizaini yeZvikamu Zvikamu nekudzvanya kaviri zita racho. Kune iyi referensi dhizaini, tumidza zita rechikamu kuti pr_partition
    • Cherechedza: Paunenge uchigadzira chikamu, iyo Intel Quartus Prime software inogadzira otomatiki zita rekuparadzanisa, zvichibva pane iyo muenzaniso zita uye hierarchy nzira. Iri zita rekutanga rekuparadzanisa rinogona kusiyana nemuenzaniso wega wega.
  4. Kuti utumire kunze iyo yakagadziridzwa static dunhu kubva ku base revision kuunganidzwa, tinya kaviri iyo yekupinda ye root_partition muPost Final Export. File column, uye nyora blinking_led_static. gdb.

Kutumira kunze Post Final Snapshot muDhizaini Partitions Windowintel-750856-Agilex-FPGA-Development-Board-FIG-1 (4)Ona kuti blinking_led.qsf ine mabasa anotevera, anoenderana neako anogadzirisika dhizaini partition:intel-750856-Agilex-FPGA-Development-Board-FIG-1 (5)

Related Information
"Gadzira Zvikamu Zvikamu" muIntel Quartus Prime Pro Edition Mushandisi Wekushandisa: Chikamu Reconfiguration

Kugovera Nzvimbo uye Yekutenderera Dunhu kune PR Chikamu
Kune yega yega yega yekudzokorora yaunogadzira, iyo PR dhizaini inoyerera inoisa inoenderana persona musimboti munharaunda yako yePR yekugovera. Kutsvaga uye kugovera iyo PR dunhu mune mudziyo floorplan kune yako base revision:

  1. Tinya-kurudyi u_blinking_led muenzaniso muProjekti Navigator wodzvanya Logic Lock Dunhu ➤ Gadzira New Logic Lock Dunhu. Dunhu rinoonekwa paLogic Lock Regions Window.
  2. Nzvimbo yako yekuisa inofanirwa kuvharira iyo blinking_led logic. Sarudza nzvimbo yekuisa nekutsvaga node muChip Planner. Tinya-kurudyi zita redunhu u_blinking_led muLogic Lock Matunhu Window uye tinya

Tsvaga Node ➤ Tsvaga muChip Planner. Nzvimbo u_blinking_led ine mavara-coded

Chip Planner Node Nzvimbo ye blinking_ledintel-750856-Agilex-FPGA-Development-Board-FIG-1 (6)

  1. Muiyo Logic Lock Matunhu hwindo, tsanangura nzvimbo yekuisa inorongedzerwa muOrigin column. Mabviro anoenderana nechepazasi-kuruboshwe kona yedunhu. For example, kuseta nzvimbo yekuisa ne (X1 Y1) inorongedzerwa se (163 4), tsanangura Mavambo se X163_Y4. Iyo Intel Quartus Prime software inoverengera otomatiki iyo (X2 Y2) ma-co-ordinate (kumusoro-kurudyi) yenzvimbo yekuisa, zvichienderana nehurefu nehupamhi hwaunotsanangura.
    • Cherechedza: Ichi chidzidzo chinoshandisa (X1 Y1) makongiresi - (163 4), uye hurefu nehupamhi hwemakumi maviri enzvimbo yekuiswa. Tsanangura chero kukosha kwenzvimbo yekuisa. Ita shuwa kuti dunhu rinovhara blinking_led logic.
  2. Gonesa iyo Yakachengetwa uye Core-chete sarudzo.
  3. Tinya kaviri sarudzo yeRouting Region. Iyo Logic Lock Routing Region Settings dialog box inooneka.
  4. Sarudza Yakagadziriswa nekuwedzera kweiyo Routing mhando. Kusarudza iyi sarudzo kunopa hurefu hwekuwedzera hwe2.
    • Cherechedza: Nzvimbo yekufambisa inofanira kunge yakakura kudarika nzvimbo yekuisa, kupa imwe shanduko yeFitter apo injini inofamba nevanhu vakasiyana.

Logic Lock Matunhu Windowintel-750856-Agilex-FPGA-Development-Board-FIG-1 (7)Ona kuti blinking_led.qsf ine mabasa anotevera, anoenderana nefloorplanning yako:intel-750856-Agilex-FPGA-Development-Board-FIG-1 (8)intel-750856-Agilex-FPGA-Development-Board-FIG-1 (9)

Related Information
"Floorplan iyo Partial Reconfiguration Dhizaini" muIntel Quartus Prime Pro Edition Mushandisi Wekushandisa: Chikamu Reconfiguration

Kuwedzera iyo Partial Reconfiguration Yekunze Configuration Controller Intel FPGA IP
Iyo Partial Reconfiguration Yekunze Configuration Controller Intel FPGA IP inopindirana neIntel Agilex PR control block kubata iyo bitstream sosi. Iwe unofanirwa kuwedzera iyi IP kune yako dhizaini kuti uite yekumisikidza kwekunze. Tevedza nhanho idzi kuti uwedzere Partial Reconfiguration External Configuration Controller
Intel FPGA IP kune purojekiti yako:

  1. Nyora Chikamu Reconfiguration muIP Catalog yekutsvaga nzvimbo (Zvishandiso ➤ IP Catalog).
  2. Tinya kaviri Chikamu Reconfiguration Yekunze Configuration Controller Intel FPGA IP.
  3. MuGadzira IP Variant dialog box, nyora external_host_pr_ip seyo File zita, wobva wadzvanya Gadzira. Iyo parameter editor inooneka.
  4. Kune Inogonesa yakabatikana interface parameter, sarudza Disable (iyo yakasarudzika marongero). Paunenge uchida kushandisa chiratidzo ichi, unogona kushandura marongero kuti Gonesa.

Gonesa Busy Interface Parameter muParameter Edhindaintel-750856-Agilex-FPGA-Development-Board-FIG-1 (10)

  1. Dzvanya File ➤ Sevha uye buda parameter mupepeti pasina kugadzira sisitimu. Iyo parameter mupepeti inogadzira iyo yekunze_host_pr_ip.ip IP musiyano file uye anowedzera file kune blinking_led project. AN 991: Partial Reconfiguration via Configuration Pins (External Host) Reference Design 750856 | 2022.11.14 AN 991:
    • Cherechedza:
    • a. Kana uri kukopa kunze_host_pr_ip.ip file kubva pr dhairekitori, gadzirisa nemaoko blinking_led.qsf file kuisa mutsara unotevera: set_global_assignment -zita IP_FILE pr_ip.ip
    • b. Isa iyo IP_FILE basa mushure meSDC_FILE assignments (blinking_led. dc) mu blinking_led.qsf yako file. Kurongeka uku kunovimbisa kumanikidzwa kwakakodzera kweiyo Partial Reconfiguration Controller IP musimboti.
    • Cherechedza: Kuti uone wachi, .sdc file yePR IP inofanira kutevera chero .sdc inogadzira wachi dzinoshandiswa neIP core. Iwe unofambisa iyi kurongeka nekuona kuti iyo .ip file yePR IP core inooneka after any .ip files kana .sdc fileyaunoshandisa kutsanangura wachi idzi mu .qsf file yeIntel Quartus Prime project revision yako. Kuti uwane rumwe ruzivo, tarisa kune Partial Reconfiguration IP Solutions User Guide.

Kuvandudza iyo yepamusoro-Level Dhizaini

Kuvandudza kumusoro.sv file ne PR_IP muenzaniso:

  1. Kuti uwedzere ekunze_host_pr_ip muenzaniso kune yepamusoro-level dhizaini, bvisa anotevera mabhuroko ekodhi kumusoro.sv file:intel-750856-Agilex-FPGA-Development-Board-FIG-1 (11)

Kutsanangura Vanhu
Iyi referensi dhizaini inotsanangura vatatu vakasiyana vanhu kune imwechete PR chikamu. Kutsanangura uye kusanganisira vanhu vari muprojekti yako:

  1. Gadzira matatu SystemVerilog files, blinking_led.sv, blinking_led_slow.sv, uye blinking_led_empty.sv mubhuku rako rekushanda revanhu vatatu.

Reference Design Personasintel-750856-Agilex-FPGA-Development-Board-FIG-1 (12) intel-750856-Agilex-FPGA-Development-Board-FIG-1 (13)

Cherechedza:

  • blinking_led.sv yatovepo sechikamu che files iwe unokopa kubva kufurati / sub-dhairekitori. Unogona kushandisa zvakare izvi file.
  • Kana iwe ukagadzira iyo SystemVerilog files kubva kuIntel Quartus Prime Text Mharidzo, dzima iyo Wedzera file kune yazvino purojekiti sarudzo, paunenge uchichengetedza iyo files.

Kugadzira Ongororo

Iyo PR dhizaini inoyerera inoshandisa iyo purojekiti yekudzokorora chimiro muIntel Quartus Prime software. Yako yekutanga dhizaini ndiyo dhizaini yekudzokorora, kwaunotsanangura iyo static dunhu miganhu uye matunhu anogadziriswa paFPGA. Kubva pakudzokororwa kwehwaro, iwe unogadzira kudzokorora kwakawanda. Aya ongororo ane akasiyana mashandisirwo ematunhu ePR. Nekudaro, ese maPR magadzirirwo ekuita anoshandisa yakafanana yepamusoro-level yekuisa uye nzira yekumisikidza kubva kune base revision. Kuti ugadzire dhizaini yePR, iwe unofanirwa kugadzira PR yekumisikidza kudzokorora kune yega munhu. Mukuwedzera, iwe unofanirwa kugovera mhando dzekudzokorora kune imwe neimwe yedzokorodzo. Mhando dzekudzokorora dziripo ndeidzi:

  • Chikamu Reconfiguration - Base
  • Partial Reconfiguration - Persona Implementation

Tafura inotevera inoronga zita rekudzokorora uye rudzi rwekudzokorora kune yega yega yedzokororo:

Mazita ekudzokorora uye Marudzi

Zita rekudzokorora Revision Type
blinking_led.qsf Chikamu Reconfiguration - Base
blinking_led_default.qsf Partial Reconfiguration - Persona Implementation
blinking_led_slow.qsf Partial Reconfiguration - Persona Implementation
blinking_led_empty.qsf Partial Reconfiguration - Persona Implementation

Kuisa iyo Base Revision Type

  1. Dzvanya Chirongwa ➤ Ongororo.
  2. MuZita rekudzokorora, sarudza blinking_led revision, wobva wadzvanya Set Yazvino.
  3. Dzvanya Shandisa. Iyo blinking_led revision inoratidza seyazvino kudzokorora.
  4. Kuseta Rudzi rweKudzokorodza kuti blinking_led, tinya Mabasa ➤ Zvirongwa ➤ Zvakawanda.
  5. Kune Revision Type, sarudza Partial Reconfiguration - Base, wobva wadzvanya OK.
  6. Ona kuti blinking_led.qsf yava kuita rinotevera basa: ##blinking_led.qsf set_global_assignment -zita REVISION_TYPE PR_BASE

Kugadzira Implementation Revisions

  1. Kuti uvhure Revisions dialog box, tinya Chirongwa ➤ Revisions.
  2. Kuti ugadzire ongororo itsva, tinya kaviri < >.
  3. Muzita rekudzokorora, tsanangura blinking_led_default uye sarudza blinking_led yeKubva pakudzokorora.
  4. Kune iyo Revision mhando, sarudza Partial Reconfiguration - PersonaImplementation.

Kugadzira Ongororointel-750856-Agilex-FPGA-Development-Board-FIG-1 (14)

  1. Saizvozvo, isa iyo Revision mhando ye blinking_led_slow uye blinking_led_empty revisions.
  2. Ona kuti imwe neimwe .qsf file ikozvino ine basa rinotevera: set_global_assignment -name REVISION_TYPE PR_IMPL set_instance_assignment -zita ENTITY_REBINDING \ place_holder -to u_blinking_led uko, place_holder ndiro zita rechimwe chikamu chekudzokorora kuchangobva kugadzirwa kwePR.

Project Revisionsintel-750856-Agilex-FPGA-Development-Board-FIG-1 (16)

Kugadzira iyo Base Revision

  1. Kuti ugadzire kudzokorora kwekutanga, tinya Kugadzirisa ➤ Tanga Kuunganidza. Neimwe nzira, iwo unotevera murairo unounganidza iyo base revision: quartus_sh -flow compile blinking_led -c blinking_led
  2. Ongorora bitstream fileizvo zvinogadzira mune zvakabuda_files directory.

Yakagadzirwa Files

Zita Type Tsanangudzo
blinking_led.sof Base programming file Inoshandiswa kune yakazara-chip base configuration
blinking_led.pr_partition.rbf PR bitstream file for base persona Inoshandiswa pachikamu chekugadzirisazve base persona.
blinking_led_static.qdb .qdb database file Yakapedzwa database file inoshandiswa kuunza kunze kweiyo static region.

Related Information

  • "Floorplan iyo Partial Reconfiguration Dhizaini" muIntel Quartus Prime Pro Edition Mushandisi Wekushandisa: Chikamu Reconfiguration
  • "Kushandisa Floorplan Constrainmentally" muIntel Quartus Prime Pro Edition Mushandisi Wekushandisa: Chikamu Reconfiguration

Kugadzirira PR Implementation Revisions
Iwe unofanirwa kugadzirira iyo PR yekumisikidza gadziriso usati wakwanisa kuunganidza uye kugadzira iyo PR bitstream yekuronga mudziyo. Iyi setup inosanganisira kuwedzera iyo static region .qdb file sekwakabva file pakudzokorora kwega kwega kwekuita. Uye zvakare, iwe unofanirwa kutsanangura iyo inoenderana chikamu chePR dunhu.

  1. Kuseta kudzokorora kwazvino, tinya Project ➤ Revisions, sarudza blinking_led_default sezita reRevision, wobva wadzvanya Set Current.
  2. Kuti uone kunobva kwairi kwekudzokorora kwega kwega kwekuita, tinya Chirongwa ➤Wedzera/Bvisa Files muProjekti. The blinking_led.sv file inooneka mu file list.

FilesPageintel-750856-Agilex-FPGA-Development-Board-FIG-1 (17)

  1. Dzokorora nhanho 1 kusvika 2 kuti uone imwe yekumisikidza ongororo sosi files:
Implementation Revision Zita Source File
blinking_led_default blinking_led.sv
blinking_led_isina blinking_led_empty.sv
blinking_led_slow blinking_led_slow.sv
  1. Kuongorora .qdb file yakabatana nechikamu chemidzi, tinya Mabasa ➤ Dhizaini yeZvikamu Zvikamu. Simbisa kuti Partition Database File inotsanangura blinking_led_static.qdb file, kana kudzvanya kaviri iyo Partition Database File cell kutsanangura izvi file. Neimwe nzira, murairo unotevera unopa izvi file: set_instance_assignment -zita QDB_FILE_PARTITION \ blinking_led_static.qdb -to |
  2. MuSero Re-binding Sero, tsanangura zita rechimwe chikamu chePR chikamu chega chega chaunoshandura mukudzokorora kwekuita. Kune iyo blinking_led_default yekumisikidza kudzokorora, zita remubatanidzwa riri blinking_led. Muchidzidzo ichi, unonyora pamusoro peiyo u_blinking_led muenzaniso kubva kubhesi revhezheni inounganidzwa neiyo itsva blinking_led entity.

Cherechedza: A placeholder entity rebinding assignment inowedzerwa kuongororo yekuitwa otomatiki. Nekudaro, iwe unofanirwa kushandura iyo default entity zita mukupihwa kune rakakodzera zita resangano redhizaini yako.

Implementation Revision Zita Entity Re-binding
blinking_led_default blinking_led
blinking_led_slow blinking_led_slow
blinking_led_isina blinking_led_isina

Entity Rebindingintel-750856-Agilex-FPGA-Development-Board-FIG-1 (18)

  1. Kubatanidza dhizaini, tinya Kugadzirisa ➤ Tanga Kuunganidza. Neimwe nzira, murairo unotevera unobatanidza chirongwa ichi: quartus_sh -flow compile blinking_led -c blinking_led_default
  2. Dzokorora matanho ari pamusoro kugadzirira blinking_led_slow uye blinking_led_empty revisions: quartus_sh -flow compile blinking_led -c blinking_led_slow quartus_sh -flow compile blinking_led -c blinking_led_empt

Cherechedza: Iwe unogona kutsanangura chero maFitter chaiwo marongero aunoda kunyorera panguva yePR kuita kuunganidzwa. Fitter chaiyo marongero anokanganisa chete kukwana kweiyo persona, pasina kukanganisa iyo inotengeswa kunze static dunhu.

Kuronga Bhodhi
Ichi chidzidzo chinoshandisa Intel Agilex F-Series FPGA yekuvandudza bhodhi pabhenji, kunze kwePCIe * slot mumushini wako wekutambira. Usati waronga bhodhi, ita shuwa kuti wapedza nhanho dzinotevera:

  1. Batanidza simba rekupa kune Intel Agilex F-Series FPGA yekuvandudza bhodhi.
  2. Batanidza iyo Intel FPGA Dhawunirodha Cable pakati pePC yako USB port neIntel FPGA Dhawunirodha Cable chiteshi pabhodhi rekuvandudza.

Kumhanyisa dhizaini paIntel Agilex F-Series FPGA yekuvandudza bhodhi:

  1. Vhura iyo Intel Quartus Prime software uye tinya Zvishandiso ➤ Chirongwa.
  2. MuPurogiramu, tinya Hardware Setup uye sarudza USB-Blaster.
  3. Dzvanya Auto Detect uye sarudza mudziyo, AGFB014R24AR0.
  4. Dzvanya OK. Iyo Intel Quartus Prime software inoona uye inogadziridza iyo Programmer nemidziyo mitatu yeFPGA pabhodhi.
  5. Sarudza iyo AGFB014R24AR0 mudziyo, tinya Shandura File uye takura blinking_led_default.sof file.
  6. Vhura Chirongwa/Gadzirisa blinking_led_default.sof file.
  7. Dzvanya Tanga uye mirira kuti bhari yekufambira mberi isvike 100%.
  8. Tarisa maLED ari pabhodhi achibwaira pamhepo yakafanana neyekutanga flat dhizaini.
  9. Kuronga nharaunda yePR chete, tinya kurudyi blinking_led_default.sof file muPurogiramu uye tinya Wedzera PR Chirongwa File.
  10. Sarudza blinking_led_slow.pr_partition.rbf file.
  11. Dzima Chirongwa/Gadzirisa blinking_led_default.sof file.
  12. Vhura Chirongwa/Gadzirisa blinking_led_slow.pr_partition.rbf file wobva wadzvanya Start. Pabhodhi, tarisa LED[0] uye LED[1] ichiramba ichibwaira. Kana bhara rekufambira mberi rasvika 100%, LED[2] uye LED[3] inopenya zvishoma.
  13. Kuronga patsva nharaunda yePR, tinya-kurudyi pakanzi .rbf file muPurogiramu uye tinya Shandura PR Kuronga File.
  14. Sarudza iyo .rbf files kune vamwe vanhu vaviri kuti vaone maitiro ari pabhodhi. Kurodha blinking_led_default.rbf file kunoita kuti ma LED abwaire pane imwe frequency, uye kurodha blinking_led_empty.rbf file inoita kuti ma LED arambe akabatidza.

Kuronga iyo Intel Agilex F-Series FPGA Development Boardintel-750856-Agilex-FPGA-Development-Board-FIG-1 (19)Hardware Testing Flow

Aya anotevera anotevedzana anotsanangura referensi dhizaini yekuyedza kuyerera.
Intel Agilex Chishandiso Chekunze Host Hardware Setupintel-750856-Agilex-FPGA-Development-Board-FIG-1 (20)

Chirongwa Mubatsiri FPGA (Yekunze Mugamuchiri)
Kutevedzana kunotevera kunotsanangura hurongwa hwemubatsiri FPGA inoshanda sePR process yekunze host:

  1. Rondedzera iyo Avalon yekushambadzira interface seti inoenderana neiyo modhi yaunosarudza (x8, x16, kana x32).
  2. Tanga chikuva nekugadzira mubatsiri FPGA uchishandisa Intel Quartus Prime Programmer uye yakabatana yekumisikidza tambo.
  3. Uchishandisa mubatsiri FPGA, verenga CONF_DONE uye AVST_READY masiginecha. CONF_DONE inofanira kunge iri 0, AVST_READY inofanira kunge iri 1. Zvinonzwisisika zviri pamusoro papini iyi zvinoratidza kuti SDM yagadzirira kugamuchira data kubva kumunhu ari kunze. Izvi zvinobuda chikamu cheSDM I/O.

Cherechedza: Pini yeCONF_DONE inosaina mugamuchiri wekunze kuti kutamisa bitstream kwabudirira. Shandisa aya masaini chete kutarisa yakazara chip yekumisikidza maitiro. Tarisa kune Intel Agilex Configuration User Guide kuti uwane rumwe ruzivo pane iyi pini.

Ronga iyo DUT FPGA ine Yakazara Chip SOF kuburikidza neExternal Host Iyi inoteedzana inotsanangura kuronga iyo DUT FPGA ine yakazara chip SRAM Object. File (.sof) uchishandisa iyo inotambira Avalon yekufambisa interface:

  1. Nyora yakazara chip bitstream muDDR4 yekunze ndangariro yemubatsiri FPGA (yekunze muenzi).
  2. Gadzirisa DUT FPGA ine chipu chakazara .sof uchishandisa Avalon streaming interface (x8, x16, x32).
  3. Verenga iyo mamiriro DUT FPGA masiginecha ekugadzirisa. CONF_DONE inofanira kuva 1, AVST_READY inofanira kuva 0.

Nguva Inotsanangurwa: Chikamu Reconfiguration Yekunze Controller Intel FPGA IPintel-750856-Agilex-FPGA-Development-Board-FIG-1 (21)

Ronga iyo DUT FPGA ine Yekutanga Persona kuburikidza Nekunze Host

  1. Isa iyo yechando pane inotarirwa PR dunhu muDUT FPGA.
  2. Uchishandisa iyo Intel Quartus Prime System Console, taura pr_request kuti utange iyo chikamu chekugadzirisa. AVST_READY inofanira kunge iri 1.
  3. Nyora yekutanga PR persona bitstream muDDR4 yekunze ndangariro yemubatsiri FPGA (yekunze muenzi).
  4. Uchishandisa Avalon yekushambadzira interface (x8, x16, x32), gadzirisa iyo DUT FPGA neyekutanga persona bitstream.
  5. Kuti utarise mamiriro ePR, tinya Zvishandiso ➤ System Console kuvhura System Console. MuSystem Console, tarisa mamiriro ePR:
    • pr_error is 2-reconfiguration in process.
    • pr_error ndeye 3-kugadzirisazve kwapera.
  6. Nyorera unfreeze paPR dunhu muDUT FPGA.

Cherechedza: Kana kukanganisa kukaitika panguva yePR, sekutadza kuongorora shanduro kana kutarisa mvumo, kushanda kwePR kunopera.

Related Information

  • Intel Agilex Configuration User Guide
  • Intel Quartus Prime Pro Edition Mushandisi Wekushandisa: Debug Zvishandiso

Gwaro Revisheni Nhoroondo yeAN 991: Chikamu Reconfiguration kuburikidza neKugadzirisa Pini (Yekunze Host) Reference Dhizaini yeIntel Agilex F-Series FPGA Development Board.

Document Version Intel Quartus Prime Version Kuchinja
2022.11.14 22.3 • Kusunungurwa kwekutanga.

AN 991: Chikamu Kugadziridzwazve kuburikidza neKugadzirisa Pini (Yekunze Host) Reference Dhizaini: yeIntel Agilex F-Series FPGA Development Board.

Mhinduro kuMabvunzi epamusoro:

  • Q Chii chinonzi PR kuburikidza nepini yekumisikidza?
  • A Yekunze Host Configuration pane peji 3
  • Q Chii chandinoda kune iyi referensi dhizaini?
  • A Reference Design Zvinodiwa pane peji 6
  • Q Ndingawane kupi referensi dhizaini?
  • A Reference Design Zvinodiwa pane peji 6
  • Q Ndinoita sei PR kuburikidza nekumisikidzwa kwekunze?
  • A Reference Design Walkthrough papeji 6
  • Q Chii chinonzi PR persona?
  • A Kutsanangura Vanhu vari papeji 11
  • Q Ndinoronga sei bhodhi?
  • A Ronga Bhodhi papeji 17
  • Q Ndedzipi PR dzinozivikanwa nyaya uye zvisingakwanisi?
  • A Intel FPGA Support Forums: PR
  • Q Iwe une kudzidziswa nezvePR?
  • A Intel FPGA Unyanzvi Kudzidzisa Catalog

Online Version Send Feedback

  • ID: 750856
  • Shanduro: 2022.11.14

Zvinyorwa / Zvishandiso

Intel 750856 Agilex FPGA Development Board [pdf] Bhuku reMushandisi
750856, 750857, 750856 Agilex FPGA Development Board, Agilex FPGA Development Board, FPGA Development Board, Development Board, Board

References

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