Cov ntsiab lus zais
1 Intel 750856 Agilex FPGA Development Board
2 Cov ntaub ntawv khoom
3 Cov lus qhia siv khoom
4 Reference Design Overview
5 Sab nraud Host Configuration
6 Reference Design Requirements
7 Reference Design Walkthrough
8 Tsim ib qho kev faib faib
9 Tsim cov kev hloov kho
10 Hloov kho npe thiab hom
11 Programming Intel Agilex F-Series FPGA Development BoardHardware Test Flow
12 Cov ntaub ntawv / Cov ntaub ntawv
12.1 Cov ntaub ntawv

Intel-LOGO

Intel 750856 Agilex FPGA Development Board

intel-750856-Agilex-FPGA-Development-Board-PRODUCT

Cov ntaub ntawv khoom

Cov qauv siv no yog rau Intel Agilex F-Series FPGA Development Board. Nws siv Ib Feem Kev Txhim Kho Sab Nraud Sab Nraud Configuration Controller Intel FPGA IP thiab muaj thaj tsam PR yooj yim. Intel Agilex Device External Host Hardware Setup muaj ib qho khoom siv sab nraud (Helper FPGA), DUT FPGA, thiab koj tus tswv tsev tsim sab nraud. Tus tswv tsev tsim nyob rau hauv cov khoom siv sab nraud yog lub luag haujlwm rau hosting cov txheej txheem PR. PR pins yog siv los txuas ob qho khoom siv thiab tuaj yeem ua tau txhua tus neeg siv I/Os.

Cov lus qhia siv khoom

Sab nraud Host Configuration

Txhawm rau ua tus tswv tsev sab nraud, ua raws li cov kauj ruam no:

  1. Tsim ib tus tswv tsev tsim hauv ib qho khoom siv sab nraud los tuav cov txheej txheem PR.
  2. Txuas tus PR pins los ntawm cov cuab yeej sab nraud mus rau Ib Feem Kev Txhim Kho Sab Nraud Sab Nraud Configuration Controller Intel FPGA IP hauv DUT FPGA.
  3. kwj teeb tsa cov ntaub ntawv los ntawm tus tswv tsev tsim rau Intel Agilex Avalon streaming interface pins uas sib haum rau PR kev tuav tes teeb liab los ntawm IP.

Ib nrab Reconfiguration ntawm Configuration Pins Operation

Cov kab hauv qab no piav qhia txog kev ua haujlwm ntawm ib nrab reconfiguration ntawm configuration pins:

  1. Qhia rau tus pr_request tus pin txuas nrog Ib Feem Reconfiguration Sab Nraud Configuration Controller Intel FPGA IP.
  2. IP lees paub lub teeb liab tsis khoom los qhia tias cov txheej txheem PR tab tom ua tiav (yeem).
  3. Yog tias cov txheej txheem teeb tsa tau npaj txhij rau kev ua haujlwm PR, avst_ready tus pin tau lees paub, qhia tias nws npaj tau txais cov ntaub ntawv.
  4. Kwj PR cov ntaub ntawv teeb tsa hla avst_data pins thiab avst_valid tus pin, ua raws li Avalon streaming specification rau cov ntaub ntawv hloov mus nrog backpressure.
  5. Streaming nres thaum avst_ready tus pin yog de-asserted.
  6. De-assert tus avst_ready tus pin los qhia tias tsis muaj cov ntaub ntawv ntxiv rau kev ua haujlwm PR.
  7. Lub Ib Feem Reconfiguration Sab Nraud Configuration Controller Intel FPGA IP de-asserts lub teeb liab tsis khoom los qhia txog qhov kawg ntawm cov txheej txheem (yeem).

Ib nrab Reconfiguration ntawm Configuration Pins (External Host) Reference Design

Daim ntawv thov no qhia txog kev teeb tsa ib nrab ntawm kev teeb tsa tus pins (tus tswv sab nraud) ntawm Intel® Agilex® F-Series FPGA kev txhim kho pawg thawj coj.

Reference Design Overview

Ib feem ntawm kev teeb tsa (PR) feature tso cai rau koj los kho ib feem ntawm FPGA dynamically, thaum tus qauv FPGA ntxiv tseem ua haujlwm. Koj tuaj yeem tsim ntau tus neeg rau ib cheeb tsam tshwj xeeb hauv koj tus qauv tsim uas tsis cuam tshuam rau kev ua haujlwm hauv cheeb tsam sab nraud. Cov txheej txheem no muaj txiaj ntsig zoo hauv cov kab ke uas muaj ntau lub sijhawm ua haujlwm-sib qhia tib yam FPGA cov khoom siv. Qhov tam sim no version ntawm Intel Quartus® Prime Pro Edition software qhia txog qhov tshiab thiab yooj yim muab tso ua ke ntws rau ib nrab reconfiguration. Qhov kev siv ntawm Intel Agilex no siv cov Kev Txhim Kho Ib Ntus Sab Nraud Configuration Controller Intel FPGA IP thiab muaj thaj tsam PR yooj yim.

Intel Agilex Ntaus Sab Nraud Sab Nraud Sab Nraud Hardware Teebintel-750856-Agilex-FPGA-Development-Board-FIG-1 (1)

Sab nraud Host Configuration

Hauv kev teeb tsa tus tswv tsev sab nraud, koj yuav tsum xub tsim tus tswv tsev tsim hauv ib qho khoom siv sab nraud los tuav cov txheej txheem PR, raws li Intel Agilex Device Sab Nraud Host Hardware Setup qhia. Tus tswv tsev tsim kwj cov ntaub ntawv teeb tsa rau Intel Agilex Avalon streaming interface pins uas sib haum rau PR handshaking signals uas los ntawm Ib Feem Kev Txhim Kho Sab Nraud Sab Nraud Kev Tswj Xyuas Intel FPGA IP. PR pins uas koj siv los txuas ob lub cuab yeej tuaj yeem yog cov neeg siv I/Os muaj.

Cov kab ke hauv qab no piav qhia txog qhov kev teeb tsa ib nrab ntawm kev teeb tsa tus pins ua haujlwm:

  1. Ua ntej tshaj tawm tus pr_request tus pin uas txuas nrog Ib Feem Kev Txhim Kho Sab Nraud Sab Nraud Configuration Controller Intel FPGA IP.
  2. IP lees paub lub teeb liab tsis khoom los qhia tias cov txheej txheem PR tab tom ua tiav (yeem).
  3. Yog hais tias lub configuration system npaj txhij mus rau ib tug PR lag luam, tus avst_ready tus pin yog asserted qhia tias nws yog npaj txhij los txais cov ntaub ntawv.
  4. Pib streaming PR configuration cov ntaub ntawv hla avst_data pins thiab avst_valid tus pin, thaum saib Avalon streaming specification rau cov ntaub ntawv hloov nrog backpressure.
  5. Streaming nres thaum twg avst_ready tus pin yog de-asserted.
  6. Tom qab streaming tag nrho cov ntaub ntawv teeb tsa, avst_ready tus pin yog de-asserted los qhia tias tsis muaj ntaub ntawv ntxiv rau kev ua haujlwm PR.
  7. Lub Ib Feem Reconfiguration Sab Nraud Configuration Controller Intel FPGA IP khoom qab zib rau lub teeb liab tsis khoom los qhia txog qhov kawg ntawm cov txheej txheem (yeem).
  8. Koj tuaj yeem tshawb xyuas pr_done thiab pr_error pins kom paub meej tias kev ua haujlwm PR ua tiav tiav. Yog hais tias qhov yuam kev tshwm sim, xws li tsis ua hauj lwm nyob rau hauv version checking thiab kev tso cai kuaj, PR lag luam yuav xaus.

Cov ntaub ntawv ntsig txog

  • Intel Agilex F-Series FPGA Development Kit Web Nplooj
  • Intel Agilex F-Series FPGA Cov Khoom Siv Txhim Kho Cov Neeg Siv
  • Intel Quartus Prime Pro Tsab Ntawv Qhia Tus Neeg Siv: Ib Feem Kho Dua Tshiab

Ib nrab Reconfiguration Sab Nraud Configuration Controller Intel FPGA IP
Ib Ntu Reconfiguration Sab Nraud Configuration Controller yuav tsum siv cov pins teeb tsa los tso PR cov ntaub ntawv rau kev ua haujlwm PR. Koj yuav tsum tau txuas tag nrho cov chaw nres nkoj saum toj kawg nkaus ntawm Ib Feem Kev Txhim Kho Sab Nraud Sab Nraud Configuration Controller Intel FPGA IP rau pr_request tus pin kom tso cai rau kev tuav tes ntawm tus tswv tsev nrog tus tswj hwm kev ruaj ntseg (SDM) los ntawm cov tub ntxhais. SDM txiav txim siab seb hom kev teeb tsa tus pins siv, raws li koj qhov MSEL teeb tsa.

Ib nrab Reconfiguration Sab Nraud Configuration Controller Intel FPGA IPintel-750856-Agilex-FPGA-Development-Board-FIG-1 (2)

Ib Feem Reconfiguration Sab Nraud Configuration Controller Parameter Chaw

Parameter Tus nqi Kev piav qhia
Pab kom Busy Interface Pab or

Disable

 Tso cai rau koj los pab lossis Disable lub Busy interface, uas lees paub lub teeb liab qhia tias kev ua haujlwm PR tau ua tiav thaum lub sijhawm teeb tsa sab nraud.

Default setting yog Disable.

Ib nrab Reconfiguration Sab Nraud Configuration Controller Ports

Chaw nres nkoj npe Dav Kev taw qhia Muaj nuj nqi
pr_ thov 1 Tswv yim Qhia tias txoj kev PR yog npaj txhij pib. Lub teeb liab yog ib tug conduit tsis synchronous rau tej moos teeb liab.
pr_ yuam kev 2 Tso zis Qhia txog qhov yuam kev ib nrab ntawm kev teeb tsa .:

• 2'b01—kev ua yuam kev PR

• 2'b11—incompatible bitstream yuam kev

Cov teeb liab no yog cov conduits tsis synchronous rau txhua lub moos.
pr_ua 1 Tso zis Qhia tias cov txheej txheem PR tiav lawm. Lub teeb liab yog ib tug conduit tsis synchronous rau tej moos teeb liab.
start_addr 1 Tswv yim Qhia qhov chaw pib ntawm PR cov ntaub ntawv hauv Active Serial Flash. Koj qhib qhov teeb liab no los ntawm kev xaiv ib qho Avalon®-ST or Active Serial rau cov Qhib Avalon-ST Pins lossis Active Serial Pins parameter. Lub teeb liab yog ib tug conduit tsis synchronous rau tej moos teeb liab.
rov pib dua 1 Tswv yim Active siab, synchronous pib dua teeb liab.
tawm_clk 1 Tso zis Lub moos qhov chaw uas tsim los ntawm lub oscillator sab hauv.
tsis khoom 1 Tso zis Tus IP lees paub qhov teeb liab no los qhia PR cov ntaub ntawv hloov mus rau hauv kev kawm. Koj qhib qhov teeb liab no los ntawm kev xaiv Pab rau cov Pab kom tibneeg hu tauj coob interface parameter.

Reference Design Requirements

Kev siv tus qauv siv no yuav tsum muaj cov hauv qab no:

  • Kev teeb tsa ntawm Intel Quartus Prime Pro Edition version 22.3 nrog kev txhawb nqa rau tsev neeg Intel Agilex.
  • Kev sib txuas rau Intel Agilex F-Series FPGA kev txhim kho pawg thawj coj ntawm lub rooj ntev zaum.
  • Download tau tus tsim example muaj nyob rau hauv qhov chaw hauv qab no: https://github.com/intel/fpga-partial-reconfig.

Mus download tau tus tsim example:

  1. Nyem Clone los yog download tau.
  2. Nyem Download ZIP. Unzip lub fpga-partial-reconfig-master.zip file.
  3. Nkag mus rau cov ntawv qhia / agilex_external_pr_configuration subfolder kom nkag mus rau cov qauv siv.

Reference Design Walkthrough

Cov kauj ruam hauv qab no piav qhia txog qhov kev siv ntawm ib nrab reconfiguration ntawm configuration pins (sab nraud party) ntawm Intel Agilex F-Series FPGA txoj kev loj hlob board:

  • Kauj ruam 1: Pib
  • Kauj ruam 2: Tsim ib qho kev faib faib
  • Kauj ruam 3: Allocating Placement thiab Routing Regions
  • Kauj ruam 4: Ntxiv ib nrab Reconfiguration External Configuration Controller IP
  • Kauj ruam 5: Defining Personas
  • Kauj ruam 6: Tsim cov kev hloov kho
  • Kauj ruam 7: Compiling the Base Revision
  • Kauj ruam 8: Npaj PR Kev Hloov Kho Kev Ua Haujlwm
  • Kauj ruam 9: Programming lub Rooj Tswjhwm Saib

Kauj ruam 1: Pib pib
Yuav luam cov qauv siv files rau koj qhov chaw ua haujlwm thiab suav nrog blinking_led flat design:

  1. Tsim cov npe hauv koj qhov chaw ua haujlwm, agilex_pcie_devkit_blinking_led_pr.
  2. Luam the downloaded tutorials/agilex_pcie_devkit_blinking_led/flat sub-folder to the directory, agilex_pcie_devkit_blinking_led_pr.
  3. Hauv Intel Quartus Prime Pro Edition software, nyem File ➤ Qhib Project thiab xaiv blinking_led.qpf.
  4. Txhawm rau nthuav dav lub hierarchy ntawm lub tiaj tus tsim, nyem Ua Haujlwm ➤ Pib ➤ Pib Kev Tshawb Fawb & Synthesis. Xwb, ntawm kab hais kom ua, khiav cov lus txib hauv qab no: quartus_syn blinking_led -c blinking_led

Tsim ib qho kev faib faib

Koj yuav tsum tsim cov qauv tsim rau txhua cheeb tsam PR uas koj xav kom rov kho dua ib nrab. Cov kauj ruam hauv qab no tsim ib qho kev faib tawm rau qhov piv txwv u_blinking_led.

Tsim cov qauv tsim partitionsintel-750856-Agilex-FPGA-Development-Board-FIG-1 (3)

  1. Txoj cai-nias lub u_blinking_led piv txwv nyob rau hauv qhov Project Navigator thiab nyem Tsim Partition ➤ Reconfigurable. Ib tug tsim muab faib icon tshwm nyob ib sab ntawm txhua qhov piv txwv uas yog teem raws li ib tug muab faib.
  2. Nyem Assignments ➤ Design Partitions Window. Lub qhov rais qhia tag nrho cov tsim partitions hauv qhov project.
  3. Kho lub npe muab faib nyob rau hauv Tsim Partitions Qhov rai los ntawm ob-nias lub npe. Rau qhov qauv siv no, hloov lub npe muab faib rau pr_partition
    • Nco tseg: Thaum koj tsim ib qho kev faib tawm, Intel Quartus Prime software cia li tsim lub npe muab faib, raws li lub npe piv txwv thiab txoj hauv kev hierarchy. Lub npe muab faib no tuaj yeem sib txawv nrog txhua qhov piv txwv.
  4. Txhawm rau xa tawm qhov kawg ntawm thaj av zoo li qub los ntawm lub hauv paus kev kho dua sau ua ke, nyem ob npaug rau kev nkag rau root_partition hauv Post kawg Export File kem, thiab ntaus blinking_led_static. gdb ib.

Exporting Post kawg Snapshot nyob rau hauv Tsim Partitions Qhov raiintel-750856-Agilex-FPGA-Development-Board-FIG-1 (4)Xyuas kom tseeb tias lub blinking_led.qsf muaj cov haujlwm hauv qab no, sib xws rau koj qhov kev faib tawm tsim kho dua tshiab:intel-750856-Agilex-FPGA-Development-Board-FIG-1 (5)

Cov ntaub ntawv ntsig txog
"Tsim Tsim Partitions" nyob rau hauv Intel Quartus Prime Pro Tsab Ntawv Qhia Tus Neeg Siv: Ib Feem Reconfiguration

Kev faib qhov chaw thiab Routing Region rau PR Partition
Rau txhua qhov kev hloov kho hauv paus koj tsim, PR tsim ntws tso cov neeg sib raug zoo hauv koj cheeb tsam PR faib. Txhawm rau nrhiav thiab muab PR cheeb tsam hauv cov phiaj xwm hauv pem teb rau koj qhov kev hloov kho hauv paus:

  1. Txoj cai-nias ntawm u_blinking_led piv txwv hauv Project Navigator thiab nyem Logic Lock Region ➤ Tsim Logic Lock Region tshiab. Cov cheeb tsam tshwm nyob rau ntawm Logic Lock Regions Qhov rai.
  2. Koj qhov chaw tso chaw yuav tsum nyob ze lub blinking_led logic. Xaiv thaj chaw tso kawm los ntawm kev nrhiav cov node hauv Chip Planner. Txoj cai-nias lub npe thaj tsam u_blinking_led hauv Logic Lock Regions Qhov rai thiab nyem

Nrhiav Node ➤ Nrhiav hauv Chip Planner. Lub cheeb tsam u_blinking_led yog xim-coded

Chip Planner Node Qhov chaw rau blinking_ledintel-750856-Agilex-FPGA-Development-Board-FIG-1 (6)

  1. Nyob rau hauv Logic Lock Regions qhov rais, qhia qhov chaw muab kev koom tes hauv cheeb tsam hauv kab hauv keeb kwm. Lub hauv paus chiv keeb sib raug rau lub kaum sab laug sab laug ntawm thaj av. Rau example, los teeb tsa thaj chaw tso kawm nrog (X1 Y1) kev sib koom ua ke raws li (163 4), qhia txog Keeb Kwm li X163_Y4. Intel Quartus Prime software cia li suav cov (X2 Y2) kev sib koom ua ke (sab saum toj-txoj cai) rau thaj chaw tso kawm, raws li qhov siab thiab dav koj teev.
    • Nco tseg: Qhov kev qhia no siv (X1 Y1) kev sib koom ua ke - (163 4), thiab qhov siab thiab dav ntawm 20 rau thaj tsam chaw. Txhais txhua tus nqi rau qhov chaw tso kawm. Xyuas kom meej tias cheeb tsam npog qhov blinking_led logic.
  2. Qhib cov kev xaiv Reserved thiab Core-Tsuas.
  3. Ob-nias qhov kev xaiv Routing Region. Lub Logic Lock Routing Region Settings dialog box tshwm.
  4. Xaiv Tsau nrog nthuav dav rau hom Routing. Xaiv qhov kev xaiv no cia li muab qhov nthuav dav ntawm 2.
    • Nco tseg: Lub cheeb tsam routing yuav tsum loj dua qhov chaw tso chaw, muab kev yooj yim ntxiv rau Fitter thaum lub cav khiav cov neeg sib txawv.

Logic Lock Regions Qhov raiintel-750856-Agilex-FPGA-Development-Board-FIG-1 (7)Xyuas kom tseeb tias blinking_led.qsf muaj cov haujlwm hauv qab no, sib xws rau koj qhov kev npaj hauv pem teb:intel-750856-Agilex-FPGA-Development-Board-FIG-1 (8)intel-750856-Agilex-FPGA-Development-Board-FIG-1 (9)

Cov ntaub ntawv ntsig txog
"Floorplan lub Ib Nrab Reconfiguration Design" hauv Intel Quartus Prime Pro Tsab Ntawv Qhia Tus Neeg Siv: Ib Feem Reconfiguration

Ntxiv qhov Ib Feem Kev Txhim Kho Sab Nraud Configuration Controller Intel FPGA IP
Lub Ib Feem Reconfiguration Sab Nraud Configuration Controller Intel FPGA IP interfaces nrog Intel Agilex PR tswj thaiv los tswj qhov bitstream. Koj yuav tsum ntxiv tus IP no rau koj tus qauv tsim los siv rau kev teeb tsa sab nraud. Ua raws li cov kauj ruam no txhawm rau ntxiv Ib Feem Kev Txhim Kho Sab Nraud Configuration Controller
Intel FPGA IP rau koj qhov project:

  1. Ntaus ib feem Reconfiguration nyob rau hauv lub IP Catalog nrhiav teb (Too ➤ IP Catalog).
  2. Muab ob npaug rau-nias Ib Ntu Reconfiguration Sab Nraud Configuration Controller Intel FPGA IP.
  3. Hauv Tsim IP Variant dialog box, ntaus external_host_pr_ip raws li File npe, thiab tom qab ntawd nyem Tsim. Cov parameter editor tshwm.
  4. Rau lub Enable tibneeg hu tauj coob interface parameter, xaiv Disable (lub neej ntawd chaw). Thaum koj xav siv lub teeb liab no, koj tuaj yeem hloov qhov chaw rau Enable.

Pab kom Busy Interface Parameter hauv Parameter Editorintel-750856-Agilex-FPGA-Development-Board-FIG-1 (10)

  1. Nyem File ➤ Txuag thiab tawm ntawm qhov parameter editor yam tsis tau tsim lub kaw lus. Tus parameter editor generates lub external_host_pr_ip.ip IP variation file thiab ntxiv cov file mus rau qhov project blinking_led. AN 991: Ib nrab Reconfiguration ntawm Configuration Pins (Sab nrauv tswv) Siv Tsim 750856 | 2022.11.14 IB 991:
    • Nco tseg:
    • a. Yog tias koj luam the external_host_pr_ip.ip file los ntawm pr directory, manually kho lub blinking_led.qsf file kom suav nrog cov kab hauv qab no: set_global_assignment -name IP_FILE pr_ip.ip ib
    • b. Muab tus IP_FILE ua haujlwm tom qab SDC_FILE assignments (blinking_led. dc) hauv koj blinking_led.qsf file. Qhov kev txiav txim no ua kom muaj kev txwv tsim nyog ntawm Ib Feem Kev Txhim Kho Kev Tswj Xyuas IP core.
    • Nco tseg: Txhawm rau txheeb xyuas cov moos, .sdc file rau PR IP yuav tsum ua raws li ib qho .sdc uas tsim cov moos uas tus IP core siv. Koj pab txhawb qhov kev txiav txim no los ntawm kev xyuas kom meej tias .ip file rau PR IP core tshwm tom qab ib qho .ip files or.sdc files uas koj siv los txhais cov moos hauv .qsf file rau koj qhov kev hloov kho tshiab ntawm Intel Quartus Prime. Yog xav paub ntxiv, saib mus rau Ib Feem Reconfiguration IP Solutions User Guide.

Hloov kho cov qauv tsim sab saum toj

Txhawm rau hloov kho top.sv file nrog PR_IP piv txwv:

  1. Txhawm rau ntxiv qhov piv txwv external_host_pr_ip rau cov qauv tsim sab saum toj, tsis hais cov cai hauv qab no hauv top.sv file:intel-750856-Agilex-FPGA-Development-Board-FIG-1 (11)

Defining Personas
Qhov kev tsim qauv siv no txhais tau peb tus kheej cais rau ib leeg PR muab faib. Txhawm rau txhais thiab suav nrog cov neeg hauv koj qhov project:

  1. Tsim peb SystemVerilog files, blinking_led.sv, blinking_led_slow.sv, thiab blinking_led_empty.sv hauv koj daim ntawv teev npe ua haujlwm rau peb tus neeg.

Reference Design Personasintel-750856-Agilex-FPGA-Development-Board-FIG-1 (12) intel-750856-Agilex-FPGA-Development-Board-FIG-1 (13)

Nco tseg:

  • blinking_led.sv twb muaj nyob ua ib feem ntawm cov files koj luam los ntawm lub tiaj / sub-directory. Koj tsuas tuaj yeem rov siv qhov no file.
  • Yog tias koj tsim qhov SystemVerilog files los ntawm Intel Quartus Prime Text Editor, lov tes taw Ntxiv file rau qhov kev xaiv tam sim no, thaum txuag lub files.

Tsim cov kev hloov kho

PR tsim ntws siv qhov kev hloov kho qhov project hauv Intel Quartus Prime software. Koj qhov kev tsim thawj zaug yog lub hauv paus kev kho dua tshiab, qhov twg koj txhais cov cheeb tsam zoo li qub ciam teb thiab thaj chaw rov kho dua ntawm FPGA. Los ntawm kev hloov kho hauv paus, koj tsim ntau qhov kev hloov kho. Cov kev hloov kho no muaj cov kev siv sib txawv rau thaj tsam PR. Txawm li cas los xij, txhua qhov kev hloov kho PR siv tib qhov kev tso kawm saum toj kawg nkaus thiab cov txiaj ntsig tau los ntawm kev hloov kho hauv paus. Txhawm rau sau tus qauv PR, koj yuav tsum tsim kho qhov kev siv PR rau txhua tus neeg. Tsis tas li ntawd, koj yuav tsum muab cov kev hloov kho tshiab rau txhua qhov kev hloov kho. Cov kev hloov kho uas muaj yog:

  • Ib nrab Reconfiguration – Base
  • Ib nrab Reconfiguration – Persona Implementation

Cov lus hauv qab no teev cov npe hloov kho thiab hom kho dua tshiab rau txhua qhov kev hloov kho:

Hloov kho npe thiab hom

Kho lub npe Kev kho hom
blinking_led.qsf Ib nrab Reconfiguration – Base
blinking_led_default.qsf Ib nrab Reconfiguration – Persona Implementation
blinking_led_slow.qsf Ib nrab Reconfiguration – Persona Implementation
blinking_led_empty.qsf Ib nrab Reconfiguration – Persona Implementation

Kev teeb tsa Base Revision Type

  1. Nyem qhov Project ➤ Hloov kho.
  2. Hauv Kev Kho Lub Npe, xaiv qhov hloov kho blinking_led, thiab tom qab ntawd nyem Teem Tam sim no.
  3. Nyem Thov. Kev hloov kho blinking_led qhia raws li kev kho tam sim no.
  4. Txhawm rau teeb tsa Kev Kho Kho Hom rau blinking_led, nyem Assignments ➤ Chaw ➤ General.
  5. Rau Kev Kho Kho Hom, xaiv Ib Feem Reconfiguration - Base, thiab tom qab ntawd nyem OK.
  6. Xyuas kom tseeb tias blinking_led.qsf tam sim no muaj cov haujlwm hauv qab no: ##blinking_led.qsf set_global_assignment -name REVISION_TYPE PR_BASE

Tsim cov kev hloov kho tshiab

  1. Txhawm rau qhib lub Khoos Kas Kho Mob, nyem qhov Project ➤ Hloov kho.
  2. Txhawm rau tsim kho tshiab, nyem ob npaug rau < >.
  3. Hauv Revision lub npe, qhia meej blinking_led_default thiab xaiv blinking_led rau Raws li kev kho dua.
  4. Rau hom Kho dua tshiab, xaiv Ib Feem Kev Kho Dua Tshiab - PersonaImplementation.

Tsim cov kev hloov khointel-750856-Agilex-FPGA-Development-Board-FIG-1 (14)

  1. Ib yam li ntawd, teeb tsa hom Kev Hloov Kho rau blinking_led_slow thiab blinking_led_empty revisions.
  2. Xyuas kom tseeb tias txhua .qsf file tam sim no muaj cov haujlwm hauv qab no: set_global_assignment -name REVISION_TYPE PR_IMPL set_instance_assignment -name ENTITY_REBINDING \ place_holder -to u_blinking_led qhov twg, place_holder yog lub npe chaw ua haujlwm rau qhov kev tsim kho tshiab PR.

Kev kho qhov projectintel-750856-Agilex-FPGA-Development-Board-FIG-1 (16)

Compiling lub Base Revision

  1. Txhawm rau sau cov kev hloov kho hauv paus, nyem Ua Haujlwm ➤ Pib Sau. Xwb, cov lus txib hauv qab no suav nrog lub hauv paus hloov kho: quartus_sh –flow compile blinking_led -c blinking_led
  2. Tshawb xyuas qhov bitstream files uas tsim nyob rau hauv cov zis_files cov directory.

Tsim Files

Lub npe Hom Kev piav qhia
blinking_led.sof Base programming file Siv rau tag nrho-chip puag configuration
blinking_led.pr_partition.rbf PR bitstream file rau base persona Siv rau ib nrab reconfiguration ntawm lub hauv paus persona.
blinking_led_static.qdb .qdb database file Qhov kawg database file siv los import cov cheeb tsam zoo li qub.

Cov ntaub ntawv ntsig txog

  • "Floorplan lub Ib Nrab Reconfiguration Design" hauv Intel Quartus Prime Pro Tsab Ntawv Qhia Tus Neeg Siv: Ib Feem Reconfiguration
  • "Siv Floorplan Constraints Incrementally" nyob rau hauv Intel Quartus Prime Pro Tsab Ntawv Qhia Tus Neeg Siv: Ib Feem Reconfiguration

Npaj PR Kev Hloov Kho Kev Ua Haujlwm
Koj yuav tsum npaj cov kev hloov kho PR ua ntej koj tuaj yeem sau thiab tsim cov PR bitstream rau cov cuab yeej programming. Qhov kev teeb tsa no suav nrog ntxiv thaj tsam zoo li qub .qdb file raws li yog qhov file rau txhua qhov kev kho dua tshiab. Tsis tas li ntawd, koj yuav tsum qhia qhov chaw sib thooj ntawm PR cheeb tsam.

  1. Txhawm rau teeb tsa qhov kev hloov kho tam sim no, nyem qhov Project ➤ Kev kho dua tshiab, xaiv blinking_led_default li lub npe Hloov kho, thiab tom qab ntawd nyem Teem Tam sim no.
  2. Txhawm rau txheeb xyuas qhov tseeb rau txhua qhov kev kho dua tshiab, nyem qhov Project ➤ Ntxiv / Tshem tawm Files hauv Project. Lub blinking_led.sv file tshwm hauv file lis.

FilesPageintel-750856-Agilex-FPGA-Development-Board-FIG-1 (17)

  1. Rov ua cov kauj ruam 1 txog 2 txhawm rau txheeb xyuas lwm qhov kev kho dua tshiab files:
Kev Hloov Kho Lub Npe Qhov chaw File
blinking_led_default blinking_led.sv
blinking_led_empty blinking_led_empty.sv
blinking_led_slow blinking_led_slow.sv
  1. Txhawm rau txheeb xyuas qhov .qdb file txuam nrog lub hauv paus muab faib, nyem Assignments ➤ Design Partitions Window. Paub meej tias qhov muab faib Database File qhia qhov blinking_led_static.qdb file, los yog muab ob npaug rau-nias qhov Partition Database File cell los qhia qhov no file. Xwb, cov lus txib hauv qab no muab qhov no file: set_instance_assignment -name QDB_FILE_PARTITION \ blinking_led_static.qdb -to |
  2. Hauv qhov chaw Re-binding cell, qhia lub npe chaw ntawm txhua qhov kev faib tawm PR uas koj hloov pauv hauv kev kho dua tshiab. Rau qhov kev hloov kho blinking_led_default, qhov chaw lub npe yog blinking_led. Hauv qhov kev qhia no, koj sau qhov ua piv txwv u_blinking_led los ntawm lub hauv paus kev kho dua suav nrog cov tshiab blinking_led qhov chaw.

Nco tseg: Ib qhov chaw muab qhov chaw rebinding assignment yog ntxiv rau qhov kev siv kho dua tshiab. Txawm li cas los xij, koj yuav tsum hloov lub npe chaw ua haujlwm nyob rau hauv txoj haujlwm rau lub npe tsim nyog rau koj tus qauv tsim.

Kev Hloov Kho Lub Npe Qhov chaw Re-binding
blinking_led_default blinking_led
blinking_led_slow blinking_led_slow
blinking_led_empty blinking_led_empty

Lub koom haum Rebindingintel-750856-Agilex-FPGA-Development-Board-FIG-1 (18)

  1. Txhawm rau sau cov qauv tsim, nyem Ua Haujlwm ➤ Pib muab tso ua ke. Xwb, cov lus txib hauv qab no suav nrog qhov project: quartus_sh –flow compile blinking_led –c blinking_led_default
  2. Rov ua cov kauj ruam saum toj no los npaj blinking_led_slow thiab blinking_led_empty revisions: quartus_sh –flow compile blinking_led –c blinking_led_slow quartus_sh –flow compile blinking_led –c blinking_led_empt

Nco tseg: Koj tuaj yeem hais qhia ib qho Fitter tshwj xeeb qhov chaw uas koj xav thov thaum lub sij hawm PR muab tso ua ke. Fitter cov chaw tshwj xeeb cuam tshuam tsuas yog qhov haum ntawm tus neeg, tsis cuam tshuam rau thaj chaw zoo li qub tuaj.

Programming lub Rooj Tswjhwm Saib
Qhov kev qhia no siv Intel Agilex F-Series FPGA kev txhim kho pawg thawj coj ntawm lub rooj ntev zaum, sab nraud ntawm PCIe * qhov hauv koj lub tshuab host. Ua ntej koj npaj lub rooj tsavxwm, xyuas kom meej tias koj tau ua tiav cov kauj ruam hauv qab no:

  1. Txuas lub hwj huam mov rau Intel Agilex F-Series FPGA kev txhim kho pawg thawj coj.
  2. Txuas Intel FPGA Download Cable ntawm koj lub PC USB chaw nres nkoj thiab Intel FPGA Download Cable chaw nres nkoj ntawm lub rooj tsav xwm kev loj hlob.

Txhawm rau khiav tus tsim ntawm Intel Agilex F-Series FPGA kev txhim kho pawg thawj coj saib:

  1. Qhib Intel Quartus Prime software thiab nyem Cov Cuab Yeej ➤ Programmer.
  2. Hauv Programmer, nyem Hardware Setup thiab xaiv USB-Blaster.
  3. Nyem Pib Tshawb Nrhiav thiab xaiv lub cuab yeej, AGFB014R24AR0.
  4. Nyem OK. Intel Quartus Prime software tshawb pom thiab hloov kho Programmer nrog peb FPGA li ntawm lub rooj tsavxwm.
  5. Xaiv AGFB014R24AR0 ntaus ntawv, nyem Hloov File thiab thauj cov blinking_led_default.sof file.
  6. Qhib Program/Configure rau blinking_led_default.sof file.
  7. Nyem Pib thiab tos rau qhov kev nce qib kom ncav cuag 100%.
  8. Saib xyuas cov LEDs ntawm lub rooj tsavxwm blinking ntawm tib zaus raws li tus qauv qub.
  9. Txhawm rau program tsuas yog thaj tsam PR, txoj cai-nias lub blinking_led_default.sof file hauv Programmer thiab nyem Ntxiv PR Programming File.
  10. Xaiv lub blinking_led_slow.pr_partition.rbf file.
  11. Disable Program/Configure rau blinking_led_default.sof file.
  12. Qhib Program/Configure rau blinking_led_slow.pr_partition.rbf file thiab nias Start. Ntawm lub rooj tsavxwm, saib LED[0] thiab LED[1] txuas ntxiv mus ntsais. Thaum qhov kev nce qib nce mus txog 100%, LED [2] thiab LED [3] blink qeeb.
  13. Txhawm rau reprogram thaj tsam PR, right-click lub .rbf file hauv Programmer thiab nyem Hloov PR Programing File.
  14. Xaiv lub .rbf files rau lwm tus ob tus neeg los saib xyuas tus cwj pwm ntawm lub rooj tsavxwm. Loading lub blinking_led_default.rbf file ua rau cov LEDs ntsais ntawm ib qho zaus, thiab thauj cov blinking_led_empty.rbf file ua rau cov LEDs nyob twj ywm ON.

Programming Intel Agilex F-Series FPGA Development Boardintel-750856-Agilex-FPGA-Development-Board-FIG-1 (19)Hardware Test Flow

Cov kab hauv qab no piav qhia txog kev siv cov khoom siv kho vajtse ntsuas kev khiav dej num.
Intel Agilex Ntaus Sab Nraud Sab Nraud Sab Nraud Hardware Teebintel-750856-Agilex-FPGA-Development-Board-FIG-1 (20)

Txoj Haujlwm Pabcuam FPGA (Tus Tswv Sab Nraud)
Cov kab ke hauv qab no piav qhia txog qhov programming tus pab FPGA uas ua haujlwm raws li PR txheej txheem sab nraud tus tswv tsev:

  1. Qhia meej txog Avalon streaming interface teeb tsa uas sib haum nrog hom uas koj xaiv (x8, x16, lossis x32).
  2. Pib lub platform los ntawm kev tsim cov pab pawg FPGA siv Intel Quartus Prime Programmer thiab txuas nrog kev teeb tsa cable.
  3. Siv tus pab FPGA, nyeem CONF_DONE thiab AVST_READY cov cim. CONF_DONE yuav tsum yog 0, AVST_READY yuav tsum yog 1. Logic siab ntawm tus pin no qhia tias SDM yog npaj los txais cov ntaub ntawv los ntawm tus tswv tsev sab nraud. Cov zis no yog ib feem ntawm SDM I/O.

Nco tseg: CONF_DONE tus pin taw qhia tus tswv tsev sab nraud uas hloov pauv bitstream ua tiav. Siv cov cim no tsuas yog saib xyuas cov txheej txheem kev teeb tsa chip tag nrho. Xa mus rau Intel Agilex Configuration User Guide rau cov lus qhia ntxiv ntawm tus pin no.

Kev Pabcuam DUT FPGA nrog Tag Nrho Chip SOF ntawm Sab Nraud Sab Nraud Cov kab hauv qab no piav qhia txog kev ua haujlwm DUT FPGA nrog tag nrho nti SRAM Khoom File (.sof) siv tus tswv tsev Avalon streaming interface:

  1. Sau tag nrho nti bitstream rau hauv DDR4 lub cim xeeb sab nraud ntawm tus pab FPGA (tus tswv sab nraud).
  2. Configure DUT FPGA nrog tag nrho nti .sof siv Avalon streaming interface (x8, x16, x32).
  3. Nyeem cov xwm txheej DUT FPGA teeb tsa teeb tsa. CONF_DONE yuav tsum yog 1, AVST_READY yuav tsum yog 0.

Lub Sijhawm Specifications: Ib Feem Reconfiguration Sab Nraud Controller Intel FPGA IPintel-750856-Agilex-FPGA-Development-Board-FIG-1 (21)

Program DUT FPGA nrog Thawj Persona ntawm Sab Nraud Tus Tswv

  1. Siv qhov khov ntawm lub hom phiaj PR cheeb tsam hauv DUT FPGA.
  2. Siv Intel Quartus Prime System Console, lees paub pr_request kom pib qhov kev teeb tsa ib nrab. AVST_READY yuav tsum yog 1.
  3. Sau thawj PR persona bitstream rau hauv DDR4 lub cim xeeb sab nraud ntawm tus pab FPGA (tus tswv tsev sab nraud).
  4. Siv Avalon streaming interface (x8, x16, x32), rov teeb tsa DUT FPGA nrog thawj tus neeg bitstream.
  5. Txhawm rau saib xyuas cov xwm txheej PR, nyem Cov Cuab Yeej ➤ System Console los tso System Console. Hauv System Console, saib xyuas PR xwm txheej:
    • pr_error yog 2-reconfiguration nyob rau hauv tus txheej txheem.
    • pr_error yog 3-reconfiguration tiav.
  6. Thov unfreeze rau thaj tsam PR hauv DUT FPGA.

Nco tseg: Yog tias qhov yuam kev tshwm sim thaum lub sijhawm ua haujlwm PR, xws li tsis ua haujlwm hauv kev kuaj xyuas lossis kev tso cai, kev ua haujlwm PR yuav xaus.

Cov ntaub ntawv ntsig txog

  • Intel Agilex Configuration User Guide
  • Intel Quartus Prime Pro Tsab Ntawv Qhia Tus Neeg Siv: Cov cuab yeej Debug

Cov Ntaub Ntawv Hloov Kho Keeb Kwm rau AN 991: Ib Feem Kev Kho Dua Tshiab ntawm Configuration Pins ( Sab Nraud Tus Tswv Cuab ) Kev Tsim Qauv rau Intel Agilex F-Series FPGA Development Board

Cov ntaub ntawv Version Intel Quartus Prime Version Hloov
2022.11.14 22.3 • Kev tso tawm thawj zaug.

AN 991: Ib Feem Reconfiguration ntawm Configuration Pins ( Sab Nraud Lub Tswv Yim ) Kev Tsim Qauv: rau Intel Agilex F-Series FPGA Development Board

Cov lus teb rau cov FAQs saum toj kawg nkaus:

  • Q PR ntawm kev teeb tsa tus pins yog dab tsi?
  • A Sab nraud Host Configuration ntawm nplooj 3
  • Q Kuv xav tau dab tsi rau tus qauv siv no?
  • A Reference Design Requirements ntawm nplooj 6
  • Q Kuv tuaj yeem tau txais tus qauv siv nyob qhov twg?
  • A Reference Design Requirements ntawm nplooj 6
  • Q Kuv yuav ua li cas PR ntawm kev teeb tsa sab nraud?
  • A Reference Design Walkthrough ntawm nplooj 6
  • Q PR persona yog dab tsi?
  • A Defining Personas ntawm nplooj 11
  • Q Kuv yuav ua li cas rau lub rooj tsavxwm?
  • A Txoj Haujlwm Pab Pawg ntawm nplooj 17
  • Q Dab tsi yog PR paub txog teeb meem thiab kev txwv?
  • A Intel FPGA Support Forums: PR
  • Q Koj puas muaj kev cob qhia txog PR?
  • A Intel FPGA Technical Training Catalog

Online Version Xa lus tawm tswv yim

  • ID: 750856
  • Version: 2022.11.14

Cov ntaub ntawv / Cov ntaub ntawv

Intel 750856 Agilex FPGA Development Board [ua pdf] Cov neeg siv phau ntawv qhia
750856, 750857, 750856 Agilex FPGA Development Board, Agilex FPGA Development Board, FPGA Development Board, Pawg Thawj Coj, Pawg Thawj Coj

Cov ntaub ntawv

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