ọdịnaya zoo
1 intel 750856 Agilex FPGA Development Board
2 Ozi ngwaahịa
3 Ntuziaka ojiji ngwaahịa
4 Ntụaka Nhazi gafereview
5 Nhazi Ọbịa Mpụga
6 Ntụaka atụmatụ chọrọ
7 Ntụgharị aka imewe ntụaka
8 Ịmepụta nkebi imewe
9 Ịmepụta nyocha
10 Aha na ụdị ngbanwe
11 Na-eme mmemme nke Intel Agilex F-Series FPGA Development BoardHardware Flow
12 Akwụkwọ / akụrụngwa
12.1 Ntụaka

intel-LOGO

intel 750856 Agilex FPGA Development Board

intel-750856-Agilex-FPGA-mmepe-bọọdụ-ngwaahịa

Ozi ngwaahịa

Atụmatụ ntụaka a bụ maka Intel Agilex F-Series FPGA Development Board. Ọ na-eji Onye njikwa nhazi nhazi nke mpụ na-ahụ anya Intel FPGA IP ma nwee mpaghara PR dị mfe. Ngwa ngwa ngwa ngwa ngwa ngwa ngwa ngwa ngwa nke mpụga nke Intel Agilex nwere ngwaọrụ mpụga (Helper FPGA), DUT FPGA, yana atụmatụ nnabata gị. Nhazi onye ọbịa na ngwaọrụ mpụga bụ maka ịnabata usoro PR. A na-eji ntụtụ PR jikọọ ngwaọrụ abụọ ahụ ma nwee ike ịbụ onye ọrụ I/O ọ bụla dị.

Ntuziaka ojiji ngwaahịa

Nhazi Ọbịa Mpụga

Iji mee nhazi nhazi nke ndị ọbịa, soro usoro ndị a:

  1. Mepụta atụmatụ nnabata na ngwaọrụ mpụga iji kwado usoro PR.
  2. Jikọọ ntụtụ PR site na ngwaọrụ mpụga na Onye njikwa nhazi nhazi nke mpụga Intel FPGA IP na DUT FPGA.
  3. Nhazi data nhazi site na nhazi onye nnabata gaa na ntụtụ interface Agilex Avalon gụgharia nke dabara na akara aka PR sitere na IP.

Nhazigharị akụkụ akụkụ site na Nhazi Nhazi arụ ọrụ

Usoro na-esonụ na-akọwa ọrụ nke nhazigharị akụkụ site na ntụtụ nhazi:

  1. Wepụta ntụtụ pr_request ejikọrọ na Onye njikwa nhazi nhazi nke mpụ na Intel FPGA IP.
  2. IP na-ekwupụta mgbama nọ n'ọrụ iji gosi na usoro PR na-aga n'ihu (nhọrọ).
  3. Ọ bụrụ na usoro nhazi ahụ dị njikere maka ọrụ PR, a na-ekwupụta pin avst_ready, na-egosi na ọ dị njikere ịnakwere data.
  4. Gbanye data nhazi PR n'elu ntụtụ avst_data na avst_valid pin, na-agbaso nkọwapụta Avalon maka mbufe data na nkwụghachi azụ.
  5. gụgharia akwụsị mgbe avst_ready pin ka ewepụrụ.
  6. Wepụ avst_ready pin ka ọ gosipụta na ọ nweghị data ọzọ achọrọ maka ọrụ PR.
  7. Onye na-ahụ maka nhazi nhazi nke mpụga Intel FPGA IP na-eme ka mgbama nọ n'aka iji gosi njedebe nke usoro a (nhọrọ).

Nhazigharị akụkụ site na ntụtụ nhazi (onye ọbịa na-apụ apụ) chepụta ntụaka

Ihe ndetu ngwa a na-egosi nhazigharị akụkụ site na nhazi nhazi (onye ọbịa mpụga) na bọọdụ mmepe Intel® Agilex® F-Series FPGA.

Ntụaka Nhazi gafereview

Akụkụ nhazigharị akụkụ (PR) na-enye gị ohere ịhazigharị akụkụ nke FPGA nke ọma, ebe ihe FPGA fọdụrụnụ na-aga n'ihu na-arụ ọrụ. Ị nwere ike ịmepụta ọtụtụ mmadụ maka otu mpaghara n'ime imewe gị nke na-adịghị emetụta ọrụ na mpaghara na-abụghị mpaghara a. Usoro a dị irè na sistemu ebe ọtụtụ ọrụ na-ekekọrịta oge-ekekọrịta akụrụngwa FPGA otu. Ụdị sọftụwia Intel Quartus® Prime Pro Edition dị ugbu a na-ewebata usoro nchịkọta ọhụrụ na nke dị mfe maka nhazigharị akụkụ. Ihe nrụtụ aka Intel Agilex a na-eji njikwa nhazi nhazi nke mpụga Intel FPGA IP ma nwee mpaghara PR dị mfe.

Ngwaọrụ Intel Agilex Mpụga Ngwaike Ngwaikeintel-750856-Agilex-FPGA-Board Mmepe-FIG-1 (1)

Nhazi Ọbịa Mpụga

Na nhazi nhazi nke mpụga, ị ga-ebu ụzọ mepụta nhazi nnabata na ngwaọrụ mpụga iji kwado usoro PR, dị ka ntọala ngwaike ngwaike nke Intel Agilex External Host na-egosi. Ndị na-eme ihe nhazi na-ebunye data nhazi data na Intel Agilex Avalon gụgharia interface pins nke kwekọrọ na akara aka PR nke na-abịa site na Onye njikwa nhazi nhazi nke mpụga Intel FPGA IP. Ntụtụ PR nke ị na-eji jikọọ ngwaọrụ abụọ a nwere ike ịbụ I/Os ọ bụla dịnụ.

Usoro na-esonụ na-akọwa nhazigharị akụkụ site na ọrụ nhazi nhazi:

  1. Buru ụzọ kwupụta ntụtụ pr_request nke ejikọrọ na Onye njikwa nhazi nhazi nke mpụga Intel FPGA IP.
  2. IP na-ekwupụta mgbama nọ n'ọrụ iji gosi na usoro PR na-aga n'ihu (nhọrọ).
  3. Ọ bụrụ na usoro nhazi ahụ dị njikere ịrụ ọrụ PR, a na-ekwupụta pin avst_ready na-egosi na ọ dị njikere ịnakwere data.
  4. Malite ịkwanye data nhazi PR n'elu ntụtụ avst_data yana avst_valid pin, ka ị na-elele nkọwapụta Avalon maka mbufe data site na iji nrụgide azụ.
  5. gụgharia na-akwụsị mgbe ọ bụla ewepụrụ avst_ready pin.
  6. Mgbe ị nwetasịrị data nhazi niile, a na-ewepụ avst_ready pin iji gosi na ọ dịghị data ọzọ achọrọ maka ọrụ PR.
  7. Onye njikwa nhazi nhazi nke mpụga Intel FPGA IP na-eme ka mgbama nọ n'aka iji gosi njedebe nke usoro a (nhọrọ).
  8. Ị nwere ike ịlele pr_done na pr_error pins iji gosi ma ọrụ PR arụchara nke ọma. Ọ bụrụ na njehie emee, dị ka ọdịda na nlele ụdị na nlele ikike, ọrụ PR kwụsịrị.

Ozi metụtara

  • Agilex F-Series FPGA Development Kit Web Ibe
  • Ntuziaka onye ọrụ Kit Agilex F-Series FPGA Development Kit
  • Ntuziaka onye ọrụ Intel Quartus Prime Pro Edition: Nhazigharị akụkụ

Onye na-ahụ maka nhazi nhazi nke mpụga Intel FPGA IP
Ihe njikwa nhazi nhazi nke mpụ ga-achọrọ ka ọ jiri ntụtụ nhazi weba data PR maka ọrụ PR. Ị ga-ejikọrịrị ọdụ ụgbọ mmiri niile dị elu nke Partial Reconfiguration External Configuration Controller Intel FPGA IP na pr_request pin iji kwe ka aka nke onye ọbịa na njikwa ngwaọrụ echedoro (SDM) site na isi. SDM na-ekpebi ụdị ntụtụ nhazi nke ị ga-eji, dịka ntọala MSEL gị siri dị.

Onye na-ahụ maka nhazi nhazi nke mpụga Intel FPGA IPintel-750856-Agilex-FPGA-Board Mmepe-FIG-1 (2)

Ntọala nhazi nhazi nke mpụ na-ahụ maka nhazi nke akụkụ

Oke Uru Nkọwa
Kwado interface na-arụ ọrụ Kwado or

Gbanyụọ

 Na-enye gị ohere Kwado ma ọ bụ gbanyụọ interface arụ ọrụ, nke na-ekwupụta mgbaàmà iji gosi na nhazi PR na-aga n'ihu n'oge nhazi mpụga.

Ntọala izizi bụ Gbanyụọ.

Ọdụ ụgbọ mmiri njikwa nhazi nke mpụga

Aha Port Obosara Ntuziaka Ọrụ
arịrịọ pr_arịrịọ 1 Ntinye Na-egosi na usoro PR dị njikere ịmalite. Mgbama bụ ọwa mmiri anaghị emekọrịta na mgbama elekere ọ bụla.
pr_error 2 Mpụta Na-egosi mperi nhazigharị akụkụ akụkụ.:

• 2'b01 — njehie PR izugbe

• 2'b11 — njehie bitstream na-adakọghị

Ihe mgbaàmà ndị a abụghị ihe jikọrọ ya na ebe elekere ọ bụla.
pr_emela 1 Mpụta Na-egosi na usoro PR zuru ezu. Mgbama bụ ọwa mmiri anaghị emekọrịta na mgbama elekere ọ bụla.
mmalite_addr 1 Ntinye Na-akọwapụta adreesị mmalite nke data PR na Serial Flash nọ n'ọrụ. Ị na-eme ka mgbaama a site na ịhọrọ nke ọ bụla Avalon®-ST or Oghere Usoro Ọrụ maka Kwado Avalon-ST ntụtụ ma ọ bụ Oghere Usoro ntụtụ na-arụ ọrụ oke. Mgbama bụ ọwa mmiri anaghị emekọrịta na mgbama elekere ọ bụla.
tọgharịa 1 Ntinye Mgbama nrụpụta nrụpụta na-arụkọ ọrụ ọnụ.
pụọ_clk 1 Mpụta Isi iyi elekere na-esite na oscillator ime.
ji n'aka 1 Mpụta IP na-ekwupụta mgbama a iji gosi mbufe data PR na-aga n'ihu. Ị na-eme ka mgbaama a site na ịhọrọ Kwado maka Kwado interface nọ n'aka oke.

Ntụaka atụmatụ chọrọ

Iji atụmatụ ntụaka a chọrọ ihe ndị a:

  • Ntinye nke Intel Quartus Prime Pro Edition 22.3 nwere nkwado maka ezinụlọ ngwaọrụ Intel Agilex.
  • Njikọ na bọọdụ mmepe FPGA Intel Agilex F-Series na bench.
  • Nbudata nke imewe example dị na ebe a: https://github.com/intel/fpga-partial-reconfig.

Ka ibudata imewe exampLe:

  1. Pịa Clone ma ọ bụ budata.
  2. Pịa Budata ZIP. Mepee fpga-partial-reconfig-master.zip file.
  3. Gaa na nkuzi/agilex_external_pr_configuration obere nchekwa iji nweta nhazi ntụaka.

Ntụgharị aka imewe ntụaka

Usoro ndị a na-akọwa mmejuputa nhazi nke akụkụ site na nhazi nhazi (onye ọbịa mpụga) na bọọdụ mmepe Intel Agilex F-Series FPGA:

  • Nzọụkwụ 1: Na-amalite
  • Nzọụkwụ 2: Ịmepụta nkebi imewe
  • Nzọụkwụ 3: Ekenye mpaghara na ụzọ ụzọ
  • Nzọụkwụ 4: Na-agbakwunye IP njikwa nhazigharị akụkụ nke mpụga
  • Nzọụkwụ 5: Ịkọwa mmadụ
  • Nzọụkwụ 6: Ịmepụta nyocha
  • Nzọụkwụ 7: Na-achịkọta Ndozigharị ntọala
  • Nzọụkwụ 8: Na-akwado ndezigharị mmejuputa iwu PR
  • Nzọụkwụ 9: Ịmepụta Board

Nzọụkwụ 1: Malite
Ka idetuo atụmatụ ntụaka filegaa na gburugburu ebe ị na-arụ ọrụ wee chịkọta atụmatụ flat blinking_led:

  1. Mepụta ndekọ na gburugburu ebe ọrụ gị, agilex_pcie_devkit_blinking_led_pr.
  2. Detuo nkuzi ebudatara/agilex_pcie_devkit_blinking_led/flat sub-folder na ndekọ, agilex_pcie_devkit_blinking_led_pr.
  3. Na ngwanrọ Intel Quartus Prime Pro Edition, pịa File ➤ Mepee Project wee họrọ blinking_led.qpf.
  4. Iji kọwapụta usoro nhazi nke flat, pịa Nhazi ➤ Malite ➤ Malite Analysis & Synthesis. N'aka nke ọzọ, na ahịrị iwu, mee iwu a: quartus_syn blinking_led -c blinking_led

Ịmepụta nkebi imewe

Ị ga-emepụta nkebi imewe maka mpaghara PR ọ bụla nke ịchọrọ ịhazigharị akụkụ ụfọdụ. Usoro ndị a na-emepụta akụkụ imewe maka ihe atụ u_blinking_led.

Ịmepụta nkebi imeweintel-750856-Agilex-FPGA-Board Mmepe-FIG-1 (3)

  1. Pịa aka nri u_blinking_led atụ na Project Navigator wee pịa Kere Partition ➤ Reconfigurable. Akara ngosi nkebi imewe na-egosi n'akụkụ ihe atụ ọ bụla edobere dị ka nkebi.
  2. Pịa Ọrụ ➤ Imepụta nkebi nkebi. Window na-egosiputa akụkụ niile nke imewe na ọrụ ahụ.
  3. Dezie nkebi aha na imewe Partitions Ohere site ugboro abụọ-ịpị aha. Maka atụmatụ ntụaka a, nyegharịa aha nkebi ka ọ bụrụ pr_partition
    • Mara: Mgbe ị mepụtara nkebi, sọftụwia Intel Quartus Prime na-ewepụta aha nkebi na-akpaghị aka, dabere na aha atụ na ụzọ ndị isi. Aha nkebi nke ndabara nwere ike ịdị iche na nke ọ bụla.
  4. Ka mbupụ mpaghara static emechachara site na nchịkọta ntugharị ntọala, pịa ntinye ugboro abụọ maka root_partition na Mbupụ ikpeazụ nke Post File kọlụm, wee pịnye blinking_led_static. gdb.

Mbupụ foto ikpeazụ ikpeazụ na windo nkebi imeweintel-750856-Agilex-FPGA-Board Mmepe-FIG-1 (4)Nyochaa na blinking_led.qsf nwere ọrụ ndị a, kwekọrọ na nkebi nhazi gị nwere ike ịhazi:intel-750856-Agilex-FPGA-Board Mmepe-FIG-1 (5)

Ozi metụtara
"Mepụta akụkụ imewe" na ntuziaka onye ọrụ Intel Quartus Prime Pro Edition: Nhazigharị akụkụ

Ekenye ntinye na mpaghara ụzọ maka nkebi PR
Maka ntughari ntọala ọ bụla ị mepụtara, usoro nhazi PR na-edobe isi persona kwekọrọ na mpaghara nkebi PR gị. Ka ịchọta ma kenye mpaghara PR na ala ngwaọrụ maka nlegharị anya ntọala gị:

  1. Pịa aka nri u_blinking_led na Project Navigator wee pịa Logic Lock Region ➤ Mepụta Mpaghara Logic Lock New. Mpaghara ahụ pụtara na windo Logic Lock Regions.
  2. Mpaghara ntinye gị ga-etinyerịrị mgbagha blinking_led. Họrọ mpaghara ntinye site na ịchọta ọnụ na Chip Planner. Pịa aka nri aha mpaghara u_blinking_led na windo Logic Lock Region wee pịa

Chọta Node ➤ Chọta na Chip Planner. Mpaghara u_blinking_led bụ akara agba

Ebe Node Chip Planner maka blinking_ledintel-750856-Agilex-FPGA-Board Mmepe-FIG-1 (6)

  1. Na mpio Logic Lock Regions, kọwapụta ngalaba nhazi mpaghara ntinye na kọlụm Origin. Isi mmalite dabara na akuku aka ekpe ala nke mpaghara ahụ. Maka example, ka ịtọọ mpaghara ntinye ya na nhazi (X1 Y1) dịka (163 4), kọwapụta Mmalite dịka X163_Y4. Akụrụngwa Intel Quartus Prime na-agbakọ nhazi (X2 Y2) na-akpaghị aka (n'elu-aka nri) maka mpaghara ntinye, dabere na ịdị elu na obosara ị kọwara.
    • Mara: Nkuzi a na-eji nhazi (X1 Y1) - (163 4), na ịdị elu na obosara nke 20 maka mpaghara ntinye. Kọwaa uru ọ bụla maka mpaghara ntinye. Gbaa mbọ hụ na mpaghara ahụ kpuchiri ezi uche blinking_led.
  2. Kwado nhọrọ echekwara na naanị isi.
  3. Pịa nhọrọ mpaghara Routing ugboro abụọ. Igbe mkpọchi Logic Lock Routing Region Settings igbe na-egosi.
  4. Họrọ Emebere ya na mgbasawanye maka ụdị ntụgharị. Ịhọrọ nhọrọ a na-akpaghị aka na-ekenye ogologo mgbasawanye nke 2.
    • Mara: Mpaghara ntụgharị ga-abụrịrị ibu karịa mpaghara ntinye, iji nyekwuo mgbanwe maka Fitter mgbe injin na-aga mmadụ dị iche iche.

Ohere Mpaghara Mkpọchi Logicintel-750856-Agilex-FPGA-Board Mmepe-FIG-1 (7)Nyochaa na blinking_led.qsf nwere ọrụ ndị a, kwekọrọ na nhazi ala gị:intel-750856-Agilex-FPGA-Board Mmepe-FIG-1 (8)intel-750856-Agilex-FPGA-Board Mmepe-FIG-1 (9)

Ozi metụtara
"Floorplan the Partial Reconfiguration Design" na Intel Quartus Prime Pro Edition Ntuziaka onye ọrụ: nhazigharị akụkụ.

Na-agbakwunye Onye njikwa nhazi nhazi nke mpụga Intel FPGA IP
Onye na-ahụ maka nhazi nhazi nke mpụga Intel FPGA IP yana ngọngọ njikwa Intel Agilex PR iji jikwaa isi iyi bitstream. Ị ga-agbakwunye IP a na nhazi gị iji mejuputa nhazi nke mpụga. Soro usoro ndị a ka ịgbakwunye Onye njikwa nhazi nhazi nke mpụ
Intel FPGA IP maka ọrụ gị:

  1. Pịnye nhazigharị akụkụ na mpaghara ọchụchọ katalọgụ IP (Ngwaọrụ ➤ Katalọgụ IP).
  2. Pịa ugboro abụọ Onye njikwa nhazi nhazi mpụga nke akụkụ Intel FPGA IP.
  3. N'ime igbe okwu Mepụta IP Variant, pịnye external_host_pr_ip dị ka nke File aha, wee pịa Mepụta. Ihe ndezi paramita na-egosi.
  4. N'ihi na Kwado interface ihe nrụnye ọrụ, họrọ Gbanyụọ (ntọala ndabere). Mgbe ịchọrọ iji mgbaama a, ị nwere ike ịgbanwee ntọala ka Kwado.

Kwado Parameter Interface arụ ọrụ na Parameter Editorintel-750856-Agilex-FPGA-Board Mmepe-FIG-1 (10)

  1. Pịa File ➤ Chekwaa wee pụọ na nchịkọta akụkọ paramita na-emepụtaghị sistemụ ahụ. Onye ndezi paramita na-ewepụta ọdịiche IP nke external_host_pr_ip.ip file ma na-agbakwụnye file ruo oru ngo blinking_ed. AN 991: Nhazigharị akụkụ site na ntụtụ nhazi (Onye ọbịa na-apụ apụ) Ntụle aka 750856 | 2022.11.14 AN 991:
    • Mara:
    • a. Ọ bụrụ na ị na-eṅomi external_host_pr_ip.ip file site na ndekọ pr, jiri aka dezie blinking_led.qsf file ịgụnye ahịrị ndị a: set_global_assignment -name IP_FILE pr_ip.ip
    • b. Debe IP_FILE ọrụ mgbe SDC_FILE ọrụ (blinking_led. dc) na blinking_led.qsf gị file. Usoro a na-eme ka mmachi kwesịrị ekwesị nke isi ihe njikwa nhazigharị akụkụ IP isi.
    • Mara: Iji chọpụta elekere, .sdc file n'ihi na PR IP ga-esochi .sdc ọ bụla nke na-emepụta clocks nke IP isi na-eji. Ị na-akwado usoro a site n'ịhụ na .ip file n'ihi na PR IP isi na-egosi mgbe ọ bụla .ip files ma ọ bụ .sdc files nke ị na-eji kọwaa elekere ndị a na .qsf file maka nyocha ọrụ Intel Quartus Prime gị. Maka ozi ndị ọzọ, rụtụ aka na ntuziaka onye ọrụ nhazigharị IP.

Na-emelite nhazi ọkwa dị elu

Ka imelite top.sv file jiri ihe atụ PR_IP:

  1. Iji tinye ihe atụ external_host_pr_ip na nhazi ọkwa dị elu, kwupụta koodu mgbochi ndị a na top.sv file:intel-750856-Agilex-FPGA-Board Mmepe-FIG-1 (11)

Na-akọwapụta Ndị mmadụ
Atụmatụ ntụaka a na-akọwapụta mmadụ atọ dị iche iche maka otu nkebi PR. Iji kọwapụta ma tinye ndị mmadụ n'ọrụ gị:

  1. Mepụta SystemVerilog atọ files, blinking_led.sv, blinking_led_slow.sv, na blinking_led_empty.sv n'ime ndekọ aha ọrụ gị maka mmadụ atọ ahụ.

Ndị nrụtụ akaintel-750856-Agilex-FPGA-Board Mmepe-FIG-1 (12) intel-750856-Agilex-FPGA-Board Mmepe-FIG-1 (13)

Mara:

  • blinking_led.sv adịlarị dị ka akụkụ nke fileị na-eṅomi site na flat/ sub-directory. Ị nwere ike iji nke a naanị ọzọ file.
  • Ọ bụrụ na ị mepụtara SystemVerilog files site na Intel Quartus Prime Text Editor, gbanyụọ Tinye file na nhọrọ oru ngo dị ugbu a, mgbe ị na-echekwa ihe files.

Ịmepụta nyocha

Usoro nhazi PR na-eji atụmatụ ntughari oru ngo na sọftụwia Intel Quartus Prime. Nhazi mbụ gị bụ ngbanwe ntọala, ebe ị na-akọwapụta oke mpaghara kwụ ọtọ na mpaghara nhazigharị na FPGA. Site na ntulegharị ntọala, ị na-emepụta ọtụtụ nyocha. Ndozigharị ndị a nwere mmejuputa iwu dị iche iche maka mpaghara PR. Agbanyeghị, ntulegharị mmejuputa PR niile na-eji otu ntinye ọkwa dị elu na nsonaazụ ntụgharị sitere na ntugharị ntọala. Iji chịkọta atụmatụ PR, ị ga-emerịrị nyocha mmejuputa PR maka onye ọ bụla. Na mgbakwunye, ị ga-ekenye ụdị ngbanwe maka ngbanwe nke ọ bụla. Ụdị ngbanwe dị bụ:

  • Nhazigharị akụkụ - Ntọala
  • Nhazigharị akụkụ - Persona Mmejuputa

Tebụlụ na-esote depụtara aha ngbanwe na ụdị ngbanwe maka ngbanwe ọ bụla:

Aha na ụdị ngbanwe

Aha ngbanwe Ụdị ngbanwe
blinking_led.qsf Nhazigharị akụkụ - Ntọala
blinking_led_default.qsf Nhazigharị akụkụ - Persona Mmejuputa
blinking_led_slow.qsf Nhazigharị akụkụ - Persona Mmejuputa
blinking_led_empty.qsf Nhazigharị akụkụ - Persona Mmejuputa

Ịtọlite ​​Ụdị Ndozigharị Ntọala

  1. Pịa Project ➤ Ndozigharị.
  2. Na Revision Aha, họrọ blinking_led revision, wee pịa Tọọ ugbu a.
  3. Pịa Tinye. Ngosipụta ntugharị blinking_led dị ka nlegharị anya ugbu a.
  4. Ka ịtọọ ụdị ngbanwe maka blinking_led, pịa Ọrụ ➤ Ntọala ➤ Ozuruọnụ.
  5. N'ihi na Revision Ụdị, họrọ Partial Reconfiguration – Base, wee pịa OK.
  6. Nyochaa na blinking_led.qsf nwere ọrụ ndị a: ##blinking_led.qsf set_global_assignment -name REVISION_TYPE PR_BASE

Ịmepụta ndezigharị mmejuputa

  1. Ka imepee igbe ngbanwe, pịa Project ➤ Ndozigharị.
  2. Iji mepụta nlegharị anya ọhụrụ, pịa ugboro abụọ < >.
  3. Na aha ngbanwe, ezipụta blinking_led_default wee họrọ blinking_led maka Dabere na ntughari.
  4. Maka ụdị ngbanwe, họrọ Nhazigharị akụkụ - PersonaImplementation.

Ịmepụta nyochaintel-750856-Agilex-FPGA-Board Mmepe-FIG-1 (14)

  1. N'otu aka ahụ, tọọ ụdị ntụgharị maka ntụgharị blinking_led_slow na blinking_led_empty.
  2. Nyochaa na onye ọ bụla .qsf file ugbu a nwere ọrụ ndị a: set_global_assignment -name REVISION_TYPE PR_IMPL set_intance_assignment -name ENTITY_REBINDING \ place_holder -to u_blinking_led where, place_holder bụ aha aha ndabara maka ndegharị mmejuputa iwu PR emepụtara ọhụrụ.

Ntụle oru ngointel-750856-Agilex-FPGA-Board Mmepe-FIG-1 (16)

Na-achịkọta Ndozigharị ntọala

  1. Iji chịkọta ngbanwe ntọala, pịa Nhazi ➤ Malite Nchịkọta. N'aka nke ọzọ, iwu na-esonụ na-achịkọta ntulegharị ntọala: quartus_sh -flow compile blinking_led -c blinking_led
  2. Lelee bitstream ahụ files na-emepụta na mmepụta_files ndekọ.

Emepụtara Files

Aha Ụdị Nkọwa
blinking_led.sof Mmemme ntọala file Ejiri ya maka nhazi ntọala mgbawa zuru oke
blinking_led.pr_partition.rbf PR bitstream file maka base persona Ejiri ya maka nhazigharị akụkụ nke base persona.
blinking_led_static.qdb .qdb nchekwa data file nchekwa data emechara file eji ebubata mpaghara static.

Ozi metụtara

  • "Floorplan the Partial Reconfiguration Design" na Intel Quartus Prime Pro Edition Ntuziaka onye ọrụ: nhazigharị akụkụ.
  • "Tinye ihe mgbochi Floorplan na-abawanye" na ntuziaka onye ọrụ Intel Quartus Prime Pro Edition: Nhazigharị akụkụ.

Na-akwado ndezigharị mmejuputa iwu PR
Ị ga-akwadorịrị ntụgharị mmejuputa PR tupu ị nwee ike chịkọta ma mepụta bitstream PR maka mmemme ngwaọrụ. Ntọlite ​​a gụnyere ịgbakwunye mpaghara static .qdb file dị ka isi iyi file maka nyocha mmejuputa ọ bụla. Na mgbakwunye, ị ga-ezipụta ihe kwekọrọ na mpaghara PR.

  1. Iji tọgharịa nlegharị anya ugbu a, pịa Project ➤ Revisions, họrọ blinking_led_default dị ka aha ngbanwe, wee pịa Tọọ Ugbu a.
  2. Iji nyochaa ebe ziri ezi maka ngbanwe mmejuputa iwu ọ bụla, pịa Project ➤Tinye/Wepụ Files na Project. Ihe blinking_led.sv file na-egosi na file ndepụta.

Files Ibeintel-750856-Agilex-FPGA-Board Mmepe-FIG-1 (17)

  1. Tinyegharịa usoro nke 1 ruo 2 iji nyochaa isi mmalite ngbanwe nke ọzọ files:
Aha ngbanwe nke mmejuputa Isi mmalite File
blinking_led_default blinking_led.sv
blinking_led_efu blinking_led_empty.sv
blinking_led_slow blinking_led_slow.sv
  1. Iji nyochaa .qdb file jikọtara na mgbọrọgwụ nkebi, click Ọrụ ➤ Imewe nkebi nkebi. Kwenye na database nkebi File na-akọwapụta blinking_led_static.qdb file, ma ọ bụ pịa ọdụ data nkebi ugboro abụọ File cell iji kọwaa nke a file. N'aka nke ọzọ, iwu na-esote na-ekenye nke a file: set_intance_assignment -aha QDB_FILE_PARTITION \ blinking_led_static.qdb -ga |
  2. N'ime cell Re-binding, ezipụta aha aha nke nkebi PR ọ bụla ị na-agbanwe na ndegharị mmejuputa. Maka ntughari mmejuputa blinking_led_default, aha otu ahụ bụ blinking_led. N'ime nkuzi a, ị degharịa ihe atụ u_blinking_led site na ntugharị ntọala na ihe ọhụrụ blinking_led.

Mara: A na-agbakwunye ihe nrụgharị ọrụ nke onye na-edobe ihe na nlegharị anya mmejuputa iwu na-akpaghị aka. Otú ọ dị, ị ga-agbanwerịrị aha ụlọ ọrụ ndabara na ọrụ ahụ gaa na aha ụlọ ọrụ kwesịrị ekwesị maka imewe gị.

Aha ngbanwe nke mmejuputa Ejikọkwa ụlọ ọrụ
blinking_led_default blinking_edu
blinking_led_slow blinking_led_slow
blinking_led_efu blinking_led_efu

Ntinyeghachi ụlọ ọrụintel-750856-Agilex-FPGA-Board Mmepe-FIG-1 (18)

  1. Iji chịkọta imewe ahụ, pịa Nhazi ➤ Malite Nchịkọta. N'aka nke ọzọ, iwu na-esonụ na-achịkọta ọrụ a: quartus_sh -flow compile blinking_led -c blinking_led_default
  2. Tinyegharịa usoro ndị a dị n'elu iji kwadebe blinking_led_slow na blinking_led_efu: quartus_sh -flow compile blinking_led -c blinking_led_slow quartus_sh -flow compile blinking_led -c blinking_led_empt

Mara: Ị nwere ike ịkọwapụta ntọala Fitter ọ bụla ịchọrọ itinye n'oge nchịkọta mmejuputa PR. Ntọala akọwapụtara nke ọma na-emetụta naanị mma nke onye ahụ, na-emetụtaghị mpaghara static ebubatara.

Ịmepụta Board
Nkuzi a na-eji bọọdụ mmepe Intel Agilex F-Series FPGA na bench, na mpụga oghere PCIe * na igwe nnabata gị. Tupu ị hazie bọọdụ ahụ, hụ na ịmechara usoro ndị a:

  1. Jikọọ ọkọnọ ike na bọọdụ mmepe Intel Agilex F-Series FPGA.
  2. Jikọọ eriri nbudata Intel FPGA n'etiti ọdụ ụgbọ USB PC gị yana ọdụ ụgbọ mmiri nbudata USB FPGA na bọọdụ mmepe.

Iji mee atụmatụ ahụ na bọọdụ mmepe Intel Agilex F-Series FPGA:

  1. Mepee sọftụwia Intel Quartus Prime wee pịa Ngwaọrụ ➤ Programmer.
  2. N'ime mmemme, pịa Ntọala ngwaike wee họrọ USB-Blaster.
  3. Pịa Chọpụta akpaaka wee họrọ ngwaọrụ, AGFB014R24AR0.
  4. Pịa OK. Akụrụngwa Intel Quartus Prime na-achọpụta ma na-emelite Programmer na ngwaọrụ FPGA atọ dị na bọọdụ ahụ.
  5. Họrọ ngwaọrụ AGFB014R24AR0, pịa Gbanwee File wee buo blinking_led_default.sof file.
  6. Kwado Mmemme/Hazie maka blinking_led_default.sof file.
  7. Pịa Malite ma chere ka ogwe ọganihu iru 100%.
  8. Lelee LEDs dị na bọọdụ ahụ ka ọ na-egbu maramara n'otu oge ahụ dị ka nhazi larịị mbụ.
  9. Iji hazie naanị mpaghara PR, pịa aka nri blinking_led_default.sof file na Programmer wee pịa Tinye PR Programming File.
  10. Họrọ blinking_led_slow.pr_partition.rbf file.
  11. Gbanyụọ mmemme/Hazie maka blinking_led_default.sof file.
  12. Kwado Mmemme/Hazie maka blinking_led_slow.pr_partition.rbf file wee pịa Malite. N'elu osisi, hụ LED[0] na LED[1] na-aga n'ihu na-enwu. Mgbe mmanya na-aga n'ihu ruru 100%, LED[2] na LED[3] na-eji nwayọ nwayọ.
  13. Iji megharịa mpaghara PR, pịa aka nri .rbf file na Programmer wee pịa Change PR Programing File.
  14. Họrọ .rbf files maka mmadụ abụọ ndị ọzọ ka ha hụ omume na bọọdụ. Na-ebu blinking_led_default.rbf file na-eme ka LEDs na-enwu n'otu oge, na-ebufe blinking_led_empty.rbf file na-eme ka LEDs nọrọ na ya.

Na-eme mmemme nke Intel Agilex F-Series FPGA Development Boardintel-750856-Agilex-FPGA-Board Mmepe-FIG-1 (19)Ugo Nnwale ngwaike

Usoro ndị na-esonụ na-akọwa eruba nleba anya imewe ngwaike.
Ngwaọrụ Intel Agilex Mpụga Ngwaike Ngwaikeintel-750856-Agilex-FPGA-Board Mmepe-FIG-1 (20)

Mepụta onye enyemaka FPGA (Onye ọbịa na-apụ apụ)
Usoro na-esonụ na-akọwa mmemme onye inyeaka FPGA na-arụ ọrụ dị ka onye na-ahụ maka mpụga PR:

  1. Ezipụta ntọala interface nkwanye Avalon nke dabara na ọnọdụ ị họọrọ (x8, x16, ma ọ bụ x32).
  2. Malite ikpo okwu site na ịhazi FPGA onye inyeaka site na iji Intel Quartus Prime Programmer na eriri nhazi ejikọrọ.
  3. Iji onye enyemaka FPGA, gụọ akara CONF_DONE na AVST_READY. CONF_DONE kwesịrị ịbụ 0, AVST_READY kwesịrị ịbụ 1. Echiche dị elu na ntụtụ a na-egosi na SDM dị njikere ịnakwere data sitere n'aka ndị ọbịa na-apụ apụ. Ihe mmepụta a bụ akụkụ nke SDM I/O.

Mara: Ntụtụ CONF_DONE na-egosi ndị ọbịa mpụga na mbufe bitstream na-aga nke ọma. Jiri akara ngosi ndị a naanị iji nyochaa usoro nhazi mgbawa zuru oke. Rụtụ aka na ntuziaka onye ọrụ nhazi Intel Agilex maka ozi ndị ọzọ na ntụtụ a.

Hazie DUT FPGA na Chip SOF zuru oke site na onye ọbịa na-apụ apụ Usoro na-esonụ na-akọwa ịhazi DUT FPGA na mgbawa SRAM ihe zuru ezu. File (.sof) na-eji onye ọbịa Avalon gụgharia interface:

  1. Dee bitstream mgbawa zuru ezu n'ime ebe nchekwa mpụga DDR4 nke onye enyemaka FPGA (onye ọbịa mpụga).
  2. Hazie DUT FPGA na mgbawa zuru ezu .sof site na iji Avalon streaming interface (x8, x16, x32).
  3. Gụọ akara ngosi nhazi DUT FPGA ọkwa. CONF_DONE kwesịrị ịbụ 1, AVST_READY kwesịrị ịbụ 0.

Nkọwa oge: Nhazigharị akụkụ akụkụ nke mpụga njikwa Intel FPGA IPintel-750856-Agilex-FPGA-Board Mmepe-FIG-1 (21)

Hazie DUT FPGA ya na Onye Mbụ site na Onye ọbịa Mpụga

  1. Tinye ifriizi na mpaghara PR ebumnuche na DUT FPGA.
  2. Iji Intel Quartus Prime System Console, kwupụta pr_request ka ịmalite nhazigharị akụkụ. AVST_READY kwesịrị ịbụ 1.
  3. Dee bitstream PR nke mbụ n'ime ebe nchekwa mpụga DDR4 nke onye enyemaka FPGA (onye ọbịa mpụga).
  4. Iji Avalon streaming interface (x8, x16, x32), megharịa DUT FPGA na onye mbụ bitstream.
  5. Iji nyochaa ọkwa PR, pịa Ngwaọrụ ➤ Sistemụ Console iji malite njikwa sistemụ. Na System Console, nyochaa ọkwa PR:
    • pr_error bụ 2-nhazigharị na usoro.
    • pr_error bụ 3 - nhazigharị ezuola.
  6. Tinye unfrize na mpaghara PR na DUT FPGA.

Mara: Ọ bụrụ na njehie emee n'oge ọrụ PR, dị ka ọdịda na nlele ụdị ma ọ bụ nlele ikike, ọrụ PR kwụsịrị.

Ozi metụtara

  • Ntuziaka onye ọrụ nhazi Intel Agilex
  • Ntuziaka onye ọrụ Intel Quartus Prime Pro Edition: Ngwaọrụ nbipu

Akụkọ ndozigharị akwụkwọ maka AN 991: Nhazigharị akụkụ site na ntụtụ nhazi (Onye ọbịa na-apụ apụ) Ntụgharị aka maka Intel Agilex F-Series FPGA Development Board

Ụdị akwụkwọ Intel Quartus Prime Version Mgbanwe
2022.11.14 22.3 • Ntọhapụ mbụ.

AN 991: Nhazigharị akụkụ site na ntunye nhazi (onye ọbịa na-apụ apụ) atụmatụ ntụaka: maka Intel Agilex F-Series FPGA Development Board

Azịza nye ajụjụ ndị kachasị elu:

  • Q Kedu ihe bụ PR site na ntụtụ nhazi?
  • A Nhazi onye ọbịa na mpụga na ibe 3
  • Q Kedu ihe m chọrọ maka nhazi ntụaka a?
  • A Ihe ndị chọrọ nrụtụ aka na ibe 6
  • Q Ebee ka m nwere ike nweta nhazi ntụaka?
  • A Ihe ndị chọrọ nrụtụ aka na ibe 6
  • Q Kedu ka m ga-esi eme PR site na nhazi mpụga?
  • A Ntụaka Nhazi Ntụaka na ibe 6
  • Q Kedu ihe bụ PR persona?
  • A Ịkọwapụta Ndị mmadụ na ibe 11
  • Q Kedu ka m ga-esi hazie bọọdụ?
  • A Hazie Board na ibe 17
  • Q Kedu ihe bụ nsogbu PR mara na njedebe?
  • A Nzukọ Nkwado Intel FPGA: PR
  • Q Ị nwere ọzụzụ na PR?
  • A Katalọgụ Ọzụzụ Nka na ụzụ Intel FPGA

Ụdị ntanetị Zipụ nzaghachi

  • ID: 750856
  • Ụdị: 2022.11.14

Akwụkwọ / akụrụngwa

intel 750856 Agilex FPGA Development Board [pdf] Ntuziaka onye ọrụ
750856, 750857, 750856 Agilex FPGA Development Board, Agilex FPGA Development Board, FPGA Development Board, Board Development Board, Board.

Ntụaka

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