Intel 750856 Agilex FPGA Development Board

Zambiri Zamalonda

Mapangidwe awa ndi a Intel Agilex F-Series FPGA Development Board. Imagwiritsa ntchito Partial Reconfiguration External Configuration Controller Intel FPGA IP ndipo ili ndi dera losavuta la PR. Intel Agilex Device External Host Hardware Setup imakhala ndi chipangizo chakunja (Helper FPGA), DUT FPGA, ndi mapangidwe anu akunja. Mapangidwe opangira mu chipangizo chakunja ali ndi udindo wochititsa ndondomeko ya PR. Zikhomo za PR zimagwiritsidwa ntchito kulumikiza zida zonse ziwiri ndipo zitha kukhala ma I/Os omwe alipo.

Malangizo Ogwiritsira Ntchito Zogulitsa

Kukonzekera Kwapanja Kwapanyumba

Kuti mupange kasinthidwe kagulu kakunja, tsatirani izi:

1. Pangani kapangidwe kake mu chipangizo chakunja kuti mugwiritse ntchito njira ya PR.
2. Lumikizani zikhomo za PR kuchokera ku chipangizo chakunja kupita ku Partial Reconfiguration External Configuration Controller Intel FPGA IP mu DUT FPGA.
3. Sanjani zosintha kuchokera pakupanga kwa wolandila kupita ku Intel Agilex Avalon yolumikizira mawonekedwe a ma pini omwe amafanana ndi ma sign a PR akugwirana chanza kuchokera ku IP.

Kukonzanso pang'ono kudzera pa Configuration Pins Operation

Zotsatirazi zikufotokozera momwe kukonzanso pang'ono kumagwirira ntchito pogwiritsa ntchito zikhomo zosinthira:

1. Nenani pini ya pr_request yolumikizidwa ndi Partial Reconfiguration External Configuration Controller Intel FPGA IP.
2. IP imatsimikizira chizindikiro chotanganidwa kusonyeza kuti ndondomeko ya PR ikuchitika (posankha).
3. Ngati dongosolo lokonzekera liri lokonzekera ntchito ya PR, pini ya avst_ready imatsimikiziridwa, kusonyeza kuti ndi yokonzeka kuvomereza deta.
4. Sakanizani zosintha za PR pazikhomo za avst_data ndi pini ya avst_valid, kutsatira kutsatsira kwa Avalon potengera kusamutsa deta ndi backpressure.
5. Kutsitsa kumayima pomwe avst_ready pin yatsitsidwa.
6. Chotsani avst_ready pin kusonyeza kuti palibenso deta yomwe ikufunika kuti mugwiritse ntchito PR.
7. The Partial Reconfiguration External Configuration Controller Intel FPGA IP imatsutsa chizindikiro chotanganidwa kusonyeza kutha kwa ndondomekoyi (posankha).

Kukonzanso Kwapang'ono kudzera pa Configuration Pins (External Host) Reference Design

Cholemba ichi chikuwonetsa kukonzanso pang'ono kudzera pamapini osinthira (wolandila wakunja) pa board yachitukuko ya Intel® Agilex® F-Series FPGA.

Reference Design Yathaview

Kukonzanso pang'ono (PR) kumakupatsani mwayi wokonzanso gawo la FPGA mwamphamvu, pomwe mapangidwe otsala a FPGA akupitilizabe kugwira ntchito. Mutha kupanga anthu angapo kudera linalake mumapangidwe anu omwe samakhudza magwiridwe antchito kumadera akunja kwa dera lino. Njira iyi ndiyothandiza pamakina omwe ntchito zingapo zimagawana nthawi yomweyo zida za FPGA. Mtundu wapano wa pulogalamu ya Intel Quartus® Prime Pro Edition imabweretsa njira yatsopano komanso yosavuta yophatikizira kuti ikonzedwenso pang'ono. Mapangidwe awa a Intel Agilex amagwiritsa ntchito Partial Reconfiguration External Configuration Controller Intel FPGA IP ndipo ali ndi dera losavuta la PR.

Kukonzekera kwa Hardware kwa Intel Agilex Chipangizo Chakunja

Kukonzekera Kwapanja Kwapanyumba

Mukusintha kwamakasitomala akunja, muyenera choyamba kupanga mapangidwe opangira mu chipangizo chakunja kuti mulandire njira ya PR, monga Intel Agilex Device External Host Hardware Setup ikuwonetsa. Kapangidwe kake kamene kamatengera kasinthidwe ka zikhomo za Intel Agilex Avalon zomwe zimagwirizana ndi ma sign a PR omwe amachokera ku Partial Reconfiguration External Configuration Controller Intel FPGA IP. Zikhomo za PR zomwe mumagwiritsa ntchito kulumikiza zida zonsezi zitha kukhala ma I/Os omwe alipo.

Mndandanda wotsatirawu ukufotokozeranso kukonzanso pang'ono pogwiritsa ntchito zikhomo zosinthira:

1. Choyamba tchulani pr_request pini yomwe imalumikizidwa ndi Partial Reconfiguration External Configuration Controller Intel FPGA IP.
2. IP imatsimikizira chizindikiro chotanganidwa kusonyeza kuti ndondomeko ya PR ikuchitika (posankha).
3. Ngati kasinthidwe kachitidwe kakonzeka kuchitidwa ntchito ya PR, avst_ready pin imatsimikiziridwa kusonyeza kuti yakonzeka kuvomereza deta.
4. Yambani kusuntha zosintha za PR pazikhomo za avst_data ndi pini ya avst_valid, mukuyang'ana momwe ma Avalon akukhamukira pakusinthana kwa data ndi backpressure.
5. Kutsatsa kumayimitsidwa nthawi iliyonse pomwe avst_ready pin ikachotsedwa.
6. Pambuyo potsitsa zosintha zonse, pini ya avst_ready imatsitsidwa kusonyeza kuti palibenso deta yomwe ikufunika kuti PR igwire ntchito.
7. The Partial Reconfiguration External Configuration Controller Intel FPGA IP imatulutsa siginecha yotanganidwa kuwonetsa kutha kwa njirayi (posankha).
8. Mutha kuyang'ana pr_done ndi pr_error pins kuti mutsimikizire ngati ntchito ya PR yatha bwino. Ngati cholakwika chichitika, monga kulephera pakuwunika kwa mtundu ndi kuwunika chilolezo, ntchito ya PR imathetsedwa.

Zambiri Zogwirizana

• Intel Agilex F-Series FPGA Development Kit Web Tsamba
• Intel Agilex F-Series FPGA Development Kit User Guide
• Intel Quartus Prime Pro Edition User Guide: Kusintha Kwapang'ono

Kukonzanso Kwapang'ono Kwakunja Kowongolera Kunja kwa Intel FPGA IP
The Partial Reconfiguration External Configuration Controller ikufunika kuti igwiritse ntchito zikhomo zosinthira kuti zitsitse deta ya PR pa ntchito ya PR. Muyenera kulumikiza madoko onse apamwamba a Partial Reconfiguration External Configuration Controller Intel FPGA IP ku pr_request pini kuti mulole kugwirana chanza kwa wolandirayo ndi woyang'anira chipangizo chotetezedwa (SDM) kuchokera pakati. SDM imatsimikizira kuti ndi mitundu yanji ya mapini oti mugwiritse ntchito, malinga ndi makonda anu a MSEL.

Kukonzanso Kwapang'ono Kwakunja Kowongolera Kunja kwa Intel FPGA IP

Kukonzanso Kwapang'ono Zokonda Zakunja Zowongolera Zosintha

Parameter	Mtengo	Kufotokozera
Yambitsani Busy Interface	Yambitsani or Letsani	Imakulolani Kuti Muyatse kapena Kuletsa mawonekedwe a Busy, omwe amawonetsa chizindikiro chosonyeza kuti kukonza kwa PR kukuchitika panthawi yakusintha kwakunja. Kukhazikitsa kofikira ndiko Letsani.

Kukonzekera Kwapang'ono Kwa Madoko Oyang'anira Zosintha Zakunja

Dzina la Port	M'lifupi	Mayendedwe	Ntchito
pr_request	1	Zolowetsa	Zikusonyeza kuti ndondomeko ya PR yakonzeka kuyamba. Chizindikirocho ndi njira yosagwirizana ndi chizindikiro cha wotchi iliyonse.
pr_error	2	Zotulutsa	Zikuwonetsa cholakwika pang'ono pokonzanso.: • 2'b01—zolakwika zonse za PR • 2'b11—cholakwika cha bitstream chosagwirizana Zizindikirozi ndi njira zomwe sizikugwirizana ndi gwero lililonse la wotchi.
pr_done	1	Zotulutsa	Zimasonyeza kuti ndondomeko ya PR yatha. Chizindikirocho ndi njira yosagwirizana ndi chizindikiro cha wotchi iliyonse.
kuyamba_addr	1	Zolowetsa	Imatchula adilesi yoyambira ya data ya PR mu Active Serial Flash. Mumathandizira chizindikirochi posankha kapena Avalon®-ST or Active seri za Yambitsani Avalon-ST Pins kapena Active Serial Pins parameter. Chizindikirocho ndi njira yosagwirizana ndi chizindikiro cha wotchi iliyonse.
khazikitsaninso	1	Zolowetsa	Chizindikiro chokhazikika chapamwamba, chosinthika.
kunja_clk	1	Zotulutsa	Gwero la wotchi lomwe limapanga kuchokera ku oscillator yamkati.
tanganidwa	1	Zotulutsa	IP imatsimikizira chizindikiro ichi kusonyeza kusamutsa deta ya PR kukuchitika. Mukuyatsa chizindikirochi posankha Yambitsani za Yambitsani mawonekedwe otanganidwa parameter.

Reference Design Zofunikira

Kugwiritsa ntchito kachipangizo kameneka kumafuna zotsatirazi:

• Kuyika kwa Intel Quartus Prime Pro Edition 22.3 mothandizidwa ndi banja la chipangizo cha Intel Agilex.
• Kulumikizana ndi Intel Agilex F-Series FPGA board board pa benchi.
• Kutsitsa kwa kapangidwe kakaleampndikupezeka pamalo otsatirawa: https://github.com/intel/fpga-partial-reconfig.

Kutsitsa kapangidwe exampLe:

1. Dinani Clone kapena tsitsani.
2. Dinani Tsitsani ZIP. Tsegulani fpga-partial-reconfig-master.zip file.
3. Yendetsani ku maphunziro/agilex_external_pr_configuration kafoda kakang'ono kuti mupeze zolembera.

Reference Design Walkthrough

Masitepe otsatirawa akufotokozera kukhazikitsidwa kwa kukonzanso pang'ono pogwiritsa ntchito zikhomo zosinthira (wolandila wakunja) pa board yachitukuko ya Intel Agilex F-Series FPGA:

• Gawo 1: Kuyambapo
• Gawo 2: Kupanga Gawo Lopanga
• Gawo 3: Kugawa Magawo Oyikira ndi Njira Zolowera
• Gawo 4: Kuonjezera Partial Reconfiguration External Configuration Controller IP
• Gawo 5: Kufotokozera Anthu
• Gawo 6: Kupanga Zosintha
• Gawo 7: Kupanga Base Revision
• Gawo 8: Kukonzekera Kukonzanso kwa PR
• Gawo 9: Kupanga Board

Gawo 1: Chiyambi
Kukopera mawonekedwe ofotokozera files kumalo anu ogwirira ntchito ndikupanga blinking_led flat design:

1. Pangani chikwatu pamalo omwe mukugwira ntchito, agilex_pcie_devkit_blinking_led_pr.
2. Koperani maphunziro otsitsidwa/agilex_pcie_devkit_blinking_led/flat sub-folder ku bukhu, agilex_pcie_devkit_blinking_led_pr.
3. Mu pulogalamu ya Intel Quartus Prime Pro Edition, dinani File ➤ Tsegulani Project ndikusankha blinking_led.qpf.
4. Kuti mumve zambiri za kamangidwe ka nyumba yathyathyathya, dinani Kukonza ➤ Yambani ➤ Yambitsani Kusanthula & Kaphatikizidwe. Kapenanso, pa mzere wolamula, yendetsani lamulo ili: quartus_syn blinking_led -c blinking_led

Kupanga Gawo Lopanga

Muyenera kupanga magawo opangira gawo lililonse la PR lomwe mukufuna kukonzanso pang'ono. Masitepe otsatirawa amapanga gawo lopangira mawonekedwe a u_blinking_led.

Kupanga Magawo Opanga

1. Dinani kumanja chithunzi cha u_blinking_led mu Project Navigator ndikudina Design Partition ➤ Reconfigurable. Chizindikiro cha magawo opangira chimawonekera pafupi ndi chochitika chilichonse chomwe chimayikidwa ngati gawo.
2. Dinani Ntchito ➤ Zenera la Magawo Opanga. Iwindo likuwonetsa magawo onse apangidwe mu polojekitiyi.
3. Sinthani dzina la magawo mu Window ya Design Partitions podina kawiri dzinalo. Pamapangidwe awa, sinthani dzina logawa kukhala pr_partition
   • Zindikirani: Mukapanga magawo, pulogalamu ya Intel Quartus Prime imangopanga dzina logawa, kutengera dzina lachitsanzo ndi njira yautsogoleri. Dzina losasinthikali limatha kusiyanasiyana pazochitika zilizonse.
4. Kuti mutumize gawo lomalizidwa lokhazikika kuchokera pazokonzanso zoyambira, dinani kawiri kulowa kwa root_partition mu Post Final Export. File column, ndi kulemba blinking_led_static. gdb.

Kutumiza Zithunzi Zomaliza Zomaliza mu Window Yopanga MagawoTsimikizirani kuti blinking_led.qsf ili ndi ntchito zotsatirazi, zogwirizana ndi gawo lanu lokonzekeranso:

Zambiri Zogwirizana
"Pangani Magawo Opanga" mu Intel Quartus Prime Pro Edition Wogwiritsa Ntchito: Kukonzanso pang'ono

Kugawa Magawo ndi Njira Yoyendetsera Gawo la PR
Pakusintha kulikonse komwe mumapanga, mawonekedwe a PR amayika maziko ofananirako m'chigawo chanu cha PR. Kupeza ndi kugawa dera la PR mu pulani ya chipangizocho kuti muwunikenso:

1. Dinani kumanja chithunzi cha u_blinking_led mu Project Navigator ndikudina Logic Lock Dera ➤ Pangani Chigawo Chatsopano Chokhoma. Derali likuwonekera pawindo la Logic Lock Regions.
2. Dera lanu liyenera kutsekereza blinking_led logic. Sankhani dera loyikapo popeza node mu Chip Planner. Dinani kumanja dzina la dera la u_blinking_led pawindo la Logic Lock Regions ndikudina

Pezani Node ➤ Pezani mu Chip Planner. Dera la u_blinking_led ndi lamitundu

Chip Planner Node Location ya blinking_led

1. Pazenera la Logic Lock Regions, tchulani magawo omwe akhazikitsidwa pagawo la Origin. Zoyambira zimagwirizana ndi ngodya ya kumanzere kwa dera. Za example, kukhazikitsa chigawo chokhazikitsidwa ndi (X1 Y1) chogwirizanitsa monga (163 4), tchulani Origin monga X163_Y4. Mapulogalamu a Intel Quartus Prime amawerengera okha ma (X2 Y2) ogwirizanitsa (kumanja-kumanja) kwa malo oyikapo, kutengera kutalika ndi m'lifupi zomwe mumatchula.
   • Zindikirani: Phunziroli limagwiritsa ntchito (X1 Y1) zogwirizanitsa - (163 4), ndi kutalika ndi m'lifupi mwake 20 pa malo oyikapo. Tanthauzirani mtengo uliwonse wagawo loyika. Onetsetsani kuti chigawochi chili ndi blinking_led logic.
2. Yambitsani zosankha Zosungidwa ndi Zofunika Kwambiri.
3. Dinani kawiri kusankha kwa Routing Region. Bokosi la zokambirana la Logic Lock Routing Region Settings likuwonekera.
4. Sankhani Zokhazikika ndi kukulitsa kwa mtundu wa Routing. Kusankha njira iyi kumangowonjezera kutalika kwa 2.
   • Zindikirani: Dera lolowera liyenera kukhala lokulirapo kuposa malo oikirako, kuti apereke kusinthasintha kowonjezera kwa Fitter injini ikadutsa anthu osiyanasiyana.

Zenera la Magawo a Logic LockTsimikizirani kuti blinking_led.qsf ili ndi ntchito zotsatirazi, zogwirizana ndi kupanga kwanu:

Zambiri Zogwirizana
"Floorplan the Partial Reconfiguration Design" mu Intel Quartus Prime Pro Edition User Guide: Kusintha Kwapang'ono

Powonjezera Kukonzanso Kwapang'ono Kukonzanso Kwakunja kwa Intel FPGA IP
The Partial Reconfiguration External Configuration Controller Intel FPGA IP imalumikizana ndi Intel Agilex PR block block kuti isamalire gwero la bitstream. Muyenera kuwonjezera IP iyi pamapangidwe anu kuti mugwiritse ntchito masinthidwe akunja. Tsatirani izi kuti muwonjezere Chowongoleredwa Chapang'ono Kukonzanso Kwakunja
Intel FPGA IP ku polojekiti yanu:

1. Lembani Kusintha Mwapang'ono mu gawo lakusaka la IP Catalog (Zida ➤ IP Catalog).
2. Dinani kawiri kagawo kakang'ono Kukonzanso Kunja kwa Intel FPGA IP.
3. Mu bokosi la bokosi la Pangani IP Variant, lembani external_host_pr_ip monga File dzina, ndiyeno dinani Pangani. The parameter editor ikuwonekera.
4. Kwa Yambitsani mawonekedwe otanganidwa, sankhani Khutsani (zokhazikika). Mukafuna kugwiritsa ntchito chizindikirochi, mutha kusintha zoikamo kuti Yambitsani.

Yambitsani Busy Interface Parameter mu Parameter Editor

1. Dinani File ➤ Sungani ndikutuluka mkonzi popanda kupanga makinawo. Zosintha za parameter zimapanga zakunja_host_pr_ip.ip kusintha kwa IP file ndi kuwonjezera file ku blinking_led project. AN 991: Kukonzanso Kwapang'ono Kupyolera M'mapini Okonzekera (Othandizira Akunja) Reference Design 750856 | 2022.11.14 AN 991:
   • Zindikirani:
   • a. Ngati mukukopera external_host_pr_ip.ip file kuchokera ku chikwatu cha pr, sinthani pamanja blinking_led.qsf file kuphatikiza mzere wotsatirawu: set_global_assignment -name IP_FILE pr_ip.ip
   • b. Ikani IP_FILE ntchito pambuyo pa SDC_FILE ntchito (blinking_led. dc) mu blinking_led.qsf yanu file. Kuyitanitsa uku kumatsimikizira kukakamizidwa koyenera kwa Partial Reconfiguration Controller IP pachimake.
   • Zindikirani: Kuti muwone mawotchi, .sdc file pakuti PR IP iyenera kutsatira .sdc iliyonse yomwe imapanga mawotchi omwe IP core imagwiritsa ntchito. Mumawongolera dongosololi powonetsetsa kuti .ip file pakuti PR IP core imawonekera pambuyo pa .ip iliyonse files kapena .sdc filezomwe mumagwiritsa ntchito kutanthauzira mawotchi awa mu .qsf file pakusintha kwanu kwa Intel Quartus Prime project. Kuti mumve zambiri, onani Buku Logwiritsa Ntchito Mayankho a IP a Partial Reconfiguration.

Kusintha Mapangidwe Apamwamba

Kusintha pamwamba.sv file ndi PR_IP chitsanzo:

1. Kuti muwonjezere chitsanzo cha external_host_pr_ip pamapangidwe apamwamba, tsitsani midadada yotsatirayi mu top.sv file:

Kufotokozera Anthu
Mapangidwe awa amatanthauzira anthu atatu osiyana pagawo limodzi la PR. Kufotokozera ndi kuphatikiza anthu mu polojekiti yanu:

1. Pangani atatu SystemVerilog files, blinking_led.sv, blinking_led_slow.sv, ndi blinking_led_empty.sv m'ndandanda yanu yogwirira ntchito kwa anthu atatuwo.

Reference Design Personas

Zindikirani:

• blinking_led.sv ilipo kale ngati gawo la files mumakopera kuchokera ku flat / sub-directory. Mutha kugwiritsanso ntchito izi file.
• Ngati mupanga SystemVerilog files kuchokera ku Intel Quartus Prime Text Editor, zimitsani Add file kuti musankhe polojekiti yamakono, mukasunga fayilo ya files.

Kupanga Zosintha

Kuyenda kwa mapangidwe a PR kumagwiritsa ntchito zomwe zasinthidwa pulojekiti mu pulogalamu ya Intel Quartus Prime. Mapangidwe anu oyambilira ndikuwunikiranso koyambira, komwe mumafotokozera malire amadera osakhazikika komanso zigawo zomwe zingasinthidwenso pa FPGA. Kuchokera pakusintha koyambira, mumapanga zosintha zingapo. Zosinthazi zili ndi machitidwe osiyanasiyana a zigawo za PR. Komabe, zosintha zonse za PR zimagwiritsa ntchito kuyika kwapamwamba komweko ndi zotsatira zamayendedwe kuchokera pakuwunikiridwa koyambira. Kuti mupange mapangidwe a PR, muyenera kupanga kukonzanso kwa PR kwa munthu aliyense. Kuphatikiza apo, muyenera kugawa mitundu yowunikanso pakusintha kulikonse. Mitundu yokonzanso yomwe ilipo ndi:

• Kusintha pang'ono - Base
• Kusintha Kwapang'ono - Kukhazikitsa Kwamunthu

Gome lotsatirali lili ndi dzina lokonzanso ndi mtundu wokonzanso pakusintha kulikonse:

Mayina Obwereza ndi Mitundu

Dzina Lokonzanso	Mtundu Wokonzanso
blinking_led.qsf	Kusintha pang'ono - Base
blinking_led_default.qsf	Kusintha Kwapang'ono - Kukhazikitsa Kwamunthu
blinking_led_slow.qsf	Kusintha Kwapang'ono - Kukhazikitsa Kwamunthu
blinking_led_empty.qsf	Kusintha Kwapang'ono - Kukhazikitsa Kwamunthu

Kukhazikitsa Base Revision Type

1. Dinani Ntchito ➤ Zosintha.
2. Mu Revision Name, sankhani blinking_led revision, ndiyeno dinani Set Current.
3. Dinani Ikani. Blinking_led revision ikuwoneka ngati kusinthidwa kwamakono.
4. Kuti mukhazikitse Mtundu wa Kukonzanso kwa blinking_led, dinani Ntchito ➤ Zikhazikiko ➤ Zambiri.
5. Pa Mtundu Wokonzanso, sankhani Kusintha pang'ono - Base, kenako dinani OK.
6. Tsimikizirani kuti blinking_led.qsf tsopano ili ndi ntchito iyi: ##blinking_led.qsf set_global_assignment -name REVISION_TYPE PR_BASE

Kupanga Zokonzanso Zothandizira

1. Kuti mutsegule bokosi lakuti Revisions dialog box, dinani Project ➤ Revisions.
2. Kuti mupange kukonzanso kwatsopano, dinani kawiri < >.
3. Mu dzina la Revision, tchulani blinking_led_default ndikusankha blinking_led for Based on revision.
4. Pamtundu wa Revision, sankhani Kusintha Kwapang'ono - PersonaImplementation.

Kupanga Zosintha

1. Mofananamo, ikani mtundu wa Revision kuti blinking_led_slow ndi blinking_led_empty revisions.
2. Tsimikizirani kuti iliyonse .qsf file tsopano ili ndi ntchito yotsatirayi: set_global_assignment -name REVISION_TYPE PR_IMPL set_instance_assignment -name ENTITY_REBINDING \ place_holder -to u_blinking_led kumene, place_holder ndi dzina losakhazikika la chiwongolero cha PR chomwe changopangidwa kumene.

Zosintha za Project

Kupanga Base Revision

1. Kuti mupange kubwereza koyambira, dinani Processing ➤ Yambani Kuphatikiza. Kapenanso, lamulo lotsatirali limapanga kukonzanso koyambira: quartus_sh -flow compile blinking_led -c blinking_led
2. Onani bitstream filezomwe zimapanga mu output_files chikwatu.

Zapangidwa Files

Dzina	Mtundu	Kufotokozera
blinking_led.sof	Base mapulogalamu file	Amagwiritsidwa ntchito pakusintha kwathunthu kwa chip base
blinking_led.pr_partition.rbf	PR pang'ono file kwa base persona	Amagwiritsidwa ntchito pakukonzanso pang'ono kwa base persona.
blinking_led_static.qdb	.qdb database file	Database yomaliza file amagwiritsidwa ntchito kuitanitsa dera lokhazikika.

Zambiri Zogwirizana

• "Floorplan the Partial Reconfiguration Design" mu Intel Quartus Prime Pro Edition User Guide: Kusintha Kwapang'ono
• "Kugwiritsa Ntchito Zoletsa za Floorplan Mochulukira" mu Intel Quartus Prime Pro Edition User Guide: Kukonzanso Kwapang'ono

Kukonzekera Kukonzanso kwa PR
Muyenera kukonzekera kukonzanso kwa PR musanayambe kupanga ndi kupanga PR bitstream ya mapulogalamu a chipangizo. Kukonzekera uku kumaphatikizapo kuwonjezera static region .qdb file monga gwero file pakuwunikiridwa kulikonse. Kuphatikiza apo, muyenera kufotokoza gulu logwirizana la PR.

1. Kuti mukhazikitse zomwe zasinthidwa, dinani Project ➤ Revisions, sankhani blinking_led_default ngati dzina la Revision, ndiyeno dinani Set Current.
2. Kuti mutsimikize gwero lolondola pakusintha kulikonse, dinani Pulojekiti ➤Onjezani/Chotsani Files mu Project. The blinking_led.sv file zikuwoneka mu file mndandanda.

FilesPage

1. Bwerezani masitepe 1 mpaka 2 kuti mutsimikize gwero lina lokonzanso files:

Dzina Lokonzanso Kachitidwe	Gwero File
blinking_led_default	blinking_led.sv
blinking_led_empty	blinking_led_empty.sv
blinking_led_slow	blinking_led_slow.sv

1. Kuti mutsimikizire .qdb file Zogwirizana ndi magawo a mizu, dinani Ntchito ➤ Zenera la Magawo Opanga. Tsimikizirani kuti Partition Database File imatchula blinking_led_static.qdb file, kapena dinani kawiri Partition Database File cell kuti mufotokoze izi file. Kapenanso, lamulo lotsatirali limapereka izi file: set_instance_assignment -name QDB_FILE_GAWO \ blinking_led_static.qdb -to |
2. Mu selo Lomangiriranso Bungwe, tchulani dzina la gulu la gawo lililonse la PR lomwe mumasintha pokonzanso kukhazikitsa. Pakusintha kwa blinking_led_default kukhazikitsa, dzina labungwe ndi blinking_led. Mu phunziro ili, mumalemba pamwamba chitsanzo cha u_blinking_led kuchokera muzosinthidwa zoyambira ndi gulu latsopano la blinking_led.

Zindikirani: Ntchito yosungiranso malo imawonjezedwa pakuwunikiridwako kokhazikika. Komabe, muyenera kusintha dzina lachinthu losakhazikika muntchitoyo kukhala dzina loyenera lakapangidwe kanu.

Dzina Lokonzanso Kachitidwe	Kumanganso Bungwe
blinking_led_default	blinking_led
blinking_led_slow	blinking_led_slow
blinking_led_empty	blinking_led_empty

Kubwezeretsanso Bungwe

1. Kuti mupange mapangidwewo, dinani Kukonza ➤ Yambani Kuphatikiza. Kapenanso, lamulo lotsatirali likupanga polojekitiyi: quartus_sh -flow compile blinking_led -c blinking_led_default
2. Bwerezani masitepe omwe ali pamwambapa kuti mukonzekere blinking_led_slow and blinking_led_empty revisions: quartus_sh -flow compile blinking_led -c blinking_led_slow quartus_sh -flow compile blinking_led -c blinking_led_empt

Zindikirani: Mutha kutchula makonda aliwonse a Fitter omwe mukufuna kugwiritsa ntchito popanga PR. Zokonda zenizeni zimangokhudza mawonekedwe amunthu, osakhudza gawo lomwe latumizidwa kunja.

Kupanga Board
Phunziroli limagwiritsa ntchito bolodi lachitukuko la Intel Agilex F-Series FPGA pa benchi, kunja kwa kagawo ka PCIe * mumakina anu ochezera. Musanakonzekere bolodi, onetsetsani kuti mwamaliza izi:

1. Lumikizani magetsi ku Intel Agilex F-Series FPGA board board.
2. Lumikizani Chingwe Chotsitsa cha Intel FPGA pakati pa doko la USB la PC yanu ndi doko la Intel FPGA Tsitsani Cable pa bolodi lachitukuko.

Kuyendetsa kapangidwe ka Intel Agilex F-Series FPGA board:

1. Tsegulani pulogalamu ya Intel Quartus Prime ndikudina Zida ➤ Programmer.
2. Mu Programmer, dinani Hardware Setup ndikusankha USB-Blaster.
3. Dinani Auto Detect ndikusankha chipangizocho, AGFB014R24AR0.
4. Dinani Chabwino. Pulogalamu ya Intel Quartus Prime imazindikira ndikusintha Programmer ndi zida zitatu za FPGA pa bolodi.
5. Sankhani chipangizo cha AGFB014R24AR0, dinani Sinthani File ndi kutsegula blinking_led_default.sof file.
6. Yambitsani Pulogalamu/Sinthani kuti blinking_led_default.sof file.
7. Dinani Start ndikudikirira kuti bar ifike 100%.
8. Yang'anani ma LED omwe ali pa bolodi akuthwanima pafupipafupi monga momwe amapangidwira koyambira.
9. Kuti mukonze chigawo cha PR chokha, dinani kumanja blinking_led_default.sof file mu Programmer ndikudina Add PR Programming File.
10. Sankhani blinking_led_slow.pr_partition.rbf file.
11. Letsani Pulogalamu/Sinthani za blinking_led_default.sof file.
12. Yambitsani Pulogalamu/Sinthani kuti blinking_led_slow.pr_partition.rbf file ndi kumadula Start. Pa bolodi, onani LED[0] ndi LED[1] zikupitiriza kuphethira. Mipiringidzo ikafika 100%, LED[2] ndi LED[3] imapenya pang'onopang'ono.
13. Kuti mukonzenso dera la PR, dinani kumanja kwa .rbf file mu Programmer ndikudina Change PR Programing File.
14. Sankhani .rbf filekwa anthu ena awiri kuti awone zomwe zikuchitika pa bolodi. Kutsegula blinking_led_default.rbf file zimapangitsa ma LED kuti aziphethira pafupipafupi, ndikutsegula blinking_led_empty.rbf file zimapangitsa ma LED kukhala ON.

Kukonza Intel Agilex F-Series FPGA Development BoardKuyenda Kuyesa kwa Hardware

Zotsatirazi zikufotokoza za kayendedwe ka kuyesa kwa hardware.
Kukonzekera kwa Hardware kwa Intel Agilex Chipangizo Chakunja

Konzani Wothandizira FPGA (Wothandizira Wakunja)
Mndandanda wotsatirawu ukufotokozerani za FPGA yothandizira FPGA yomwe imagwira ntchito ngati PR process host host:

1. Tchulani zochunira za mawonekedwe a Avalon omwe amagwirizana ndi momwe mwasankha (x8, x16, kapena x32).
2. Yambitsani nsanja pokonza wothandizira FPGA pogwiritsa ntchito Intel Quartus Prime Programmer ndi chingwe cholumikizira cholumikizira.
3. Pogwiritsa ntchito wothandizira FPGA, werengani ma sigino a CONF_DONE ndi AVST_READY. CONF_DONE ikuyenera kukhala 0, AVST_READY ikhale 1. Mfundo zomveka bwino pa piniyi zikuwonetsa kuti SDM ndiyokonzeka kulandila data kuchokera kwa wolandira wakunja. Kutulutsa uku ndi gawo la SDM I/O.

Zindikirani: Pini ya CONF_DONE imayimira wolandira wakunja kuti kusamutsa kwa bitstream kwayenda bwino. Gwiritsani ntchito zizindikirozi kuti muyang'ane ndondomeko yonse ya kasinthidwe ka chip. Onani ku Intel Agilex Configuration User Guide kuti mudziwe zambiri pa pini iyi.

Konzani pulogalamu ya DUT FPGA yokhala ndi Full Chip SOF kudzera pa External Host File (.sof) pogwiritsa ntchito mawonekedwe ochezera a Avalon:

1. Lembani zonse chip bitstream mu DDR4 kukumbukira kunja kwa wothandizira FPGA (wolandira akunja).
2. Konzani DUT FPGA ndi chip chathunthu .sof pogwiritsa ntchito mawonekedwe a Avalon akukhamukira (x8, x16, x32).
3. Werengani masinthidwe a DUT FPGA masinthidwe. CONF_DONE ikuyenera kukhala 1, AVST_READY ikhale 0.

Kufotokozera Kwanthawi: Kusintha Kwapang'ono Kukonzanso Kwakunja kwa Intel FPGA IP

Konzani DUT FPGA ndi Munthu Woyamba kudzera mwa Wolandila Wakunja

1. Ikani zoziziritsa kudera lomwe mukufuna PR ku DUT FPGA.
2. Pogwiritsa ntchito Intel Quartus Prime System Console, tsimikizirani pr_request kuti muyambe kukonzanso pang'ono. AVST_READY iyenera kukhala 1.
3. Lembani PR persona bitstream yoyamba mu DDR4 kukumbukira kunja kwa wothandizira FPGA (wolandira kunja).
4. Pogwiritsa ntchito mawonekedwe a Avalon (x8, x16, x32), sinthaninso DUT FPGA ndi mtundu woyamba wa persona.
5. Kuti muwone momwe PR ilili, dinani Zida ➤ System Console kuti mutsegule System Console. Mu System Console, yang'anani mawonekedwe a PR:
   • pr_error ndi 2-kukonzanso kukuchitika.
   • pr_error ndi 3-kukonzanso kwatha.
6. Ikani kuzizira kudera la PR ku DUT FPGA.

Zindikirani: Ngati cholakwika chikachitika pakugwira ntchito kwa PR, monga kulephera pakuwunika kapena kuyang'ana chilolezo, ntchito ya PR imatha.

Zambiri Zogwirizana

• Intel Agilex Configuration User Guide
• Intel Quartus Prime Pro Edition User Guide: Debug Tools

Mbiri Yokonzanso Zolemba za AN 991: Kukonzanso Mwapang'ono kudzera pa Configuration Pins (External Host) Reference Design for Intel Agilex F-Series FPGA Development Board

Document Version	Intel Quartus Prime Version	Zosintha
2022.11.14	22.3	• Kutulutsidwa koyamba.

AN 991: Kukonzanso Kwapang'ono kudzera pa Zikhomo Zosinthira (Wogwiritsa Wakunja) Reference Design: kwa Intel Agilex F-Series FPGA Development Board

Mayankho a Mafunso Ofunsidwa Kawirikawiri:

• Q Kodi PR kudzera pa zikhomo zosinthira ndi chiyani?
• A Kukonzekera kwa Olandira Akunja patsamba 3
• Q Kodi ndifunika chiyani pazapangidwe zolozerazi?
• A Zofunikira Zopangira Reference patsamba 6
• Q Kodi ndingapeze kuti zofotokozera?
• A Zofunikira Zopangira Reference patsamba 6
• Q Kodi ndimapanga bwanji PR pogwiritsa ntchito kasinthidwe kakunja?
• A Reference Design Walkthrough patsamba 6
• Q Kodi PR persona ndi chiyani?
• A Kufotokozera Anthu patsamba 11
• Q Kodi ndingapange bwanji board?
• A Konzani Bungwe patsamba 17
• Q Kodi ndi zovuta ziti za PR ndi zolepheretsa?
• A Intel FPGA Support Forums: PR
• Q Kodi mumaphunzitsidwa za PR?
• A Intel FPGA Technical Training Catalog

Paintaneti Tumizani Ndemanga

• ID: 750856
• Mtundu: 2022.11.14

Zolemba / Zothandizira

Intel 750856 Agilex FPGA Development Board [pdf] Buku Logwiritsa Ntchito 750856, 750857, 750856 Agilex FPGA Development Board, Agilex FPGA Development Board, FPGA Development Board, Development Board, Board

Maumboni

• Buku Logwiritsa Ntchito