intel 750856 Agilex FPGA Development Board
Fa'amatalaga o oloa
O lenei mamanu fa'asino mo le Intel Agilex F-Series FPGA Development Board. O lo'o fa'aogaina le Fa'atonu Fa'apitoa Fa'apitoa Fa'atonu Fa'atonu Intel FPGA IP ma e iai se vaega faigofie PR. O le Intel Agilex Device External Host Hardware Setup e aofia ai se masini i fafo (Fesoasoani FPGA), se DUT FPGA, ma lau mamanu talimalo fafo. O le mamanu talimalo i totonu o le masini fafo e nafa ma le faʻafeiloaʻi o le PR process. O pine PR e fa'aoga e fa'afeso'ota'i ai masini e lua ma e mafai ona avea ma so'o se fa'aoga avanoa I/Os.
Fa'atonuga o le Fa'aaogaina o Mea
Fa'atonuga o Talimalo i fafo
Ina ia fa'atinoina le fa'atulagaina o le talimalo i fafo, mulimuli i laasaga nei:
- Fausia se mamanu talimalo i totonu o se masini fafo e faʻafeiloaʻi ai le faiga o le PR.
- Faʻafesoʻotaʻi pine PR mai le masini fafo i le Partial Reconfiguration External Configuration Controller Intel FPGA IP i le DUT FPGA.
- Fa'asalalauina fa'amaumauga mai le fa'ailoga talimalo i le Intel Agilex Avalon fa'afefeina fa'aoga pine e fetaui ma fa'ailoga lima lima PR mai le IP.
Vaega Toefa'atonu e ala ile Fa'agaioiga Pins
O le fa'asologa o lo'o i lalo o lo'o fa'amatalaina ai le fa'agaioiga o vaega toe fa'aopoopo e ala i pine fa'atulagaina:
- Fa'amau le pine pr_request e feso'ota'i ma le Vaega Fa'atonu Fa'atonu Fa'atonu Pule Intel FPGA IP.
- O loʻo faʻaalia e le IP se faʻailoga pisi e faʻaalia ai o loʻo faʻagasolo le faiga o le PR (filifiliga).
- Afai ua saunia le faiga faʻatulagaina mo se galuega PR, o le avst_ready pine ua faʻamaonia, e faʻaalia ai ua sauni e talia faʻamatalaga.
- Fa'asolo atu fa'amaumauga a le PR i luga o pine avst_data ma le pine avst_valid, e mulimuli i le fa'asologa o le fa'asologa o Avalon mo le fa'aliliuina o fa'amatalaga ma le fa'aoso i tua.
- E taofi le tafega pe a le toe fa'amaonia le pine avst_ready.
- Fa'amama le pine avst_ready e fa'ailoa ai e le toe mana'omia ni fa'amatalaga mo le fa'atinoga o le PR.
- Le Fa'atonu Fa'atonu Fa'apitoa Fa'atonu Pule Intel FPGA IP fa'amanino le fa'ailoga pisi e fa'ailoa ai le fa'ai'uga o le fa'agasologa (filifiliga).
Toe Fa'atonu Fa'apitoa e ala i Pin Fa'atonu (Fa'aui i fafo) Fa'ailoga Fa'asinomaga
O lenei tusi talosaga o lo'o fa'aalia ai le toe fa'atulagaina o se vaega e ala i pine fa'atulagaina (fa'aoga i fafo) i luga o le Intel® Agilex® F-Series FPGA development board.
Fa'asinoga Design Overview
O le vaega reconfiguration (PR) vaega e mafai ai ona e toe fetuutuunai se vaega o le FPGA dynamically, ae o le FPGA design o loo faaauau pea ona galue. E mafai ona e faia ni tagata se tele mo se itulagi patino i lau mamanu e le afaina ai le gaioiga i vaega i fafo atu o lenei itulagi. O lenei metotia e aoga i faiga e tele galuega fa'atino taimi-fa'asoa tutusa punaoa masini FPGA. O le fa'asologa o lo'o i ai nei o le Intel Quartus® Prime Pro Edition software ua fa'ailoa mai ai se fa'asologa fou ma fa'afaigofie mo le toe fa'atulagaina o vaega. O lenei Intel Agilex reference design e fa'aogaina ai le Partial Reconfiguration External Configuration Controller Intel FPGA IP ma e iai se vaega faigofie PR.
Intel Agilex Device Seti Meafaigaluega Fa'aui i fafo
Fa'atonuga o Talimalo i fafo
I le faʻatulagaina o talimalo i fafo, e tatau ona e faia muamua se mamanu talimalo i totonu o se masini fafo e faʻafeiloaʻi ai le PR process, e pei ona faʻaalia e le Intel Agilex Device External Host Hardware Setup. O le mamanu talimalo o loʻo faʻasalalau faʻamaumauga o faʻamaumauga i le Intel Agilex Avalon streaming interface pine e fetaui ma faailoilo faʻafeiloaʻi PR e sau mai le Partial Reconfiguration External Configuration Controller Intel FPGA IP. O pine PR e te fa'aogaina e fa'afeso'ota'i ai masini e lua e mafai ona avea ma so'o se I/Os fa'aoga avanoa.
O le fa'asologa o lo'o i lalo o lo'o fa'amatalaina ai le toe fa'atulagaina o vaega e ala i fa'agaioiga pine fa'atulagaina:
- Fa'ailoa muamua le pine pr_request o lo'o feso'ota'i ma le Fa'atonu Fa'atonu Fa'apitoa Fa'atonu Pule Intel FPGA IP.
- O loʻo faʻaalia e le IP se faʻailoga pisi e faʻaalia ai o loʻo faʻagasolo le faiga o le PR (filifiliga).
- Afai ua sauni le faiga faʻatulagaina e faʻatino se galuega PR, o le avst_ready pine o loʻo faʻamaonia e faʻaalia ai ua sauni e talia faʻamatalaga.
- Amata ona fa'asalalau fa'amaumauga fa'atulagaina o le PR i luga o pine avst_data ma le pine avst_valid, a'o mata'ituina le fa'asologa o le fa'aosoina o Avalon mo le fa'aliliuina atu o fa'amatalaga ma le fa'amautu.
- E taofi le tafe i so'o se taimi e te'a ai le pine avst_ready.
- A maeʻa faʻasalalau faʻamaumauga uma, o le avst_ready pine e faʻamalo e taʻu mai ai e le toe manaʻomia ni faʻamatalaga mo le PR.
- O le Vaega Fa'atonu Fa'atonu Fa'atonu Fa'atonu Pule Intel FPGA IP fa'amamafa le fa'ailoga pisi e fa'ailoa ai le i'uga o le fa'agasologa (filifiliga).
- E mafai ona e siaki pine pr_done ma pr_error e faʻamaonia pe faʻamaeʻaina lelei le PR. Afai e tupu se mea sese, e pei o le toilalo i le siakiina o faʻamatalaga ma le faʻatagaina o le siakiina, e faʻamutaina le PR.
Fa'amatalaga Fa'atatau
- Intel Agilex F-Series FPGA Development Kit Web Itulau
- Intel Agilex F-Series FPGA Development Kit Guide Guide
- Intel Quartus Prime Pro Lomiga Taiala mo Tagata Ta'iala: Toe Fa'atonu Fa'apitoa
Fa'atonu Fa'apitoa Fa'atonu Fafo Fa'atonu Pule Intel FPGA IP
E mana'omia le Fa'atonu Fa'atonu Fa'apitoa Fa'atonu Fa'atonu e fa'aoga pine fa'aopoopo e fa'asolo ai fa'amaumauga a le PR mo le fa'atinoga o le PR. E tatau ona e fa'afeso'ota'i uma pito i luga o pito i luga ole vaega ole Fa'atonu Fa'atonu Fa'apitoa Fa'atonu Pule Intel FPGA IP ile pine pr_request e fa'ataga ai le lululima o le 'au fa'atasi ma le pule o masini malupuipuia (SDM) mai le totonugalemu. E fuafua e le SDM po'o fea ituaiga pine fa'aopoopo e fa'aoga, e tusa ai ma lau fa'atulagaga MSEL.
Fa'atonu Fa'apitoa Fa'atonu Fafo Fa'atonu Pule Intel FPGA IP
Toefa'a'ese'ese Fa'asagaga Fa'afofo Fa'atonu Pule Fa'atonu Fa'atonu
| Parameter | Taua | Fa'amatalaga |
| Fa'aagaoi le Pisi Fesootaiga | Fa'amalo or
Fa'agata |
Fa'ataga oe e fa'aagaoioia pe fa'agata le feso'ota'iga Pisi, lea e fa'ailoa mai ai se fa'ailoga e fa'ailoa ai o lo'o fa'agasolo le faiga o le PR a'o fa'atulaga fafo.
O le seti masani o le Fa'agata. |
Toefa'a'ese'ese Fa'asagaga Fa'a-fofo Fa'atonu Taulaga Pule
| Igoa o le Taulaga | Lautele | Fa'atonuga | Galuega |
| pr_request | 1 | Ulufale | Fa'ailoa mai ua sauni le faiga o le PR e amata. O le faailo o se alavai e le ogatasi ma soo se faailo o le uati. |
| pr_error | 2 | Tuuina atu | Fa'ailoa mai ose vaega toe fetu'una'iga sese.:
• 2'b01—sese lautele PR • 2'b11—sese bitstream e le fetaui O nei faailoilo o alavai ia e le ogatasi i so'o se punavai o le uati. |
| pr_faia | 1 | Tuuina atu | Fa'ailoa mai ua mae'a le faiga ole PR. O le faailo o se alavai e le ogatasi ma soo se faailo o le uati. |
| start_addr | 1 | Ulufale | Fa'ailoa mai le tuatusi amata o fa'amatalaga PR ile Active Serial Flash. E te fa'atagaina lenei fa'ailoga e ala i le filifilia o se tasi Avalon®-ST or Active Serial mo le Fa'aaga Pins Avalon-ST po'o Pins Serial Active fa'ata'oto. O le faailo o se alavai e le ogatasi ma soo se faailo o le uati. |
| toe setiina | 1 | Ulufale | Fa'ailoga maualuga fa'agaoioi, fa'atonu fa'atonu. |
| out_clk | 1 | Tuuina atu | Punavai uati e fa'atupu mai se oscillator totonu. |
| pisi | 1 | Tuuina atu | O lo'o fa'ailoa mai e le IP lenei fa'ailoga e fa'ailoa mai ai le fa'aliliuina atu o fa'amaumauga a le PR o lo'o fa'agasolo. E te fa'atagaina lenei fa'ailoga e ala i le filifili Fa'amalo mo le Fa'aagaoi le fa'aoga pisi fa'ata'oto. |
Fa'asinoga Fa'atusa Manaoga
O le faʻaaogaina o lenei mamanu faʻasino e manaʻomia mea nei:
- Fa'atuina o le Intel Quartus Prime Pro Edition version 22.3 fa'atasi ai ma le lagolago mo le aiga masini Intel Agilex.
- So'oga ile Intel Agilex F-Series FPGA development board ile nofoa.
- La'uina mai le mamanu example avanoa i le nofoaga nei: https://github.com/intel/fpga-partial-reconfig.
Ina ia sii maia le mamanu exampLe:
- Kiliki Clone pe download.
- Kiliki i lalo le ZIP. Tatala le fpga-partial-reconfig-master.zip file.
- Su'e i le a'oa'oga/agilex_external_pr_configuration subfolder e maua ai le mamanu fa'asino.
Fa'asinomaga Design Walkthrough
O laasaga nei o loʻo faʻamatalaina ai le faʻatinoina o le toe faʻatulagaina o vaega e ala i pine faʻapipiʻi (faʻafeiloaʻi fafo) i luga o le Intel Agilex F-Series FPGA development board:
- Laasaga 1: Amataina
- Laasaga 2: Fausiaina o se Vaeluaga o Fuafuaga
- Laasaga 3: Tu'ufa'atasia Tulaga ma Fa'a'ala'au Itulagi
- Laasaga 4: Fa'aopoopoina le Fa'atonu Fa'apitoa Fa'apitoa Fa'atonu Pule IP
- Laasaga 5: Fa'amatalaina o Tagata
- Laasaga 6: Fausiaina o Toe Iloiloga
- Laasaga 7: Tu'ufa'atasiga o le Toefuata'iga Fa'avae
- Laasaga 8: Tapenaga Toe Iloiloga o le Faatinoga o Galuega
- Laasaga 9: Polokalama le Komiti Faatino
Laasaga 1: Amataina
Ina ia kopi le mamanu faasinomaga files i lou siosiomaga faigaluega ma tuufaatasia le blinking_led mafolafola mamanu:
- Fausia se lisi i lou siosiomaga faigaluega, agilex_pcie_devkit_blinking_led_pr.
- Kopi le la'u mai a'oa'oga/agilex_pcie_devkit_blinking_led/flat sub-folder i le lisi, agilex_pcie_devkit_blinking_led_pr.
- I le polokalama Intel Quartus Prime Pro Edition, kiliki File ➤ Tatala Poloketi ma filifili blinking_led.qpf.
- Ina ia fa'amanino le fa'asologa o le mamanu mafolafola, kiliki Fa'agaioiga ➤ Amata ➤ Amata Iloiloga & Fa'asologa. I le isi itu, i le laina-faʻatonu, taʻavale le poloaiga lenei: quartus_syn blinking_led -c blinking_led
Fausiaina o se Vaeluaga o Fuafuaga
E tatau ona e faia ni vaeluaga o mamanu mo vaega PR ta'itasi e te mana'o e toe fa'aopoopo. O laasaga nei e fausia ai se vaeluaga mamanu mo le fa'ata'ita'iga u_blinking_led.
Fausia Fuafuaga Vaevaega
- Kiliki taumatau le u_blinking_led instance i le Project Navigator ma kiliki Design Partition ➤ Reconfigurable. O se ata vaeluaga mamanu e aliali i tafatafa o fa'ata'ita'iga ta'itasi o lo'o fa'atulagaina o se vaeluaga.
- Kiliki Assignments ➤ Design Partitions Window. O le faamalama o loʻo faʻaalia uma vaega mamanu i totonu o le poloketi.
- Fa'asa'o le igoa vaeluaga i le Design Partitions Window e ala i le kiliki-lua o le igoa. Mo lenei mamanu faʻasino, toe faʻaigoaina le igoa vaeluaga i le pr_partition
- Fa'aaliga: A e fatuina se vaeluaga, o le Intel Quartus Prime software e otometi lava ona gaosia se igoa vaeluaga, e faʻavae i luga o le igoa faʻataʻitaʻiga ma le ala faʻatulagaina. Ole igoa ole vaeluaga ole igoa e mafai ona fesuisuia'i ile fa'ata'ita'iga ta'itasi.
- Ina ia auina atu i fafo le vaega faʻamautu faʻamaeʻaina mai le faʻavae toe faʻapipiʻiina, kiliki faʻalua le ulufale mo root_partition i le Post Final Export File koluma, ma lolomi le blinking_led_static. gdb.
Tu'u atu i fafo le Ata Fa'ai'u Fa'ai'u ile Fa'amalama o Vaega Fa'ata'ita'i
Fa'amaonia o le blinking_led.qsf o lo'o i ai tofiga nei, e fetaui ma lau vaeluaga o le mamanu e mafai ona toe fa'atulagaina:
Fa'amatalaga Fa'atatau
“Fausia Fuafuaga Vaevaega” i le Intel Quartus Prime Pro Edition Taiala mo Tagata Fa'aoga: Fa'atonu Fa'atonu
Tu'ufa'atasia le Tulaga ma le Fa'a'ala'au Itulagi mo se Va'ega PR
Mo su'esu'ega fa'avae uma e te faia, o le fa'asologa o le PR design e tu'u ai le fa'atatau o le tagata i totonu o lau vaega va'aiga PR. Ina ia su'e ma tu'u le vaega ole PR ile fuafuaga ole fola ole masini mo lau toe iloiloga fa'avae:
- Kiliki taumatau le u_blinking_led instance i le Project Navigator ma kiliki Logic Lock Region ➤ Create New Logic Lock Region. O lo'o fa'aalia le itulagi ile Logic Lock Regions Window.
- E tatau ona fa'apipi'i i lau fa'atūlaga le fa'amana'oga blinking_led. Filifili le itu e tu'u ai e ala ile su'eina ole node ile Chip Planner. Kiliki taumatau le igoa o le itulagi u_blinking_led i le Logic Lock Regions Window ma kiliki
Su'e Node ➤ Su'e ile Chip Planner. O le itulagi u_blinking_led e fa'ailoga lanu
Chip Planner Node Nofoaga mo blinking_led
- I le fa'amalama Logic Lock Regions, fa'amaoti le fa'atulagaina o le itulagi fa'amaopoopo i le Origin column. O le amataga e fetaui ma le pito i lalo agavale o le itulagi. Mo example, e fa'atulaga se vaega fa'apipi'i fa'atasi ma (X1 Y1) fa'amaopoopo e pei o (163 4), fa'ama'oti le Origin o le X163_Y4. O le polokalama a le Intel Quartus Prime e otometi lava ona fuafua fa'atasi (X2 Y2) fa'amaopoopo (pito i luga-taumatau) mo le nofoaga e tu'u ai, e fa'atatau i le maualuga ma le lautele e te fa'ailoa mai.
- Fa'aaliga: O lenei aʻoaʻoga e faʻaogaina ai le (X1 Y1) faʻamaopoopo - (163 4), ma le maualuga ma le lautele o le 20 mo le nofoaga tuʻuina. Fa'amatala so'o se tau mo le nofoaga e tu'u ai. Ia mautinoa o lo'o ufiufi e le itulagi le fa'atatau o le blinking_led.
- Fa'aaga le filifiliga Fa'asao ma Na'o le Autu.
- Kiliki faalua le filifiliga Itulagi Routing. O lo'o fa'aali mai le pusa fa'atalanoaga o Fa'asinomaga Loka Loka Fa'aitulagi.
- Filifili Fixed with expansion mo le ituaiga Fa'aala. O le filifilia o lenei filifiliga e otometi lava ona tuʻuina atu le umi faʻalautele o le 2.
- Fa'aaliga: E tatau ona lapo'a atu le vaega o auala i lo le vaega o lo'o tu'u ai, ina ia fa'aopoopo atili ai le fetu'utu'una'i mo le Fitter pe'ā 'ese'ese tagata e uia e le afi.
Loka Fa'amalama Fa'amalo
Fa'amaonia o le blinking_led.qsf o lo'o i ai tofiga nei, e fetaui ma lau fuafuaga o le fola:
Fa'amatalaga Fa'atatau
“Floorplan the Partial Reconfiguration Design” i le Intel Quartus Prime Pro Edition Taiala mo Tagata Fa'aoga: Vaega Toefa'atonu.
Fa'aopoopoina le Fa'atonu Fa'apitoa Fa'apitoa Fa'atonu Pule Intel FPGA IP
O le Vaega Fa'atonu Fa'atonu Fa'atonu Fa'atonu Pule Intel FPGA IP fa'afeso'ota'i ma le poloka fa'atonutonu a le Intel Agilex PR e pulea ai le puna bitstream. E tatau ona e faʻaopoopoina lenei IP i lau mamanu e faʻatino ai le faʻatulagaga i fafo. Mulimuli i laasaga nei e fa'aopoopo ai le Pule Fa'atonu Fa'apitoa Fa'apitoa Fa'apitoa Fa'apitoa
Intel FPGA IP i lau poloketi:
- Fa'aigoa Vaega Toefa'atonu i totonu o le fa'amaumauga o su'esu'ega IP Catalog (Meafaigaluega ➤ IP Catalog).
- Kiliki fa'alua Fa'atonu Fa'atonu Fa'atonu Fa'atonu Pule Intel FPGA IP.
- I le Fausia le IP Variant dialog box, fa'aoga external_host_pr_ip e pei o le File igoa, ona kiliki lea Fausia. E aliali mai le fa'atonu fa'amaufa'ailoga.
- Mo le Fa'aagaoioiga pisi fa'ata'ita'iga parakala, filifili Disable (le tulaga fa'aletonu). A e manaʻomia le faʻaogaina o lenei faailo, e mafai ona e fesuiaʻi le seti i le Enable.
Fa'aagaoi le Parameter Interface Pisi ile Parameter Editor
- Kiliki File ➤ Fa'asao ma alu ese mai le fa'atonu fa'atonu e aunoa ma le fa'atupuina o le faiga. O le fa'atonu fa'amaufa'ailoga e fa'atupuina le external_host_pr_ip.ip fesuiaiga IP file ma faaopoopo le file i le fa'ata'ita'iina o le blinking_led project. AN 991: Fa'atonu Fa'apitoa e ala i pine Fa'atonu (Fa'aui fafo) Fa'asinoga Fa'ailoga 750856 | 2022.11.14 AN 991:
- Fa'aaliga:
- a. Afai o loʻo e kopiina le external_host_pr_ip.ip file mai le pr directory, fa'asa'o ma le lima le blinking_led.qsf file ia aofia ai le laina lea: set_global_assignment -name IP_FILE pr_ip.ip
- b. Tuu le IP_FILE tofiga pe a uma le SDC_FILE tofitofiga (blinking_led. dc) i lau blinking_led.qsf file. O lenei fa'atonuga e fa'amautinoa ai le fa'atumauina talafeagai o le vaega o le Pule Fa'atonuina ole Vaega IP.
- Fa'aaliga: Ina ia iloa uati, le .sdc file aua o le PR IP e tatau ona mulimuli i soʻo se .sdc e fatuina ai uati e faʻaogaina e le IP autu. E te faafaigofieina lenei poloaiga e ala i le faamautinoaina o le .ip file mo le PR IP autu e aliali mai pe a uma soʻo se .ip files po'o .sdc files e te fa'aogaina e fa'amatala ai nei uati i le .qsf file mo lau toe teuteuga o le poloketi Intel Quartus Prime. Mo nisi fa'amatalaga, va'ai ile Vaega Toe Fa'atonuina ole Fa'atonu IP Fofo mo Tagata Ta'iala.
Fa'afou le Fuafuaga Tulaga Maualuga
E fa'afou le top.sv file fa'atasi ai ma le PR_IP fa'ata'ita'iga:
- Ina ia faʻaopoopo le external_host_pr_ip faʻataʻitaʻiga i le mamanu pito i luga, faʻamalo le faʻamatalaga o poloka code nei ile pito i luga.sv file:
Fa'amatalaina o Tagata
O lenei mamanu fa'asinomaga e fa'amatalaina ai ni tagata eseese se tolu mo le vaega PR e tasi. Ina ia fa'amatala ma fa'aaofia tagata i lau galuega faatino:
- Fausia se tolu SystemVerilog files, blinking_led.sv, blinking_led_slow.sv, ma blinking_led_empty.sv i lau lisi galue mo tagata e toatolu.
Reference Design Personas
Fa'aaliga:
- blinking_led.sv ua uma ona avanoa o se vaega o le filee te kopiina mai le flat/sub-directory. E mafai lava ona e toe fa'aaogaina lenei mea file.
- Afai e te fatuina le SystemVerilog files mai le Intel Quartus Prime Text Editor, tape le Add file i le filifiliga o lo'o iai nei, pe a fa'asaoina le files.
Fausiaina o Toe Iloiloga
O le PR design flow e fa'aogaina ai le toe teuteuga o galuega i le polokalama Intel Quartus Prime. O lau mamanu muamua o le toe teuteuga faavae, lea e te faʻamalamalamaina ai tuaoi o le itulagi faʻamautu ma reconfigurable itulagi i luga o le FPGA. Mai le toe iloiloga faavae, e te faia ni toe iloiloga se tele. O nei toe iloiloga o loʻo i ai faʻatinoga eseese mo itulagi PR. Ae ui i lea, o faʻataʻitaʻiga uma o le faʻatinoga o le PR e faʻaogaina le tuʻufaʻatasia pito i luga ma le faʻasologa o taunuuga mai le toe iloiloga faavae. Ina ia tu'ufa'atasia se PR design, e tatau ona e faia se iloiloga fa'atinoina o le PR mo tagata ta'itasi. E le gata i lea, e tatau ona e tofia ituaiga toe teuteu mo toe teuteuga taitasi. O ituaiga toe iloiloga o loʻo avanoa e:
- Toe fetuutuunai vaega - Fa'avae
- Vaega Toefa'atonu - Fa'atinoina o Tagata
O le laulau o lo'o i lalo o lo'o lisiina ai le igoa toe teuteu ma le ituaiga toe teuteuga mo teuteuga ta'itasi:
Su'ega Igoa ma Ituaiga
| Suafa Igoa | Ituaiga Toe Iloilo |
| blinking_led.qsf | Toe fetuutuunai vaega - Fa'avae |
| blinking_led_default.qsf | Vaega Toefa'atonu - Fa'atinoina o Tagata |
| blinking_led_slow.qsf | Vaega Toefa'atonu - Fa'atinoina o Tagata |
| blinking_led_empty.qsf | Vaega Toefa'atonu - Fa'atinoina o Tagata |
Fa'atulaga le Ituaiga Toefuata'iga Fa'avae
- Kiliki Poloketi ➤ Toe Iloiloga.
- I le Revision Name, filifili le blinking_led revision, ona kiliki lea Seti le taimi nei.
- Kiliki Apply. Ua fa'aalia le toe teuteuga o le blinking_led e pei o le toe iloiloga o lo'o iai nei.
- Ina ia seti le Ituaiga Toe Iloilo mo blinking_led, kiliki Tofiga ➤ Seti ➤ Lautele.
- Mo Revision Type, filifili Partial Reconfiguration - Base, ona kiliki lea OK.
- Fa'amaonia o le blinking_led.qsf o lo'o i ai nei le tofiga nei: ##blinking_led.qsf set_global_assignment -igoa REVISION_TYPE PR_BASE
Fausia Fa'atonuga Fa'atinoga
- Ina ia tatala le pusa fa'atalanoaga o Revisions, kiliki Project ➤ Revisions.
- Ina ia faia se toe iloiloga fou, kiliki faalua < >.
- I le igoa Toe Iloiloga, fa'asino le blinking_led_default ma filifili le blinking_led mo Fa'avae i le toe iloiloga.
- Mo le ituaiga Toefuata'iga, filifili Fa'asagaga Fa'apitoa - PersonaImplementation.
Fausiaina o Toe Iloiloga
- Fa'apena fo'i, fa'atulaga le ituaiga Toefuata'iga mo fa'afouga fa'amatamata_lemu ma fa'aliga_fa'aola.
- Fa'amaonia o .qsf ta'itasi file o lo'o i ai nei le tofiga: set_global_assignment -igoa REVISION_TYPE PR_IMPL set_instance_assignment -igoa ENTITY_REBINDING \ place_holder -to u_blinking_led lea, place_holder o le igoa fa'aletino e le'i fa'atulagaina mo le suiga fou o le fa'atinoga o le PR.
Toe Iloiloga o Poloketi
Tuufaatasia o le Toefuataiga Faavae
- Ina ia tuufaatasia le toe iloiloga faavae, kiliki Processing ➤ Start Compilation. I le isi itu, o le poloaiga lenei e tuufaatasia ai le toe iloiloga faavae: quartus_sh –flow compile blinking_led -c blinking_led
- Asiasi le bitstream files e fa'atupuina i le gaosiga_files directory.
Fausia Files
| Igoa | Ituaiga | Fa'amatalaga |
| blinking_led.sof | Polokalama faavae file | Fa'aoga mo le fa'atulagaina o fa'avae masini uma |
| blinking_led.pr_partition.rbf | PR bitstream file mo tagata faavae | Fa'aoga mo le toe fa'atulagaina o vaega ole tagata fa'avae. |
| blinking_led_static.qdb | .qdb fa'amaumauga file | Fa'amautu fa'amaumauga file fa'aaoga e fa'aulufale mai ai le vaega fa'amautu. |
Fa'amatalaga Fa'atatau
- “Floorplan the Partial Reconfiguration Design” i le Intel Quartus Prime Pro Edition Taiala mo Tagata Fa'aoga: Vaega Toefa'atonu.
- “Fa'aogaina Fa'agata Fa'afuafua” ile Intel Quartus Prime Pro Lomiga Taiala mo Tagata Fa'aoga: Toe Fa'atonu vaega.
Sauniuniga Toe Iloiloga o le Faatinoga o le PR
E tatau ona e saunia le PR faʻatinoga o faʻataʻitaʻiga aʻo leʻi mafai ona e tuʻufaʻatasia ma gaosia le PR bitstream mo masini polokalame. O lenei seti e aofia ai le fa'aopoopoina o le static region .qdb file e fai ma puna file mo toe iloiloga o faatinoga taitasi. E le gata i lea, e tatau ona e faʻamaonia le vaega tutusa o le PR region.
- Ina ia seti le toe iloiloga o loʻo i ai nei, kiliki Project ➤ Revisions, filifili blinking_led_default o le Revision name, ona kiliki lea Set Current.
- Ina ia fa'amaonia le puna sa'o mo fa'atonuga ta'itasi, kiliki Project ➤Add/Remove Files i Poloketi. O le blinking_led.sv file aliali mai i le file lisi.
Files Itulau
- Toe fai la'asaga 1 e oo i le 2 e fa'amaonia ai le isi fa'apogai o le toe fa'atinoga files:
| Su'ega Fa'atinoga Igoa | Punavai File |
| blinking_led_default | blinking_led.sv |
| blinking_led_empty | blinking_led_empty.sv |
| blinking_led_slow | blinking_led_slow.sv |
- Ina ia faʻamaonia le .qdb file e feso'ota'i ma le vaeluaga o a'a, kiliki Tofiga ➤ Fa'ailoga Vaevaega Fa'amalama. Faʻamaonia o le Vaevaega Faʻamaumauga File fa'ailoa mai le blinking_led_static.qdb file, po'o le kiliki fa'alua o le Vaevaega Fa'amaumauga File cell e faʻamaonia ai lenei mea file. I le isi itu, o le poloaiga lenei e tuʻuina atu ai lenei file: set_instance_assignment -igoa QDB_FILE_VAEGA \ blinking_led_static.qdb -to |
- I totonu o le Entity Re-binding cell, faʻamaonia le igoa o le vaega o vaega PR taʻitasi e te suia i le toe iloiloga o le faʻatinoga. Mo le toe iloiloga o le faatinoga o le blinking_led_default, o le igoa o le faalapotopotoga o le blinking_led. I lenei a'oa'oga, e te toe fa'asolo le u_blinking_led fa'ata'ita'iga mai le toe iloiloga fa'avae fa'atasi ma le blinking_led entity fou.
Fa'aaliga: E otometi le fa'aopoopoina o le fa'atonuga e toe fa'aopoopoina ai le fa'atinoga. Ae ui i lea, e tatau ona e suia le igoa fa'aletonu i le tofiga i se igoa fa'alapotopotoga talafeagai mo lau mamanu.
| Su'ega Fa'atinoga Igoa | Toe fusifusia |
| blinking_led_default | fa'ata'imata |
| blinking_led_slow | blinking_led_slow |
| blinking_led_empty | blinking_led_empty |
Fa'atasiga Fa'atasi
- Ina ia tuufaatasia le mamanu, kiliki Processing ➤ Start Compilation. I le isi itu, o le poloaiga lenei e tuufaatasia ai lenei poloketi: quartus_sh –flow compile blinking_led –c blinking_led_default
- Toe fai la'asaga o lo'o i luga e saunia ai toe teuteuga emo_led_slow ma emoe_led_empty: quartus_sh –fa'aga tu'ufa'atasia blinking_led –c blinking_led_slow quartus_sh –flow tu'ufa'atasi blinking_led –c blinking_led_empt
Fa'aaliga: E mafai ona e faʻamaonia soʻo se faʻatulagaga faʻapitoa a le Fitter e te manaʻo e faʻaoga i le taimi o le faʻatulagaina o le PR. Fa'atonu tulaga fa'apitoa e a'afia ai na'o le fetaui o le tagata, e aunoa ma le a'afiaina o le vaega fa'aulufale mai.
Polokalama le Komiti Faatino
O lenei aʻoaʻoga e faʻaaogaina ai le Intel Agilex F-Series FPGA development board i luga o le nofoa, i fafo atu o le PCIe * slot i lau masini talimalo. Ae e te leʻi faʻapipiʻiina le laupapa, ia mautinoa ua maeʻa laasaga nei:
- Faʻafesoʻotaʻi le eletise i le Intel Agilex F-Series FPGA development board.
- Fa'afeso'ota'i le Intel FPGA Download Cable i le va o lau PC USB port ma le Intel FPGA Download Cable port i luga o le laupapa atina'e.
Ina ia faʻatautaia le mamanu ile Intel Agilex F-Series FPGA development board:
- Tatala le polokalama Intel Quartus Prime ma kiliki Tools ➤ Programmer.
- I le Polokalama, kiliki Faʻatonu Setup ma filifili USB-Blaster.
- Kiliki Auto Detect ma filifili le masini, AGFB014R24AR0.
- Kiliki OK. O le Intel Quartus Prime software e iloa ma faʻafouina le Polokalama ma masini FPGA e tolu i luga o le laupapa.
- Filifili le masini AGFB014R24AR0, kiliki Suiga File ma uta le blinking_led_default.sof file.
- Fa'aaga le Polokalama/Fa'atonu mo blinking_led_default.sof file.
- Kiliki Amata ma faʻatali mo le alualu i luma pa e oʻo i le 100%.
- Mata'ituina ia LED i luga o le laupapa e emo i le taimi tutusa ma le uluai mamanu mafolafola.
- Ina ia fa'apolokalame na'o le PR region, kiliki-matau le blinking_led_default.sof file i le Polokalama ma kiliki Faʻaopoopo PR Programming File.
- Filifili le blinking_led_slow.pr_partition.rbf file.
- Fa'agata Polokalama/Configure mo blinking_led_default.sof file.
- Fa'aaga le Polokalama/Configure mo blinking_led_slow.pr_partition.rbf file ma kiliki Amata. I luga o le laupapa, mata'ituina le LED[0] ma le LED[1] o lo'o fa'aauau pea ona emo. A o'o le pa o le alualu i luma i le 100%, emo fa'agesegese le LED[2] ma le LED[3].
- Ina ia toe polokalame le PR region, kiliki-matau le .rbf file i le Polokalama ma kiliki Suiga PR Programing File.
- Filifili le .rbf files mo isi tagata e lua e matau le amio i luga o le laupapa. Tu'u le blinking_led_default.rbf file mafua ai ona emoemo LED i se taimi patino, ma uta le blinking_led_empty.rbf file mafua ai ona tumau pea le LED.
Polokalama le Intel Agilex F-Series FPGA Development Board
Su'ega Su'ega Meafaigaluega
O fa'asologa o lo'o i lalo e fa'amatala ai le fa'ata'ita'iga o su'ega meafaigaluega.
Intel Agilex Device Seti Meafaigaluega Fa'aui i fafo
Polokalama le Fesoasoani FPGA (Taga'i i fafo)
O le fa'asologa o lo'o i lalo o lo'o fa'amatalaina ai le fa'apolokalameina o le fesoasoani FPGA o lo'o fa'agaoioia e pei o le PR fa'agasologa o le talimalo i fafo:
- Fa'ailoa le fa'atulagaina o le Avalon streaming interface e fetaui ma le faiga e te filifilia (x8, x16, po'o le x32).
- Fa'amataina le fa'avae e ala i le fa'apolokalameina o le fesoasoani FPGA e fa'aaoga ai le Intel Quartus Prime Programmer ma feso'ota'i uaea fa'atulagaina.
- Fa'aaogā le fesoasoani FPGA, faitau fa'ailoga CONF_DONE ma AVST_READY. CONF_DONE e tatau ona 0, AVST_READY e tatau ona 1. Logic maualuga i luga o lenei pine e taʻu mai ai ua sauni le SDM e talia faʻamatalaga mai se talimalo i fafo. O lenei galuega faatino o se vaega ole SDM I/O.
Fa'aaliga: O le pine CONF_DONE e fa'ailo ai se 'au mai fafo e manuia le fesiitaiga o bitstream. Fa'aaogā fa'ailoga nei e mata'itu ai le fa'agasologa atoa o le fa'atulagaina o chip. Va'ai ile Intel Agilex Configuration User Guide mo nisi fa'amatalaga ile pine lea.
Polokalama le DUT FPGA ma Full Chip SOF e ala i fafo Host O le faasologa o loʻo faʻamatalaina le faʻatulagaina o le DUT FPGA ma le SRAM Object atoa. File (.sof) e fa'aaoga ai le fa'aoga Avalon streaming interface:
- Tusi le bitstream chip atoa i totonu o le DDR4 manatua fafo o le fesoasoani FPGA (tagata talimalo i fafo).
- Fa'atulaga le DUT FPGA fa'atasi ai ma le va'aiga atoa .sof e fa'aaoga ai le Avalon streaming interface (x8, x16, x32).
- Faitau le tulaga DUT FPGA fa'ailoga fa'atulagaina. CONF_DONE e tatau ona 1, AVST_READY e tatau ona 0.
Fa'amatalaga Taimi: Toe Fa'atonu Fa'apitoa Pule i fafo Intel FPGA IP
Polokalama le DUT FPGA ma le First Persona e ala i fafo
- Fa'aoga le fa'a'aisa i luga ole vaega ole PR i le DUT FPGA.
- I le fa'aaogaina o le Intel Quartus Prime System Console, fa'ailoa le pr_request e amata ai le toe fa'atulagaina o vaega. AVST_READY e tatau ona 1.
- Tusi le muamua PR persona bitstream i totonu o le DDR4 manatua i fafo o le fesoasoani FPGA (tagata talimalo i fafo).
- I le fa'aaogaina o le Avalon streaming interface (x8, x16, x32), toe fa'aleleia le DUT FPGA fa'atasi ai ma le tagata muamua bitstream.
- Ina ia mataʻituina le tulaga PR, kiliki Tools ➤ System Console e faʻalauiloa System Console. I le System Console, mata'itu le tulaga PR:
- pr_error o le 2—toe fa'atulagaina i le faagasologa.
- pr_error e 3—ua mae'a le toe fa'atulagaina.
- Fa'aaoga le fa'a'aisa i le PR region i le DUT FPGA.
Fa'aaliga: Afai e tupu se mea sese i le taimi o le PR, e pei o le toilalo i le siakiina o lomiga poʻo le faʻatagaina o le siakiina, e faʻamutaina le PR.
Fa'amatalaga Fa'atatau
- Intel Agilex Configuration User Guide
- Intel Quartus Prime Pro Edition Taiala mo Tagata Fa'aoga: Debug Tools
Fa'amatalaga Toe Iloiloga o Fa'amaumauga mo AN 991: Toe Fa'atonu Fa'apitoa e ala i Pin Fa'atonu (Taga'i i fafo) Fa'ailoga Fa'asinoga mo le Intel Agilex F-Series FPGA Development Board
| Fa'amatalaga Fa'amaumauga | Intel Quartus Prime Version | Suiga |
| 2022.11.14 | 22.3 | • Fa'asalalauga muamua. |
AN 991: Fa'atonu Fa'apitoa e ala i Pin Fa'atonu (Fa'aui i fafo) Fa'ailoga Fa'asinomaga: mo le Intel Agilex F-Series FPGA Development Board
Tali i FAQ pito i luga:
- Q O le a le PR e ala i pine fa'atulagaina?
- A Fetufa'aiga Fa'apitoa i fafo ile itulau 3
- Q O le a le mea ou te manaʻomia mo lenei mamanu faʻasino?
- A Fa'asinoga Fa'atusa Mana'omia ile itulau 6
- Q O fea e mafai ona ou maua ai le mamanu fa'asino?
- A Fa'asinoga Fa'atusa Mana'omia ile itulau 6
- Q E fa'afefea ona ou fa'atinoina le PR e ala i le fa'atulagaina o fafo?
- A Reference Design Walkthrough i le itulau e 6
- Q O le a le PR persona?
- A Fa'amatalaina o Tagata i le itulau e 11
- Q E faapefea ona ou faapolokalameina le laupapa?
- A Polokalama le Komiti Faatino i le itulau e 17
- Q O a fa'afitauli ma tapula'a ua iloa e le PR?
- A Intel FPGA Lagolago Fono: PR
- Q E iai sau toleniga ile PR?
- A Intel FPGA Technical Training Catalog
Online Version Lauina Manatu
- ID: 750856
- Fa'aliliuga: 2022.11.14
Pepa / Punaoa
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intel 750856 Agilex FPGA Development Board [pdf] Taiala mo Tagata Fa'aoga 750856, 750857, 750856 Agilex FPGA Development Board, Agilex FPGA Development Board, FPGA Development Board, Development Board, Board |