F-Tile JESD204C Intel FPGA IP Design Example User Guide

O lenei ta'iala fa'aoga o lo'o tu'uina atu ai foliga, ta'iala fa'aoga, ma fa'amatalaga auiliili e uiga i le mamanu examples mo le F-Tile JESD204C Intel® FPGA IP fa'aoga Intel Agilex™ masini.

Tagata Fa'amoemoe

O lenei pepa e fa'amoemoe mo:

Fa'ata'ita'i fa'ata'ita'i e fai le filifiliga IP i le taimi o le fa'atulagaina o fuafuaga fa'atulagaina
Fa'ailoga masini pe a tu'ufa'atasia le IP i totonu o la latou mamanu fa'atulagaina

Fa'ainisinia fa'amaonia i le taimi o fa'ata'ita'iga tulaga fa'aoga ma vaega fa'amaonia meafaigaluega

Pepa Fa'atatau
O le laulau o loʻo i lalo o loʻo lisiina ai isi faʻamatalaga faʻamatalaga e fesoʻotaʻi ma le F-Tile JESD204C Intel FPGA IP.

Laulau 1. Pepa Fa'atatau

Fa'asinomaga	Fa'amatalaga
F-Tile JESD204C Intel FPGA IP Taiala Fa'aaogāina	Tuuina atu faʻamatalaga e uiga i le F-Tile JESD204C Intel FPGA IP.
F-Tile JESD204C Intel FPGA IP Fa'amatalaga Fa'amatalaga	Lisi suiga na faia mo le F-Tile JESD204C F-Tile JESD204C i se faʻasalalauga faʻapitoa.
Intel Agilex Device Data Pepa	O lenei pepa o loʻo faʻamatalaina uiga eletise, suiga o uiga, faʻatulagaina faʻamatalaga, ma le taimi mo masini Intel Agilex.

Acronyms ma Glossary

Laulau 2. Lisi Acronym

Acronym	Fa'alautele
LEMC	Local Extended Multiblock Clock
FC	Fua o le uati faavaa
ADC	Analog to Digital Converter
DAC	Fa'afuainumera i le Analog Converter
DSP	Fa'afuainumera Fa'ailoga Fa'ailoga
TX	Transmisi
RX	Talia

Acronym	Fa'alautele
DLL	Laega feso'ota'iga fa'amaumauga
CSR	Pulea ma tulaga resitala
CRU	Uati ma Toe Seti Vaega
ISR	Fa'alavelave Au'aunaga masani
FIFO	Muamua-I totonu-Muamua-I fafo
SERDES	Serializer Deserializer
ECC	Fa'atonu Fa'atonu Fa'ailoga
FEC	Fa'asa'oga Sese i luma
SERR	Su'esu'ega Tasi Sese (i le ECC, fa'asa'o)
DERR	Su'esu'ega Faalua Sese (i le ECC, oti)
PRBS	Pseudorandom binary sequence
MAC	Pule Fa'asalalau Avanoa. O le MAC e aofia ai le faʻasologa o faʻasalalauga, faʻasologa o felauaiga, ma faʻamaumauga fesoʻotaʻiga.
PHY	Fa'aletino. O le PHY e masani ona aofia ai le vaega fa'aletino, SERDES, aveta'avale, tagata e talia ma le CDR.
PCS	Fa'asinomaga Fa'aletino La'asaga
PMA	Fa'apipi'i Fa'aletino
RBD	RX Buffer Fa'atuai
UI	Iunite Vaeluaga = umi o le faasologa bit
Faitauga RBD	RX Buffer Fa'atuai le taunuu mai o le laina lata mai
RBD offset	RX Buffer Fa'atuai avanoa fa'amalolo
SH	Fa'aulutala fa'atasi
TL	La'au felauaiga
EMIB	Fa'apipi'i Tele-mate Feso'ota'i Alalaupapa

Laulau 3. Lisi Fa'amatalaga

Vaitaimi	Fa'amatalaga
Mea Fa'aliliu	ADC poʻo DAC liliu
Mea Fa'atonu	FPGA poʻo ASIC
Octet	O se vaega o 8 bits, o loʻo avea ma faʻaoga i le 64/66 encoder ma gaioiga mai le decoder.
u'u	O se seti o 4 bits o le iunite galue faavae o JESD204C faʻamatalaga
Poloka	O se fa'ailoga 66-bit na fa'atupuina e le 64/66 encoding scheme
Laina Fua Faatatau	Ole fua fa'amatalaga lelei ole so'oga fa'asologa Fua Faatatau o le Lane = (Mx Sx N'x 66/64 x FC) / L
So'oga Uati	So'oga Uati = Lane Line Fua/66.
Fa'avaa	O se seti o octet sosoo e mafai ona iloa ai le tulaga o octet taitasi e ala i le faasino i se fa'ailoga fa'aoga fa'avaa.
Uati faavaa	O se uati fa'aoga e tamo'e i le fua o le fa'avaa, e tatau ona 1x ma le 2x feso'ota'iga uati.

Vaitaimi	Fa'amatalaga
Samples i le faavaa uati	Samples i le uati, o le aofa'iga samples i le uati faavaa mo le masini liliu.
LEMC	O le uati i totonu e fa'aoga e fa'aoga ai le tua'oi o le tele poloka fa'alautele i le va o laina ma fa'asino i fafo (SYSREF po'o le Vasega 1).
Vasega laiti 0	Leai se lagolago mo le fa'amautu le tumau. E tatau ona vave tu'uina atu fa'amatalaga i luga o le laina i le laina o le kesi i luga o le tali.
Vasega laiti 1	Deterministic latency fa'aaoga SYSREF.
Feso'ota'iga Telepoint	Feso'ota'iga va'ava'ai ma masini fa'aliliu e 2 pe sili atu.
64B/66B Fa'ailoga	Laina laina e fa'afanua fa'amaumauga 64-bit i le 66 bits e fai ai se poloka. Ole fa'asologa o fa'amaumauga fa'avae ose poloka e amata ile 2-bit sync header.

Laulau 4. Fa'ailoga

Vaitaimi	Fa'amatalaga
L	Numera o laina i le masini liliu
M	Numera o tagata liliu i le masini
F	Numera o octets i le faavaa i luga o le laina e tasi
S	Numera o sample tu'uina atu i le tasi lilivau i le ta'amilosaga fa'avaa
N	Fuafuaga faaliliu
N'	Aofa'i numera o bits i le sample i le faʻamaumauga faʻamatalaga tagata faʻaoga
CS	Numera o pusi fa'atonutonu ile liua sample
CF	Numera o upu fa'atonutonu ile faavaa uati vaitaimi ile so'oga
HD	High Density fa'amaumauga a tagata fa'aoga
E	Numera o poloka fa'atele i totonu ole poloka fa'atele

F-Tile JESD204C Intel FPGA IP Design Example Taiala Amata vave

Le F-Tile JESD204C Intel FPGA IP mamanu examples mo masini Intel Agilex o loʻo faʻaalia ai se suʻega faʻataʻitaʻiga ma se mamanu meafaigaluega e lagolagoina le tuʻufaʻatasia ma suʻega meafaigaluega.
E mafai ona e gaosia le F-Tile JESD204C design exampe ala i le IP catalog i le polokalama Intel Quartus® Prime Pro Edition.

Ata 1. Atina'e Stage mo le Design Example

Design Example Ata poloka

Ata 2. F-Tile JESD204C Design Example Ata Poloka Tulaga Maualuga

Le mamanu exampe aofia ai modules nei:

Platform Designer faiga
- F-Tile JESD204C Intel FPGA IP
- JTAG i Avalon Master Bridge
- Fa'atonu le I/O (PIO).
- Fa'asinoala Tau Taulaga (SPI)—matai module— IOPLL
- SYSREF generator
- Example Design (ED) Puleaina CSR
- Toe seti sequencers
Faiga PLL

Fua fa'ameamea
Su'e mamanu

Laulau 5. Fuafuaga Example Modules

Vaega	Fa'amatalaga
Platform Designer faiga	O le faiga o le Platform Designer e fa'apipi'i vave ai le F-Tile JESD204C IP ala fa'amaumauga ma fa'aoga lagolago.
F-Tile JESD204C Intel FPGA IP	Lenei Platform Designer subsystem o lo'o iai le TX ma le RX F-Tile JESD204C IPs fa'atasi ma le duplex PHY.
JTAG i Avalon Master Bridge	O lenei alalaupapa e tuʻuina atu ai le faʻamafanafanaga faʻaoga avanoa i le IP faʻapipiʻi manatua i le mamanu e ala i le JTAG feso'ota'iga.
Fa'atonu le I/O (PIO).	O lenei pule e maua ai se atigipusa e manatua-faafanua mo sampling ma ave fa'amoemoe lautele I/O uafu.
matai SPI	O lenei module e fa'atautaia le fa'aliliuina fa'asologa o fa'amaumauga fa'atulagaina i le SPI fa'aoga i le pito liliu.
SYSREF generator	O le SYSREF generator e faʻaaogaina le uati fesoʻotaʻiga e fai ma uati faʻamatalaga ma faʻatupuina pulus SYSREF mo le F-Tile JESD204C IP. Fa'aaliga: O lenei mamanu exampLe fa'aogaina le SYSREF generator e fa'aalia ai le fa'auluina o feso'ota'iga F-Tile JESD204C IP. I le F-Tile JESD204C subclass 1 system level application, e tatau ona e gaosia le SYSREF mai le puna lava e tasi ma le uati masini.
IOPLL	O lenei mamanu exampLe fa'aaogaina o le IOPLL e fa'atupuina ai se uati fa'aoga mo le fa'aliliuina o fa'amatalaga i le F-Tile JESD204C IP.
ED Puleaina CSR	O lenei module e maua ai le SYSREF suʻesuʻeina ma le tulaga, ma le suʻega faʻataʻitaʻiga ma le tulaga.
Toe seti sequencers	O lenei mamanu exampe aofia ai le 2 seti sequencers: Toe Seti Fa'asologa 0—Ta'ita'ia le toe setiina ile TX/RX Avalon® streaming domain, Avalon memory-map domain, PLL autu, TX PHY, TX core, ma SYSREF generator. Toe Seti le Fa'asologa 1—Uu le toe setiina i le RX PHY ma le RX autu.
Faiga PLL	Punavai o le uati autu mo le F-tile malo IP ma EMIB kolosi.
Fua fa'ameamea	O le generator mamanu e gaosia se PRBS po'o le ramp mamanu.
Su'e mamanu	E fa'amaonia e le siaki mamanu le PRBS po'o le ramp mamanu maua, ma fu'a se mea sese pe a maua se le fetaui o faamatalaga sample.

Polokalama Manaoga

E fa'aoga e Intel le polokalame lea e fa'ata'ita'i ai le mamanu examples i se faiga Linux:

Polokalama Intel Quartus Prime Pro Edition
Questa*/ModelSim* po o le VCS*/VCS MX simulator

Fausiaina o le Fuafuaga

Le fa'atupuina o le mamanu example mai le fa'atonu IP parameter:

Fausia se poloketi e faʻatatau i le Intel Agilex F-tile device family ma filifili le masini e manaʻomia.
I le IP Catalog, Meafaigaluega ➤ IP Catalog, filifili F-Tile JESD204C Intel FPGA IP.
Fa'ailoa se igoa pito i luga ma le faila mo lau suiga masani IP. Kiliki OK. E fa'aopoopo e le fa'atonu fa'amaufa'ailoga le pito i luga .ip file i le galuega o lo'o iai otometi. Afai e uunaia oe e faaopoopo ma le lima le .ip file i le poloketi, kiliki Project ➤ Add/ Remove Files i Poloketi e fa'aopoopo le file.
I lalo o le Example Design tab, faʻamaonia le mamanu example parakalafa e pei ona faamatalaina i le Design Example Parameter.
Kiliki Fausia Example Design.

O le polokalama e gaosia uma mamanu files i totonu o sub-directories. O nei files e manaʻomia e faʻatautaia faʻataʻitaʻiga ma tuʻufaʻatasiga.

Design Example Parameter
O le F-Tile JESD204C Intel FPGA IP fa'atonu fa'atonu e aofia ai le Example Design tab mo oe e faʻamaoti ai ni faʻamaufaʻailoga aʻo leʻi faia le mamanu example.

Laulau 6. Parameter i le Example Design Tab

Parameter	Filifiliga	Fa'amatalaga
Filifili Design	System Console Pulea Leai	Filifili le pulega fa'amafanafanaga fa'aoga e maua ai le fa'ata'ita'igaample ala faʻamatalaga e ala i le faʻamafanafanaga faʻaoga.
Fa'ata'oto	Ua pe, ua pe	Fa'aola mo le IP e fa'atupu ai le mana'omia files mo le fa'ata'ita'iina o le mamanu example.
Fa'asologa	Ua pe, ua pe	Fa'aola mo le IP e fa'atupu ai le mana'omia filemo Intel Quartus Prime tu'ufa'atasiga ma fa'ata'ita'iga meafaigaluega.
HDL fa'atulagaina (mo fa'ata'ita'iga)	Verilog VDHL	Filifili le faatulagaga HDL o le RTL files mo fa'ata'ita'iga.
HDL fa'atulagaina (mo le tuufaatasia)	Verilog na'o	Filifili le faatulagaga HDL o le RTL files mo le tuufaatasia.

Parameter	Filifiliga	Fa'amatalaga
Fausia 3- uaea SPI module	Ua pe, ua pe	Ia ki ina ia mafai ai le 3-wire SPI interface nai lo le 4-wire.
Sysref faiga	Tasi tasi Vaitaimi Gapped faavaitaimi	Filifili pe e te manaʻo i le faʻaogaina o le SYSREF e tasi le pusi faʻataʻitaʻiga, faʻavaitaimi, poʻo le vaeluaga faʻavaitaimi, e faʻatatau i au mamanu manaʻoga ma taimi fetuutuunai. Tasi tasi—Filifili le filifiliga lenei ina ia mafai ai e le SYSREF ona avea ma se ata pusi e tasi le pu. Ole sysref_ctrl[17] register bit's value o le 0. A uma le F-Tile JESD204C IP reset deasserts, sui le sysref_ctrl[17] register's value mai le 0 i le 1, sosoo ai ma le 0, mo se pusi SYSREF e tasi. Vaitaimi—SYSREF i taimi fa'avaitaimi e 50:50 le taamilosaga tiute. Ole vaitaimi ole SYSREF ole ESYSREF_MULP. Gapped periodic—SYSREF o lo'o i ai polokalame fa'apolokalame fa'asologa o tiute o fa'asologa o le 1 feso'ota'iga ta'amilosaga uati. Ole vaitaimi ole SYSREF ole ESYSREF_MULP. Mo le fa'atulagaina o le ta'amilosaga o tiute i fafo, o le poloka fa'atupuina o le SYSREF e tatau ona otometi lava ona fa'ailoa le 50:50 tiute fa'ata'amilosaga. Fa'asino i le SYSREF Galue vaega mo nisi fa'amatalaga e uiga i le SYSREF vaitaimi.
Filifili laupapa	Leai	Filifili le laupapa mo le mamanu example. Leai—O lenei filifiliga e le aofia ai vaega o meafaigaluega mo le mamanu example. O fa'atonuga uma o pine o le a fa'atutu i pine fa'apitoa.
Mamanu Su'ega	PRBS-7 PRBS-9 PRBS-15 PRBS-23 Ramp	Filifili mamanu mamanu ma siaki siaki mamanu. Fua Fa'ata'ita'iga—JESD204C lagolago PRBS mamanu fa'atupu i fa'amaumauga sample. O lona uiga o le lautele o faʻamatalaga o le N + CS filifiliga. PRBS mamanu mamanu ma siaki e aoga mo le fatuina o faamatalaga sample faʻamalosi mo suʻega ma e le fetaui ma le PRBS faʻataʻitaʻiga i luga ole ADC/DAC converter. Ramp Fua Fa'ata'ita'iga—JESD204C so'oga layer e fa'agaoioia masani ae o le felauaiga mulimuli ane ua fa'aletonu ma le fa'aogaina mai le fa'aputuina. O laina ta'itasi e fa'asalalauina se vaitafe octet tutusa e fa'atuputeleina mai le 0x00 i le 0xFF ona toe fai lea. Ramp faʻataʻitaʻiga faʻataʻitaʻiga e mafai e pbs_test_ctl. PRBS Pattern Checker—JESD204C PRBS scrambler o lo'o fa'amaopoopoina e le tagata lava ia ma e fa'amoemoe pe a mafai e le IP core ona fa'avasega le feso'ota'iga, o le fatu si'i ua uma ona fa'atasi. PRBS scrambling fatu o le a alu i le 8 octets e amata ai. Ramp Su'e Fa'ata'ita'iga—JESD204C scrambling o le tagata lava ia synchronizing ma e fa'amoemoe pe a mafai e le IP core ona fa'avasega le feso'ota'iga i luga, o le fatu scrambling ua uma ona fa'atasi. O le octet aoga muamua e utaina o le ramp taua muamua. O fa'amaumauga mulimuli ane e tatau ona fa'aopoopo i luga i le 0xFF ma ta'avale i luga i le 0x00. Ramp siaki mamanu e tatau ona siaki mo se mamanu tutusa i luga o auala uma.
Fa'aagaioi totonu fa'asologa fa'asologa fa'asologa	Ua pe, ua pe	Filifili totonu fa'asologa fa'asologa fa'asologa.
Fa'agaoioi le Alavai Poloaiga	Ua pe, ua pe	Filifili le mamanu alavai fa'atonu.

Fa'atonuga Fa'atonu
Le F-Tile JESD204C mamanu example directories o loʻo i ai gaosia files mo le mamanu examples.

Ata 3. Fa'atonuga mo F-Tile JESD204C Intel Agilex Design Example

Laulau 7. Fa'atonuga Files

Folders	Files
ed/rtl	tx j204c_f_tx_ip.qsys j204c_f tx_ss.qsys altera_s10_user_rst_clkgate_0.ip j204c f_se_outbuf_1bit.ip
fa'ata'ita'iga/faufautua	modelsim_sim.tcl tb_top_waveform.do
fa'ata'ita'iga/synopsys	vcs vcs_sim.sh tb_top_wave_ed.do vcsmx vcsmx_sim.sh tb_top_wave_ed.do

Fa'ata'ita'iina o le Fa'ata'ita'iga Example Testbench

Le mamanu example testbench simulates lau mamanu gaosia.

Ata 4. Taualumaga

Ina ia fa'atusa le mamanu, fai laasaga nei:

Suia le lisi galue iample_design_directory>/simulation/ .
I le laina faʻatonu, faʻataʻitaʻi le faʻasologa faʻasologa. O le laulau o loʻo i lalo o loʻo faʻaalia ai le faʻatonuga e faʻatautaia ai simulators lagolagoina.

Simulator	Poloaiga
Questa/ModelSim	vsim -do modelsim_sim.tcl
Questa/ModelSim	vsim -c -do modelsim_sim.tcl (e aunoa ma Questa/ ModelSim GUI)
VCS	sh vcs_sim.sh
VCS MX	sh vcsmx_sim.sh

E fa'ai'u le fa'ata'ita'iga i fe'au e ta'u mai ai pe na manuia le tamo'ega pe leai.

Ata 5. Fa'ata'ita'iga Manuia
O lenei fuainumera o loʻo faʻaalia ai le feʻau faʻataʻitaʻiga manuia mo VCS simulator.

Tuufaatasia o le Design Example

Ia tuufaatasia le tuufaatasiga-na'o example poloketi, mulimuli i laasaga nei:

Ia mautinoa le tuufaatasia o le mamanu exampua maea le tupulaga.

I le polokalama Intel Quartus Prime Pro Edition, tatala le poloketi Intel Quartus Prime Pro Editionample_ design_ directory>/ed/quartus.
I luga o le Processing menu, kiliki Amata Compilation.

Fa'amatalaga Fa'amatalaga mo le F-Tile JESD204C Design Example

Le F-Tile JESD204C mamanu example fa'aalia le fa'atinoga o fa'amatalaga fa'asalalau e fa'aaoga ai le loopback mode.
E mafai ona e faʻamaonia le faʻatulagaina o faʻasologa o lau filifiliga ma faʻatupuina le mamanu example.
Le mamanu exampE na'o le lua e maua mo le fa'avae ma le PHY. E mafai ona e filifilia le Base na'o le PHY na'o le fesuiaiga ae o le IP e fa'atupuina le mamanu example mo Base ma PHY.

Fa'aaliga: O nisi fa'atonuga maualuga o fa'amaumauga e ono fa'aletonu le taimi. Ina ia aloese mai le faaletonu o le taimi, mafaufau e fa'amaoti le tau fa'atele fa'atele o taimi fa'avaa (FCLK_MULP) i le fa'ailoga Fa'atonu o le F-Tile JESD204C Intel FPGA IP fa'atonu fa'atonu.

Vaega Vaega

Le F-Tile JESD204C mamanu exampe maua ai se fa'atonuga fa'apolokalame fa'avae e fa'aoga ai le iunite fa'amalo ma pe leai fo'i le lagolago fa'amafanafana faiga.

Le mamanu exampe mafai ai e se feso'ota'iga ta'avale i totonu ma fafo fa'asolo i tua.

JTAG i Avalon Master Bridge
O le JTAG i Avalon Master Bridge e maua ai se feso'ota'iga i le va o le 'au talimalo e maua ai le fa'afanua F-Tile JESD204C IP ma le fa'atonutonuina o le IP ma le tulaga resitala e ala i le J.TAG feso'ota'iga.

Ata 6. Faiga faʻatasi ma se JTAG i Avalon Master Bridge Core

Fa'aaliga: E tatau ona le itiiti ifo i le 2X le vave o le uati o le polokalama nai lo le JTAG uati. O le uati fa'aoga o le mgmt_clk (100MHz) i lenei mamanu fa'ataample.

Fa'atasi I/O (PIO) Autu
O le fa'aoga tutusa (PIO) fa'atasi ma Avalon fa'aoga e maua ai se atigipusa manatua-fa'afanua i le va o le Avalon e manatua-fa'afanua pologa uafu ma fa'amoemoe lautele I/O ports. O ports I/O e fa'afeso'ota'i pe i luga ole masini masini, po'o pine I/O e feso'ota'i i masini i fafo ile FPGA.

Ata 7. PIO Core ma Taulaga Ulufale, Taulaga Fa'aulufale, ma Taulaga IRQ
Ona o le faaletonu, o le vaega o le Platform Designer e fa'agata le Interrupt Service Line (IRQ).

O ports PIO I/O o lo'o tu'uina ile pito i luga ole HDL file (io_ tulaga mo uafu ulufale, io_ pulea mo ports galuega faatino).

O le laulau o loʻo i lalo o loʻo faʻamatalaina ai le fesoʻotaʻiga faʻailoga mo le tulaga ma le pulea o ports I / O i le DIP switch ma le LED i luga o le atinaʻe pusa.

Laulau 8. PIO Core I/O Taulaga

Taulaga	Bit	Fa'ailoga
Out_port	0	USER_LED SPI polokalame ua mae'a
Out_port	31:1	Fa'apolopolo
I_taulaga	0	USER_DIP fa'alotoifale fa'asolo i tua fa'aagaoioi Off = 1 I luga = 0
	1	USER_DIP FPGA fa'atupuina SYSREF fa'aaga e Tape = 1 I luga = 0
	31:2	Fa'apolopolo.

SPI Matai
O le SPI matai module o se tulaga fa'avae Platform Designer i totonu o le IP Catalog standard library. O lenei module e faʻaaogaina le SPI protocol e faʻafaigofie ai le faʻatulagaina o tagata liliu mai fafo (mo example, ADC, DAC, ma masini uati i fafo) e ala i se avanoa resitala faʻatulagaina i totonu o nei masini.

O le matai o le SPI o loʻo i ai se Avalon e faʻapipiʻiina le mafaufau e fesoʻotaʻi ma le Avalon master (JTAG i Avalon master bridge) e ala i le feso'ota'iga va'aiga fa'amaufa'ailoga a Avalon. E maua e le matai SPI faatonuga fa'atulagaina mai le matai Avalon.

O le SPI matai module e pulea e oʻo atu i le 32 SPI pologa tutoʻatasi. O le SCLK baud rate ua faʻatulagaina i le 20 MHz (vaevaeina e le 5).
O lenei module ua faʻatulagaina i se 4-uaea, 24-bit lautele lautele. Afai e filifilia le Fausia 3-Uaea SPI Module filifiliga, o se isi module e vave ona fa'aliliuina le 4-uaea galuega a le SPI matai i le 3-uaea.

IOPLL
O le IOPLL e fa'atupuina le uati e mana'omia e fa'atupu ai le frame_clk ma le link_clk. Ole uati fa'asino ile PLL e mafai ona fa'atulagaina ae fa'atapula'a ile fa'amaumauga/fa'ailoga ole 33.

Mo mamanu exampe lagolagoina le fua faatatau o faamatalaga o le 24.33024 Gbps, o le fua faatatau o le uati mo frame_clk ma link_clk e 368.64 MHz.
Mo mamanu exampe lagolagoina le fua faatatau o faamatalaga o le 32 Gbps, o le fua faatatau o le uati mo frame_clk ma link_clk e 484.848 MHz.

SYSREF Generator
SYSREF ose fa'ailoga taimi taua mo tagata liliu fa'amatalaga ma F-Tile JESD204C fa'aoga.

Le SYSREF generator i le mamanu exampO lo'o fa'aaogaina mo na'o le fa'ata'ita'iga o le fa'ata'ita'iga o feso'ota'iga lua JESD204C IP. I le JESD204C subclass 1 system level application, e tatau ona e gaosia SYSREF mai le puna lava e tasi e pei o le uati masini.

Mo le F-Tile JESD204C IP, o le SYSREF multiplier (SYSREF_MULP) o le SYSREF pule resitala o loʻo faʻamatalaina ai le vaitaimi SYSREF, o le numera n-integer numera o le E parameter.

E tatau ona e mautinoa E*SYSREF_MULP ≤16. Mo example, afai E=1, o le faatulagaga faaletulafono mo SYSREF_MULP e tatau ona i totonu o le 1–16, ma afai E=3, o le faatulagaga faaletulafono mo SYSREF_MULP e tatau ona i totonu o le 1–5.

Fa'aaliga: Afai e te setiina se SYSREF_MULP i fafo, o le SYSREF generator o le a faʻapipiʻi le seti i SYSREF_MULP=1.
E mafai ona e filifili pe e te manaʻo i le ituaiga SYSREF ia avea ma se pusi e tasi-fana, faʻavaitaimi, poʻo le vaʻa faʻavaitaimi e ala i le Ex.ample Design tab i le F-Tile JESD204C Intel FPGA IP fa'atonu fa'atonu.

Laulau 9. ExampLes of Periodic and Gapped Periodic SYSREF Counter

E	SYSREF_MULP	SYSREF VAITAI (ESYSREF_MULP 32)	Taamilosaga Tiute	Fa'amatalaga
1	1	32	1..31 (Polokalame)	Gapped Vaitaimi
1	1	32	16 (Fa'amau)	Vaitaimi
1	2	64	1..63 (Polokalame)	Gapped Vaitaimi
1	2	64	32 (Fa'amau)	Vaitaimi
1	16	512	1..511 (Polokalame)	Gapped Vaitaimi
1	16	512	256 (Fa'amau)	Vaitaimi
2	3	19	1..191 (Polokalame)	Gapped Vaitaimi
2	3	192	96 (Fa'amau)	Vaitaimi
2	8	512	1..511 (Polokalame)	Gapped Vaitaimi
2	8	512	256 (Fa'amau)	Vaitaimi
2	9 (Fa'asā)	64	32 (Fa'amau)	Gapped Vaitaimi
2	9 (Fa'asā)	64	32 (Fa'amau)	Vaitaimi

Laulau 10. SYSREF Pule Resitala
E mafai ona e toe fa'afouina le SYSREF control registers pe a fai e ese le fa'atulagaina o le resitala nai lo le fa'atulagaina na e fa'ailoaina i le taimi na e faia ai le mamanu fa'atasi.ample. Fa'atulaga le resitala a le SYSREF a'o le'i toe setiina le F-Tile JESD204C Intel FPGA IP. Afai e te filifilia le SYSREF generator fafo e ala i le
sysref_ctrl [7] resitara bit, e mafai ona e le amanaʻia tulaga mo le ituaiga SYSREF, faʻateleina, taamilosaga tiute ma vaega.

Pisi	Tau Fa'atonu	Fa'amatalaga
sysref_ctrl[1:0]	2'b00: Tasi tasi 2'b01: Vaitaimi 2'b10: Gapped fa'avaitaimi	ituaiga SYSREF. Ole tau fa'aletonu e fa'alagolago ile seti SYSREF i le Example Lisiina tab i le F-Tile JESD204C Intel FPGA IP fa'atonu fa'atonu.
sysref_ctrl[6:2]	5'b00001	SYSREF fa'atele. Ole fanua SYSREF_MULP e fa'atatau ile ituaiga SYSREF fa'avaitaimi ma gapped-periodic. E tatau ona e fa'atulagaina le tau fa'atele e fa'amautinoa ai o le tau ESYSREF_MULP o lo'o i le va o le 1 i le 16 a'o le'i alu ese le F-Tile JESD204C IP. Afai o le ESYSREF_MULP tau o lo'o i fafo atu o lenei vaega, o le fa'atele o le tau e fa'aletonu ile 5'b00001.
sysref_ctrl[7]	Auala fa'amatalaga ta'ilua: 1'b1 Simplex TX po'o le RX fa'amaumauga: 1'b0	SYSREF filifili. Ole tau fa'aletonu e fa'alagolago ile fa'atulagaina ole ala fa'amatalaga ile Example Design tab i le F-Tile JESD204C Intel FPGA IP fa'atonu fa'atonu. 0: Simplex TX poʻo RX (SYSREF fafo) 1: Fa'atosina (SYSREF totonu)
sysref_ctrl[16:8]	9'h0	SYSREF ta'amilosaga tiute pe'a fa'avaitaimi le ituaiga SYSREF pe va'a fa'avaitaimi. E tatau ona e faʻatulagaina le taamilosaga tiute aʻo leʻi oʻo i le F-Tile JESD204C IP mai le toe setiina. Tau aupito maualuga = (ESYSREF_MULP32)-1 Mo exampLe: 50% taamilosaga tiute = (ESYSREF_MULP32)/2 Ole ta'amilosaga tiute e fa'aletonu ile 50% pe afai e te le fa'atulagaina lenei fanua resitala, pe afai e te fa'atulagaina le fanua resitala ile 0 pe sili atu nai lo le tau maualuga fa'atagaina.
sysref_ctrl[17]	1'b0	Pulea tusilima pe a tasi le ata o le ituaiga SYSREF. Tusi le 1 e seti ai le faailo SYSREF i le maualuga. Tusi le 0 e seti ai le faailo SYSREF i lalo. E tatau ona e tusia se 1 ona sosoo ai lea ma le 0 e fatu ai se pulusi SYSREF i le ata e tasi.
sysref_ctrl[31:18]	22'h0	Fa'apolopolo.

Toe Seti Fa'asologa
O lenei mamanu exampe aofia ai le toe setiina sequencers se lua:

Toe Seti le Fa'asologa 0—Ta'u le toe setiina i le TX/RX Avalon streaming domain, Avalon memory-mapped domain, PLL autu, TX PHY, TX core, ma SYSREF generator.

Toe Seti le Fa'asologa 1—Uu le toe setiina i le RX PHY ma le RX Core.

3-Uaea SPI
O lenei module e filifili e liliu le SPI interface i le 3-uaea.

Faiga PLL
F-tile e tolu PLL i luga ole laupapa. O nei faiga PLLs o le puna autu uati mo IP faigata (MAC, PCS, ma FEC) ma EMIB kolosi. O lona uiga, pe a e faʻaogaina le faiga o le PLL clocking mode, e le o lokaina poloka e le PMA clock ma e le faʻalagolago i se uati e sau mai le FPGA core. O faiga ta'itasi PLL na'o le fa'atupuina o le uati o lo'o feso'ota'i ma le feso'ota'iga e tasi. Mo example, e te manaʻomia ni PLL se lua e faʻatautaia ai le tasi faʻaoga i le 1 GHz ma le tasi faʻaoga ile 500 MHz. O le fa'aogaina o le PLL e mafai ai ona e fa'aoga tuto'atasi auala ta'itasi e aunoa ma se suiga ole uati e a'afia ai se laina tuaoi.
E mafai e PLL faiga ta'itasi ona fa'aoga so'o se tasi o uati fa'asino FGT valu. E mafai e le System PLLs ona fa'asoa se uati fa'asinoga pe iai fo'i fa'amatalaga fa'amatalaga eseese. E mafai e fesoʻotaʻiga taʻitasi ona filifili po o le a le PLL e faʻaaogaina, ae, pe a filifilia, e faʻamautu, e le mafai ona toe faʻaogaina le faʻaogaina o le toe faʻaleleia.

Fa'amatalaga Fa'atatau
F-tile Architecture ma PMA ma FEC Direct PHY IP User Guide

O nisi fa'amatalaga e uiga i le faiga fa'apolokalame PLL i masini Intel Agilex F-tile.

Fua Fa'ata'ita'i ma Su'e
Ole mamanu fa'atupu ma siaki e aoga mo le fa'atupuina o fa'amaumauga samptusi ma mata'itū mo fa'amoemoega o su'ega.
Fuafuaga 11. Fausia Mamanu Lagolago

Fausia Mamanu	Fa'amatalaga
PRBS mamanu mamanu	Le F-Tile JESD204C mamanu example PRBS mamanu mamanu e lagolagoina le tikeri o polynomials: PRBS23: X23+X18+1 PRBS15: X15+X14+1 PRBS9: X9+X5+1 PRBS7: X7+X6+1
Ramp mamanu generator	O le ramp fa'aopoopo le tau o mamanu i le 1 mo s mulimuli umaample fa'atasi ai ma le lautele o le afi afi o le N, ma ta'avale i luga i le 0 pe a uma vaega i le sample 1. Fa'aaga le ramp mamanu generator e ala i le tusia o le 1 i le bit 2 o le tusi resitala tst_ctl o le poloka pule ED.
Fa'atonu ala ramp mamanu generator	Le F-Tile JESD204C mamanu example lagolagoina le alavai poloaiga ramp mamanu generator i le laina. O le ramp fa'aopoopo le tau o mamanu i le 1 i le 6 vaega o upu fa'atonu. O le fatu amata o se fa'asologa fa'aopoopo i ala uma.

Laulau 12. Su'e Mamanu Lagolago

Su'e Mamanu	Fa'amatalaga
PRBS siaki mamanu	O le fatu fa'ato'a i totonu o le siaki fa'ata'ita'iga e fa'amaopoopo e le tagata lava ia pe a ausia e le F-Tile JESD204C IP le fa'aogaina o le kesi. E mana'omia e le su'esu'e fa'ata'ita'iga le 8 octets mo le fatu fa'ato'a e fa'amaopoopo.
Ramp siaki mamanu	O fa'amatalaga aoga muamua sample mo liliu taitasi (M) ua utaina o le tau muamua o le ramp mamanu. Fa'amatalaga mulimuli sampe tatau ona si'itia le tau i le 1 i ta'amilosaga uati ta'itasi e o'o i le maualuga ona ta'avale lea i le 0.

Su'e Mamanu	Fa'amatalaga
	Mo example, pe a S = 1, N = 16 ma WIDTH_MULP = 2, o le lautele o faʻamatalaga i le tagata liliu mai o le S * WIDTH_MULP * N = 32. O le maualuga o faʻamatalaga sample tau o le 0xFFFF. O le ramp siaki mamanu e fa'amaonia o mamanu tutusa e maua i tagata liliu uma.
Fa'atonu ala ramp siaki mamanu	Le F-Tile JESD204C mamanu example lagolagoina le alavai poloaiga ramp siaki mamanu. O le upu fa'atonu muamua (6 bits) mauaina o lo'o utaina e pei o le tau muamua. O upu fa'atonu i le laina tutusa e tatau ona fa'atuputeleina i le 0x3F ma ta'avale i luga i le 0x00. O le laina poloaiga ramp siaki siaki mamanu mo ramp mamanu i luga o auala uma.

F-Tile JESD204C TX ma RX IP
O lenei mamanu example fa'atagaina oe e fa'atulaga TX/RX ta'itasi i le mode simplex po'o le duplex mode.
Fa'atonuga fa'alua e fa'ataga ai le fa'atinoina o galuega fa'atino a le IP e fa'aogaina ai le fa'asolo i totonu po'o fafo. CSRs i totonu o le IP e le'o fa'atumauina ese e fa'ataga ai le fa'atonutonuina o le IP ma le mata'ituina o tulaga.

F-Tile JESD204C Design Example Uati ma Toe setiina

Le F-Tile JESD204C mamanu example ua i ai se seti o le uati ma toe seti faailoilo.

Laulau 13.Design Example Uati

Faailoga Uati	Fa'atonuga	Fa'amatalaga
mgmt_clk	Ulufale	Uati eseese LVDS ma taimi ole 100 MHz.
refclk_xcvr	Ulufale	Uati fa'asinoga Transceiver fa'atasi ai ma le tele o fa'amaumauga fa'amaumauga/tulaga o le 33.
refclk_core	Ulufale	Uati faasinoga autu e tutusa le taimi e pei o refclk_xcvr.
in_sysref	Ulufale	SYSREF faailoilo. Ole maualuga ole SYSREF ole fua ole fa'amaumauga/(66x32xE).
sysref_out	Tuuina atu
txlink_clk rxlink_clk	Totonu	TX ma le RX feso'ota'iga uati fa'atasi ai ma taimi ole fa'amaumauga/66.
txframe_clk rxframe_clk	Totonu	Uati fa'avaa TX ma RX fa'atasi ai ma taimi ole fa'amaumauga/33 (FCLK_MULP=2) Uati fa'avaa TX ma RX fa'atasi ai ma taimi ole fa'amaumauga/66 (FCLK_MULP=1)
tx_fclk rx_fclk	Totonu	TX ma le RX vaega uati fa'atasi ai ma taimi ole fa'amaumauga/66 (FCLK_MULP=2) TX ma le RX vaega uati maualuga i taimi uma (1'b1) pe a FCLK_MULP=1
spi_SCLK	Tuuina atu	SPI baud rate uati ma taimi ole 20 MHz.

A e utaina le mamanu example i totonu o se masini FPGA, o se mea i totonu ninit_done mea e faʻamautinoa ai o le JTAG i Avalon Master bridge o lo'o toe setiina fa'apea ma isi poloka uma.

O le SYSREF generator o loʻo i ai lona seti tutoʻatasi e tui faʻatasi ai ma le faʻamoemoe mo le txlink_clk ma rxlink_clk uati. O lenei metotia e sili atu le atoatoa i le faʻataʻitaʻiina o le faailo SYSREF mai se vaʻa uati fafo.

Laulau 14. Design Example Toe setiina

Toe Seti Faailoga	Fa'atonuga	Fa'amatalaga
global_rst_n	Ulufale	Oomi ki le lalolagi toe setiina mo poloka uma, vagana ai le JTAG i Avalon Master Bridge.
ninit_done	Totonu	Tulaga mai le Toe Fa'asa'olotoina IP mo le JTAG i Avalon Master Bridge.
edctl_rst_n	Totonu	O le poloka ED Control ua toe setiina e JTAG i Avalon Master Bridge. O ports hw_rst ma global_rst_n e le toe setiina le poloka ED Control.
hw_muamua	Totonu	Fa'amanino ma fa'amalo le hw_rst e ala i le tusi atu i le resitara rst_ctl o le poloka ED Control. fai mai mgmt_rst_in_n pe a fa'amaonia le hw_rst.
mgmt_muamua_i_n	Totonu	Toe setiina mo Avalon fa'afanua fa'amaufa'ailoga o feso'ota'iga IP eseese ma fa'aoga o fa'asologa fa'asologa: j20c_reconfig_reset mo F-Tile JESD204C IP duplex Native PHY spi_rst_n mo le matai SPI pio_rst_n mo le tulaga PIO ma le pulea reset_in0 port of reset sequencer 0 ma le 1 O le global_rst_n, hw_rst, poʻo le edctl_rst_n port ua faʻamaonia le toe setiina i luga ole mgmt_rst_in_n.
sysref_rst_n	Totonu	Toe setiina mo poloka afi SYSREF i le poloka ED Control e faʻaaoga ai le seti seti 0 reset_out2 uafu. O le toe setiina sequencer 0 reset_out2 port deasserts le toe setiina pe afai e loka PLL autu.
core_pll_rst	Totonu	Toe setiina le PLL autu e ala i le seti sequencer 0 reset_out0 port. O le PLL autu e toe setiina pe a fai le mgmt_rst_in_n toe setiina.
j204c_tx_avs_rst_n	Totonu	Toe setiina le F-Tile JESD204C TX Avalon fa'afanua fa'amaufa'ailoga e ala i le toe setiina o le fa'asologa 0. O le TX Avalon fa'afanua fa'amaufa'ailoga e fa'amaonia pe a fa'amauina le mgmt_rst_in_n.
j204c_rx_avs_rst_n	Totonu	Toe setiina le F-Tile JESD204C TX Avalon fa'afanua fa'afanua e ala i le toe setiina o le fa'asologa 1. O le RX Avalon fa'afanua fa'amaufa'ailoga e fa'ailoa mai pe a fa'amauina le mgmt_rst_in_n.
j204c_tx_rst_n	Totonu	Toe setiina le F-Tile JESD204C TX so'otaga ma felauaiga i totonu o txlink_clk, ma txframe_clk, domains. Le toe setiina sequencer 0 reset_out5 uafu toe setiina j204c_tx_rst_n. O le toe setiina lea e fa'agata pe a loka le PLL autu, ma fa'ailoa mai ai fa'ailoga tx_pma_ready ma tx_ready.
j204c_rx_rst_n	Totonu	Toe setiina le F-Tile JESD204C RX so'oga ma felauaiga i totonu, rxlink_clk, ma rxframe_clk domains.

Toe Seti Faailoga	Fa'atonuga	Fa'amatalaga
		O le toe setiina sequencer 1 reset_out4 uafu toe setiina j204c_rx_rst_n. Le toe setiina deasserts pe a loka le PLL autu, ma le rx_pma_ready ma rx_ready faailoilo ua faʻamaonia.
j204c_tx_rst_ack_n	Totonu	Toe seti le faailo o le faatalofa i le j204c_tx_rst_n.
j204c_rx_rst_ack_n	Totonu	Toe seti le faailo o le faatalofa i le j204c_rx_rst_n.

Ata 8. Fa'asologa o Taimi mo le Design Example Toe setiina

F-Tile JESD204C Design Example Faailoga

Laulau 15. Fa'ailoga Fa'afeso'ota'i Fa'atonu

Fa'ailoga	Fa'atonuga	Fa'amatalaga
Uati ma Toe setiina
mgmt_clk	Ulufale	100 MHz uati mo pulega faiga.
refclk_xcvr	Ulufale	Uati fa'asino mo le F-tile UX QUAD ma le System PLL. E tutusa ma fa'amaumauga fa'amaumauga/fa'ailoga o le 33.
refclk_core	Ulufale	Uati faasinoga PLL autu. Fa'aoga tutusa le taimi ole uati e pei ole refclk_xcvr.
in_sysref	Ulufale	SYSREF faailo mai fafo SYSREF generator mo JESD204C Subclass 1 faatinoga.
sysref_out	Tuuina atu	SYSREF faʻailoga mo le JESD204C Subclass 1 faʻatinoga na faia e le masini FPGA mo le mamanu muamuaampna'o le fa'avaeina o feso'ota'iga.

Fa'ailoga	Fa'atonuga	Fa'amatalaga
SPI
spi_SS_n[2:0]	Tuuina atu	Malosiaga maualalo, SPI pologa filifili faailoilo.
spi_SCLK	Tuuina atu	SPI fa'asologa uati.
spi_sdio	Ulufale/Auga	Faʻamatalaga faʻamatalaga mai le matai i le pologa i fafo. Tu'u fa'amatalaga mai le pologa i fafo i le matai.

Fa'ailoga	Fa'atonuga	Fa'amatalaga
Fa'aaliga:A fa'atupuina le 3-Wire SPI Module filifiliga e mafai.
spi_MISO Manatua: Pe a le mafai le filifiliga Fausia 3-Uaea SPI Module.	Ulufale	Tuuina atu faʻamatalaga mai le pologa i fafo i le matai SPI.
spi_MOSI Fa'aaliga: Pe a le mafai le filifiliga Fausia 3-Uaea SPI Module.	Tuuina atu	Faʻamatalaga faʻamatalaga mai le matai SPI i le pologa fafo.

Fa'ailoga	Fa'atonuga	Fa'amatalaga
ADC/DAC
tx_serial_data[LINK*L-1:0]	Tuuina atu	Fa'amatalaga fa'asologa fa'asologa o fa'amatalaga fa'asalalau maualuga i le DAC. O lo'o fa'apipi'i le uati i le fa'asologa o fa'amaumauga.
tx_serial_data_n[LINK*L-1:0]
rx_serial_data[LINK*L-1:0]	Ulufale	Eseese maualuga saoasaoa fa'amaumauga fa'aulu mai le ADC. Ua toe maua mai le uati mai le fa'asologa o fa'amaumauga.
rx_serial_data_n[LINK*L-1:0]

Fa'ailoga	Fa'atonuga	Fa'amatalaga
Faamoemoega Lautele I/O
ta'ita'i_tagata[3:0]	Tuuina atu	Fa'ailoa le tulaga mo tulaga nei: [0]: Ua mae'a polokalame a le SPI [1]: TX so'oga sese [2]: RX so'oga sese [3]: Fa'ailoga siaki fa'asologa mo Avalon fa'asalalau fa'amaumauga
user_dip[3:0]	Ulufale	Faiga fa'aoga DIP sui fa'aoga: [0]: Fa'alotoifale fa'asologa fa'asolo i tua e mafai [1]: FPGA-fausia SYSREF mafai [3:2]: Faasao

Fa'ailoga	Fa'atonuga	Fa'amatalaga
Out-of-band (OOB) ma Tulaga
rx_patchk_data_error[LINK-1:0]	Tuuina atu	A fa'ailoa mai lea fa'ailoga, e fa'ailoa mai ai ua iloa e le siaki fa'ata'ita'iga se mea sese.
rx_link_error[LINK-1:0]	Tuuina atu	Pe a faʻaalia lenei faʻailoga, o loʻo faʻaalia ai le JESD204C RX IP na faʻaalia le faʻalavelave.
tx_link_error[LINK-1:0]	Tuuina atu	A faʻaalia lenei faʻailoga, o loʻo faʻaalia ai le JESD204C TX IP na faʻaalia le faʻalavelave.
emb_lock_out	Tuuina atu	Pe a faʻaalia lenei faʻailoga, e faʻaalia ai le JESD204C RX IP ua ausia le loka EMB.
loka_i fafo	Tuuina atu	A fa'ailoa mai lea fa'ailoga, e fa'ailoa mai ai ua lokaina le ulutala o le sync JESD204C RX IP.

Fa'ailoga	Fa'atonuga	Fa'amatalaga
Avalon Streaming
rx_avst_valid[LINK-1:0]	Ulufale	Fa'ailoa mai pe fa'aliliu sample fa'amaumauga i le fa'asologa o talosaga e aoga pe le aoga. 0: E le aoga fa'amaumauga 1: Faʻamaumauga e aoga
rx_avst_data[(TOTAL_SAMPLE*N)-1:0 ]	Ulufale	Faaliliu sample faʻamatalaga i le faʻasologa o talosaga.

F-Tile JESD204C Design Example Pulea Resitala

Le F-Tile JESD204C mamanu exampLe resitara i le ED Control poloka faʻaaoga byte-addressing (32 bits).

Laulau 16. Design Example Fa'afanua Fa'asinomaga
O nei 32-bit ED Control poloka resitala o loʻo i totonu o le mgmt_clk domain.

Vaega	tuatusi
F-Tile JESD204C TX IP	0x000C_0000 – 0x000C_03FF
F-Tile JESD204C RX IP	0x000D_0000 – 0x000D_03FF
Pulea SPI	0x0102_0000 – 0x0102_001F
PIO Pulea	0x0102_0020 – 0x0102_002F
Tulaga PIO	0x0102_0040 – 0x0102_004F
Toe seti le Fa'asologa 0	0x0102_0100 – 0x0102_01FF
Toe seti le Fa'asologa 1	0x0102_0200 – 0x0102_02FF
ED Pulea	0x0102_0400 – 0x0102_04FF
F-Tile JESD204C IP transceiver PHY Reconfig	0x0200_0000 – 0x023F_FFFF

Siata 17. Resitala Avanoa Ituaiga ma Fa'amatalaga
O lo'o fa'amatala mai e le laulau lenei le ituaiga avanoa e resitala mo Intel FPGA IPs.

Ituaiga Avanoa	Uiga
RO/V	Polokalama na'o le faitau (leai se aafiaga ile tusitusi). Atonu e eseese le tau.
RW	E faitau ma toe fa'afo'i mai e le polokalame le tau o lo'o iai nei. E tusia ma seti e le polokalame le vaega i le tau e mana'omia.
RW1C	E faitau ma toe fa'afo'i mai e le polokalame le tau o lo'o iai nei. E tusia e le polokalame le 0 ma e leai se aoga. E tusia e le polokalame le 1 ma fa'amama le bit i le 0 pe afai ua seti le bit i le 1 e meafaigaluega. O meafaigaluega e setiina le bit i le 1. E maualuga atu le fa'amuamua i lo le seti o meafaigaluega.

Laulau 18. ED Control Address Faafanua

Offset	Resitala Igoa
0x00	rst_ctl
0x04	muamua_sts0
*faaauau…*

Offset	Resitala Igoa
0x10	rst_sts_deteksi0
0x40	sysref_ctl
0x44	sysref_sts
0x80	tst_ctl
0x8c	tst_err0

Laulau 19. ED Pulea poloka Pulea ma Resitala Tulaga

Byte Offset	Resitala	Igoa	Avanoa	Toe setiina	Fa'amatalaga
0x00	rst_ctl	rst_assert	RW	0x0	Toe setiina le pule. [0]: Tusi le 1 e fai ai le seti. (hw_rst) Toe tusi le 0 e le toe setiina. [31:1]: Faasao.
0x04	muamua_sts0	tulaga_muamua	RO/V	0x0	Toe setiina tulaga. [0]: Tulaga loka PLL Autu. [31:1]: Faasao.
0x10	rst_sts_dete cted0	rst_sts_set	RW1C	0x0	SYSREF tulaga su'esu'e pito mo totonu po'o fafo SYSREF generator. [0]: Taua o le 1 Fa'ailoa mai o le SYSREF si'isi'i pito o lo'o maua mo le va'aiga laiti 1. E mafai e le polokalame ona tusi le 1 e fa'amama ai le vaega lea ina ia mafai ai ona su'esu'e pito SYSREF fou. [31:1]: Faasao.
0x40	sysref_ctl	sysref_contr ol	RW	Fa'amatalaga fa'amatalaga Tasi tasi: 0x00080	SYSREF pulea. Fa'asino i Laulau 10 i le itulau 17 mo nisi fa'amatalaga e uiga i le fa'aogaina o lenei tusi resitala.
				Vaitaimi:	Fa'aaliga: E faalagolago le tau toe setiina
				0x00081	le ituaiga SYSREF ma F-Tile
				Gapped-vaitaimi:	JESD204C IP fa'amaumauga ala ala fa'asologa fa'asologa.
				0x00082
				TX poʻo RX faʻamatalaga
				ala
				Tasi tasi:
				0x00000
				Vaitaimi:
				0x00001
				avanoa-
				faavaitaimi:
				0x00002
0x44	sysref_sts	sysref_statu s	RO/V	0x0	SYSREF tulaga. O lenei tusi resitala o loʻo i ai le taimi lata mai o le SYSREF ma le faʻatulagaina o tiute o le afi SYSREF i totonu. Fa'asino i Laulau 9 i le itulau 16 mo le tau fa'aletulafono o le vaitaimi o le SYSREF ma le taamilosaga o tiute.
*faaauau…*

Byte Offset	Resitala	Igoa	Avanoa	Toe setiina	Fa'amatalaga
					[8:0]: Vaitaimi SYSREF. A o le tau o le 0xFF, o le SYSREF vaitaimi = 255 A o le tau pe afai 0x00, o le SYSREF vaitaimi = 256. [17:9]: SYSREF taamilosaga tiute. [31:18]: Faasao.
0x80	tst_ctl	tst_control	RW	0x0	Pulea su'ega. Fa'aoga lenei tusi resitala ina ia mafai ai ona fa'atino su'ega su'ega eseese mo le generator mamanu ma siaki. [1:0] = fanua faasao [2] = ramp_test_ctl 1'b0 = Fa'aagaoioia PRBS mamanu mamanu ma siaki 1'b1 = E mafai ai le ramp mamanu generator ma siaki [31:3]: Faasao.
0x8c	tst_err0	tst_error	RW1C	0x0	Fa'ailoga fu'a mo Link 0. A o'o le bit 1'b1, e ta'u mai ai ua tupu se mea sese. E tatau ona e fo'ia le mea sese a'o le'i tusia le 1'b1 i le vaega ta'itasi e fa'amama ai le fu'a sese. [0] = Fa'atonu siaki siaki [1] = tx_link_error [2] = rx_link_error [3] = Poloaiga siaki siaki sese [31:4]: Fa'asao.

Tala Fa'asolopito o Fa'amaumauga mo le F-Tile JESD204C Intel FPGA IP Design Example User Guide

Fa'amatalaga Fa'amaumauga	Intel Quartus Prime Version	IP Version	Suiga
2021.10.11	21.3	1.0.0	Fa'asalalauga muamua.

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intel F-Tile JESD204C Intel FPGA IP Design Example [pdf] Taiala mo Tagata Fa'aoga
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F-Tile JESD204C Intel FPGA IP Design Example

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