F-Tile JESD204C Intel FPGA IP Tsim Example

Hais txog F-Tile JESD204C Intel® FPGA IP Tsim Example User Guide

Cov neeg siv phau ntawv qhia no muab cov yam ntxwv, cov lus qhia siv, thiab cov lus piav qhia ntxaws txog tus qauv tsim examples rau F-Tile JESD204C Intel® FPGA IP siv Intel Agilex™ li.

Lub Hom Phiaj

Cov ntaub ntawv no yog npaj rau:

• Tus kws tsim qauv tsim los ua tus IP xaiv thaum lub sijhawm tsim qauv tsim qauv theem
• Cov neeg tsim khoom kho vajtse thaum sib koom ua ke IP rau hauv lawv cov qauv tsim
• Validation engineers thaum lub sij hawm system simulation thiab kho vajtse validation theem

Cov ntaub ntawv ntsig txog
Cov lus hauv qab no teev lwm cov ntaub ntawv siv uas cuam tshuam nrog F-Tile JESD204C Intel FPGA IP.

Rooj 1. Cov ntaub ntawv ntsig txog

Kev siv	Kev piav qhia
F-Tile JESD204C Intel FPGA IP Tus Neeg Siv Qhia	Muab cov ntaub ntawv hais txog F-Tile JESD204C Intel FPGA IP.
F-Tile JESD204C Intel FPGA IP Tso Lus Sau	Sau cov kev hloov pauv tau ua rau F-Tile JESD204C F-Tile JESD204C hauv ib qho kev tso tawm.
Intel Agilex Device Data Sheet	Cov ntaub ntawv no piav qhia txog cov yam ntxwv hluav taws xob, hloov cov yam ntxwv, kev teeb tsa tshwj xeeb, thiab lub sijhawm rau Intel Agilex li.

Acronyms thiab Glossary

Table 2. Sau npe

Lub ntsiab lus	Kev nthuav dav
LEMC	Local Extended Multiblock Clock
FC	Ncej moos tus nqi
ADC	Analog rau Digital Converter
DAC	Digital rau Analog Converter
DSP	Digital Signal Processor
TX	Transmitter
RX	Tus txais

Lub ntsiab lus	Kev nthuav dav
DLL	Cov ntaub ntawv txuas txheej
CSR	Tswj thiab teev npe
CRU	Clock thiab Reset Unit
ISR	Kev Pab Cuam Tshuam
FIFO	Thawj-hauv-Thawj-Tawm
SERDES	Serializer Deserializer
ECC	Yuam Kev Kho Code
FEC	Piav Kev Yuam Kev Xa Mus
SERR	Kev Tshawb Fawb Ib Leeg (hauv ECC, kho tau)
DERR	Ob chav kuaj pom yuam kev (hauv ECC, tuag)
PRBS	Pseudorandom binary sequence
MAC	Media Access Controller. MAC suav nrog cov txheej txheem sublayer, thauj txheej, thiab cov ntaub ntawv txuas txheej.
PHY	Lub cev txheej. PHY feem ntau suav nrog cov txheej txheem lub cev, SERDES, tsav tsheb, txais thiab CDR.
PCS	Physical Coding Sub-layer
PMA	Lub cev nruab nrab txuas
RBD	RX Buffer Ncua sijhawm
UI	Unit Interval = duration of serial bit
RBD suav	RX Buffer Delay txoj kab tshiab kawg tuaj txog
RBD offset	RX Buffer Ncua sijhawm tso tawm lub sijhawm
SH	Sync header
TL	Thauj txheej
EMIB	Embedded Multi-die Interconnect Choj

Table 3. Glossary List

Lub sij hawm	Kev piav qhia
Hloov ntaus ntawv	ADC los yog DAC converter
Logic Device	FPGA los yog ASIC
Octet	Ib pawg ntawm 8 khoom, ua haujlwm rau kev nkag mus rau 64/66 encoder thiab tso tawm los ntawm lub tshuab txiav
Nibble	Ib txheej ntawm 4 khoom uas yog lub hauv paus ua haujlwm ntawm JESD204C specifications
Thaiv	Lub cim 66-ntsis tsim los ntawm 64/66 encoding tswvyim
Kab Tus Nqi	Cov ntaub ntawv muaj txiaj ntsig zoo ntawm serial txuas Txoj kab nqes tus nqi = (Mx Sx N'x 66/64 x FC) / L
Txuas moos	Link Clock = Txoj kab nqes/66.
Ncej	Ib txheej sib law liag octet nyob rau hauv uas txoj hauj lwm ntawm txhua octet tuaj yeem txheeb xyuas tau los ntawm kev siv rau lub teeb liab sib dhos.
Ncej moos	Lub moos system uas khiav ntawm tus ncej tus nqi, uas yuav tsum yog 1x thiab 2x txuas moos.

Lub sij hawm	Kev piav qhia
Samples per frame moos	Samples per moos, tag nrho samples nyob rau hauv ncej moos rau lub converter ntaus ntawv.
LEMC	Lub moos sab hauv siv los kho tus ciam teb ntawm qhov txuas txuas ntxiv ntawm txoj kab ntawm txoj kab thiab mus rau cov ntaub ntawv sab nraud (SYSREF lossis Subclass 1).
SIB 0	Tsis muaj kev txhawb nqa rau kev txiav txim siab latency. Cov ntaub ntawv yuav tsum raug tso tawm tam sim ntawm txoj kab mus rau txoj kab deskew ntawm receiver.
SIB 1	Kev txiav txim siab latency siv SYSREF.
Multipoint Txuas	Cov cuab yeej sib txuas nrog 2 lossis ntau dua cov khoom siv hloov pauv.
64B / 66B Encoding	Kab code uas qhia 64-ntsis cov ntaub ntawv mus rau 66 khoom los tsim ib qho thaiv. Cov ntaub ntawv theem pib yog ib qho thaiv uas pib nrog 2-ntsis sync header.

Table 4. Cov cim

Lub sij hawm	Kev piav qhia
L	Tus lej ntawm txoj kab rau ib qho khoom siv converter
M	Tus naj npawb ntawm converters rau ib lub cuab yeej
F	Tus naj npawb ntawm octets ib thav duab ntawm ib txoj kab
S	Tus naj npawb ntawm samples kis ib zaug converter ib lub voj voog thav duab
N	Hloov daws teeb meem
N'	Tag nrho cov naj npawb ntawm cov khoom ib sample nyob rau hauv tus neeg siv cov ntaub ntawv hom
CS	Tus naj npawb ntawm cov khoom tswj ib qho kev hloov pauv sample
CF	Tus naj npawb ntawm cov lus tswj ib lub sijhawm teev sijhawm ib qhov txuas
HD	High Density neeg siv cov ntaub ntawv hom
E	Tus naj npawb ntawm multiblock nyob rau hauv ib qho txuas ntxiv multiblock

F-Tile JESD204C Intel FPGA IP Tsim Example Quick Start Guide

F-Tile JESD204C Intel FPGA IP tsim examples rau Intel Agilex pab kiag li lawm nta ib simulating testbench thiab ib tug kho vajtse tsim uas txhawb kev muab tso ua ke thiab kho vajtse kuaj.
Koj tuaj yeem tsim F-Tile JESD204C tsim examples los ntawm IP catalog hauv Intel Quartus® Prime Pro Edition software.

Daim duab 1. Kev Txhim Kho Stages rau Design Example

Tsim Exampthiab Block Diagram

Daim duab 2. F-Tile JESD204C Tsim Example High-level Block Diagram

Design example muaj cov nram qab no modules:

• Platform Designer system
  • F-Tile JESD204C Intel FPGA IP
  • JTAG mus rau Avalon Master choj
  • Parallel I/O (PIO) maub los
  • Serial Port Interface (SPI)-master module- IOPLL
  • SYSREF generator
  • Example Design (ED) Control CSR
  • Pib dua sequencers
• System PLL
• Qauv generator
• Qauv checker

Table 5. Tsim Exampua Modules

Cheebtsam	Kev piav qhia
Platform Designer system	Lub Platform Designer system instantiates F-Tile JESD204C IP cov ntaub ntawv txoj kev thiab txhawb cov khoom siv.
F-Tile JESD204C Intel FPGA IP	Lub Platform Designer subsystem muaj TX thiab RX F-Tile JESD204C IPs instantiated ua ke nrog duplex PHY.
JTAG mus rau Avalon Master choj	Tus choj no muab qhov system console host nkag mus rau lub cim xeeb-mapped IP hauv kev tsim los ntawm JTAG interface.
Parallel I/O (PIO) maub los	Cov maub los no muab lub cim xeeb-mapped interface rau sampling thiab tsav tsheb lub hom phiaj I/O ports.
SPI tus tswv	Qhov module no tswj cov kev hloov pauv ntawm cov ntaub ntawv teeb tsa mus rau SPI interface ntawm lub converter kawg.
SYSREF generator	Lub tshuab hluav taws xob SYSREF siv lub moos txuas ua lub sijhawm siv thiab tsim SYSREF pulses rau F-Tile JESD204C IP. Nco tseg: Qhov no tsim example siv lub tshuab hluav taws xob SYSREF los ua kom pom cov duplex F-Tile JESD204C IP txuas pib. Hauv F-Tile JESD204C subclass 1 system daim ntawv thov, koj yuav tsum tsim cov SYSREF los ntawm tib qhov chaw raws li lub moos.
IOPLL	Qhov no tsim example siv IOPLL los tsim cov neeg siv moos rau kev xa cov ntaub ntawv mus rau F-Tile JESD204C IP.
ED Control CSR	Cov qauv no muab SYSREF nrhiav kom paub tswj thiab xwm txheej, thiab kuaj cov qauv tswj thiab xwm txheej.
Pib dua sequencers	Qhov no tsim example muaj 2 reset sequencers: Pib dua Sequence 0-Tau qhov pib dua rau TX/RX Avalon® streaming domain, Avalon nco-mapped domain, core PLL, TX PHY, TX core, thiab SYSREF generator. Rov pib dua ib ntus 1-Tau qhov pib dua rau RX PHY thiab RX core.
System PLL	Lub moos tseem ceeb rau F-tile nyuaj IP thiab EMIB hla.
Qauv generator	Tus qauv generator tsim ib qho PRBS lossis ramp qauv.
Qauv checker	Tus qauv kuaj xyuas qhov PRBS lossis ramp qauv tau txais, thiab chij qhov yuam kev thaum nws pom qhov tsis sib xws ntawm cov ntaub ntawv sample.

Software Yuav Tsum Tau

Intel siv cov software hauv qab no los sim tus tsim examples hauv Linux system:

• Intel Quartus Prime Pro Edition software
• Questa*/ModelSim* los yog VCS*/VCS MX simulator

Tsim tus Tsim

Tsim kom muaj tus tsim examplos ntawm tus IP parameter editor:

1. Tsim ib qhov project tsom Intel Agilex F-tile ntaus ntawv tsev neeg thiab xaiv cov khoom xav tau.
2. Hauv IP Catalog, Cov Cuab Yeej ➤ IP Catalog, xaiv F-Tile JESD204C Intel FPGA IP.
3. Qhia meej lub npe saum toj kawg nkaus thiab cov ntawv tais ceev tseg rau koj qhov kev cai IP hloov pauv. Nyem OK. Cov parameter editor ntxiv rau sab saum toj-theem .ip file mus rau qhov project tam sim no tau txais. Yog tias koj raug ceeb toom kom manually ntxiv .ip file mus rau qhov project, nyem qhov Project ➤ Ntxiv / Tshem tawm Files hauv Project ntxiv rau file.
4. Hauv qab Example Design tab, qhia tus tsim example parameters raws li tau piav qhia hauv Design Example Parameters.
5. Nyem Tsim Example Design.

Lub software tsim tag nrho cov tsim files nyob rau hauv sub-directories. Cov no files yuav tsum tau khiav simulation thiab muab tso ua ke.

Tsim Example Parameters
F-Tile JESD204C Intel FPGA IP parameter editor suav nrog Example Tsim tab rau koj kom qhia meej qee yam tsis ua ntej tsim cov qauv tsim example.

Table 6. Parameters hauv Example Design Tab

Parameter	Kev xaiv	Kev piav qhia
Xaiv Tsim	Qhov System Console Control Tsis muaj	Xaiv qhov system console tswj kom nkag mus rau tus tsim example cov ntaub ntawv txoj kev los ntawm qhov system console.
Kev simulation	Rau, Tawm	Qhib rau tus IP los tsim qhov tsim nyog files rau simulating tus tsim example.
Synthesis	Rau, Tawm	Qhib rau tus IP los tsim qhov tsim nyog files rau Intel Quartus Prime muab tso ua ke thiab kho vajtse ua qauv qhia.
HDL hom ntawv (rau simulation)	Verilog VDHL	Xaiv HDL hom ntawv ntawm RTL files rau simulation.
HDL hom ntawv (rau synthesis)	Verilog nkaus xwb	Xaiv HDL hom ntawv ntawm RTL files rau synthesis.

Parameter	Kev xaiv	Kev piav qhia
Tsim 3-xaim SPI module	Rau, Tawm	Tig rau kom pab tau 3-xaim SPI interface hloov 4-xaim.
Sysref hom	Ib rab phom Lub caij nyoog Gapped periodic	Xaiv seb koj puas xav kom SYSREF kev sib raug zoo los ua ib qho kev txhaj tshuaj mem tes hom, ntu ntu, lossis ntu ntu, raws li koj xav tau tsim thiab lub sijhawm hloov pauv. Kev txhaj tshuaj ib zaug-Xaiv qhov kev xaiv no los pab SYSREF los ua ib qho kev txhaj tshuaj mem tes. Lub sysref_ctrl[17] sau npe me ntsis tus nqi yog 0. Tom qab F-Tile JESD204C IP reset deasserts, hloov lub sysref_ctrl[17] sau npe tus nqi ntawm 0 mus rau 1, ces mus rau 0, rau ib tug txhaj tshuaj SYSREF mem tes. Periodic-SYSREF nyob rau hauv lub sij hawm hom muaj 50:50 lub luag hauj lwm voj voog. SYSREF lub sijhawm yog E*SYSREF_MULP. Gapped periodic—SYSREF muaj programmable luag hauj lwm voj voog ntawm granularity ntawm 1 txuas moos voj voog. SYSREF lub sijhawm yog E*SYSREF_MULP. Rau kev teeb tsa lub voj voog tawm ntawm lub luag haujlwm, SYSREF tiam thaiv yuav tsum tau txiav txim siab 50: 50 lub voj voog ua haujlwm. Xa mus rau lub SYSREF Lub tshuab hluav taws xob seem kom paub ntau ntxiv txog SYSREF lub sij hawm.
Xaiv lub rooj tsavxwm	Tsis muaj	Xaiv lub rooj tsavxwm rau tus tsim example. Tsis muaj - Qhov kev xaiv no tsis suav nrog cov khoom siv kho vajtse rau tus tsim example. Txhua tus pin txoj haujlwm yuav raug teeb tsa rau tus pins virtual.
Xeem Qauv	PIB-7 PIB-9 PIB-15 PIB-23 Ramp	Xaiv cov qauv tsim hluav taws xob thiab cov qauv kuaj xyuas. Pattern Generator—JESD204C txhawb PRBS qauv generator ib cov ntaub ntawv sample. Qhov no txhais tau hais tias qhov dav ntawm cov ntaub ntawv yog N + CS kev xaiv. PRBS qauv generator thiab checker yog pab tau rau tsim cov ntaub ntawv sample stimulus rau kev sim thiab nws tsis sib xws nrog PRBS xeem hom ntawm ADC / DAC converter. Ramp Pattern Generator-JESD204C txuas txheej ua haujlwm ib txwm tab sis kev thauj mus los tom qab raug xiam oob khab thiab cov tswv yim los ntawm lub formatter tsis quav ntsej. Txhua txoj kab xa cov kwj octet zoo ib yam uas nce los ntawm 0x00 rau 0xFF thiab rov ua dua. Ramp qauv kuaj yog pab tau los ntawm prbs_test_ctl. PRBS Pattern Checker-JESD204C PRBS scrambler yog tus kheej synchronizing thiab nws xav tias thaum tus tub ntxhais IP tuaj yeem txiav txim siab txuas mus, cov noob scrambler twb synchronized. PRBS scrambling noob yuav siv li 8 octets rau tus kheej pib. Ramp Pattern Checker-JESD204C scrambling yog tus kheej synchronizing thiab nws xav tias thaum tus tub ntxhais IP tuaj yeem txiav txim siab txuas mus, cov noob scrambling twb synchronized. Thawj qhov siv tau octet yog loaded li ramp thawj tus nqi. Cov ntaub ntawv tom ntej yuav tsum nce mus txog 0xFF thiab dov mus rau 0x00. Ramp tus qauv checker yuav tsum kuaj xyuas cov qauv zoo ib yam thoob plaws txhua txoj kab.
Pab kom internal serial loopback	Rau, Tawm	Xaiv lub serial loopback sab hauv.
Qhib Command Channel	Rau, Tawm	Xaiv cov qauv hais kom ua channel.

Directory Structure
F-Tile JESD204C tsim example directory muaj generated files rau tus tsim examples.

Daim duab 3. Directory Structure rau F-Tile JESD204C Intel Agilex Tsim Example

Table 7. Phau ntawv Files

Cov ntaub ntawv	Files
ed/rtl ib	tx j204c_f_tx_ip.qsys j204c_f tx_ss.qsys altera_s10_user_rst_clkgate_0.ip j204c f_se_outbuf_1bit.ip
simulation/tus qhia	modelim_sim.tcl tb_top_waveform.do
simulation/synopsys	vcs ua vcs_sim.sh tb_top_wave_ed.do vcsmx ua vcsmx_sim.sh tb_top_wave_ed.do

Simulating Design Exampua Testbench

Design example testbench simulates koj tsim tsim.

Daim duab 4. Cov txheej txheem

Txhawm rau simulate tus tsim, ua cov kauj ruam hauv qab no:

1. Hloov cov npe ua haujlwm rauample_design_directory>/simulation/ .
2. Hauv kab hais kom ua, khiav cov ntawv simulation. Cov lus hauv qab no qhia cov lus txib kom khiav cov kev txhawb nqa simulators.

Simulator	txib
Questa/ModelSim	vsim -do modelim_sim.tcl
	vsim -c -do modelim_sim.tcl (tsis muaj Questa / ModelSim GUI)
VCS	sh vcs_sim.sh
VCS MX	sh vcsmx_sim.sh

Lub simulation xaus nrog cov lus uas qhia seb qhov kev khiav tau ua tiav lossis tsis tau.

Daim duab 5. Simulation ua tau tiav
Daim duab no qhia txog cov lus simulation ua tiav rau VCS simulator.

Compiling tus Design Example

Txhawm rau muab tso ua ke-tsuas yog example project, ua raws li cov kauj ruam no:

1. Xyuas kom muab tso ua ke tsim example tiam tag.
2. Hauv Intel Quartus Prime Pro Edition software, qhib Intel Quartus Prime Pro Edition projectample_design_ directory>/ed/quartus.
3. Nyob rau hauv cov ntawv qhia zaub mov, nyem Start Compilation.

Cov lus piav qhia ntxaws rau F-Tile JESD204C Tsim Example

F-Tile JESD204C tsim example qhia txog kev ua haujlwm ntawm cov ntaub ntawv streaming siv hom loopback.
Koj tuaj yeem teev cov kev teeb tsa ntawm koj xaiv thiab tsim cov qauv tsim example.
Design example tsuas yog muaj nyob rau hauv hom duplex rau ob qho tib si Base thiab PHY variant. Koj tuaj yeem xaiv Base nkaus xwb lossis PHY nkaus xwb tab sis tus IP yuav tsim tus qauv tsim example rau Base thiab PHY.

Nco tseg:  Qee cov ntaub ntawv tus nqi siab configuration yuav ua tsis tau lub sij hawm. Txhawm rau zam lub sijhawm tsis ua haujlwm, xav txog kev qhia qis qis qis zaus ntau zaus (FCLK_MULP) tus nqi hauv Configurations tab ntawm F-Tile JESD204C Intel FPGA IP parameter editor.

Qhov System Cheebtsam

F-Tile JESD204C tsim example muab software-raws li kev tswj ntws uas siv lub zog tswj chav nrog lossis tsis muaj kev txhawb nqa console.

Design example enables nws pib txuas mus rau hauv thiab sab nraud loopback hom.

JTAG mus rau Avalon Master Choj
Tus J.TAG rau Avalon Master Choj muab kev sib txuas ntawm tus tswv tsev kom nkag mus rau lub cim xeeb-mapped F-Tile JESD204C IP thiab peripheral IP tswj thiab cov xwm txheej sau npe los ntawm JTAG interface.

Daim duab 6. System nrog JTAG mus rau Avalon Master Choj Core

Nco tseg:  Lub moos moos yuav tsum yog tsawg kawg 2X sai dua JTAG moos. Lub kaw lus moos yog mgmt_clk (100MHz) hauv qhov tsim no example.

Parallel I/O (PIO) Core
Qhov sib piv cov tswv yim / tso zis (PIO) core nrog Avalon interface muab lub cim xeeb-mapped interface ntawm Avalon nco-mapped qhev chaw nres nkoj thiab lub hom phiaj I/O ports. Cov chaw nres nkoj I/O txuas rau ntawm-chip tus neeg siv lub logic, lossis rau I / O tus pins uas txuas rau cov khoom siv sab nraud rau FPGA.

Daim duab 7. PIO Core nrog Input Ports, Output Ports, thiab IRQ Support
Los ntawm lub neej ntawd, lub Platform Designer tivthaiv cuam tshuam rau Interrupt Service Line (IRQ).

PIO I / O cov chaw nres nkoj tau muab tso rau ntawm qib siab HDL file (io_ xwm txheej rau input ports, io_ tswj rau cov zis ports).

Cov lus hauv qab no piav qhia txog cov teeb liab txuas rau cov xwm txheej thiab tswj I / O cov chaw nres nkoj rau DIP hloov thiab LED ntawm cov khoom siv txhim kho.

Table 8. PIO Core I/O Ports

Chaw nres nkoj	Me ntsis	Teeb liab
Tawm_port	0	USER_LED SPI programming ua tiav
	31:1 ua	Khaws tseg
Hauv_port	0	USER_DIP internal serial loopback pab kom Off = 1 Nws = 0
	1	USER_DIP FPGA-tsim SYSREF pab tawm = 1 Nws = 0
	31:2 ua	Khaws tseg.

SPI Master
SPI master module yog tus qauv Platform Designer tivthaiv hauv IP Catalog tus qauv tsev qiv ntawv. Cov qauv no siv SPI raws tu qauv los pab txhawb kev teeb tsa ntawm cov hloov pauv sab nraud (example, ADC, DAC, thiab lub tshuab hluav taws xob sab nraud) ntawm qhov chaw sau npe hauv cov khoom siv no.

Tus tswv SPI muaj Avalon nco-mapped interface uas txuas rau Avalon tswv (JTAG mus rau Avalon tus choj) ntawm Avalon nco-mapped interconnect. Tus tswv SPI tau txais cov lus qhia kev teeb tsa los ntawm Avalon tus tswv.

SPI tus tswv module tswj txog li 32 tus qhev ywj pheej SPI. SCLK baud tus nqi tau teeb tsa rau 20 MHz (saib los ntawm 5).
Qhov no module yog configured rau 4-xaim, 24-ntsis dav interface. Yog tias xaiv Tsim 3-Wire SPI Module xaiv, ib qho ntxiv module yog instantiated los hloov 4-xaim tso zis ntawm SPI tswv rau 3-xaim.

IOPLL
Lub IOPLL tsim lub moos xav tau los tsim frame_clk thiab link_clk. Lub moos siv rau PLL yog configurable tab sis txwv rau cov ntaub ntawv tus nqi / qhov tseem ceeb ntawm 33.

• Rau tsim example uas txhawb cov ntaub ntawv tus nqi ntawm 24.33024 Gbps, lub moos tus nqi rau frame_clk thiab link_clk yog 368.64 MHz.
• Rau tsim example uas txhawb cov ntaub ntawv tus nqi ntawm 32 Gbps, lub moos tus nqi rau frame_clk thiab link_clk yog 484.848 MHz.

SYSREF Generator
SYSREF yog lub sijhawm tseem ceeb rau cov ntaub ntawv hloov pauv nrog F-Tile JESD204C interface.

SYSREF generator hauv tus tsim example yog siv rau duplex JESD204C IP txuas pib ua qauv qhia lub hom phiaj nkaus xwb. Hauv JESD204C subclass 1 system daim ntawv thov, koj yuav tsum tsim SYSREF los ntawm tib qhov chaw raws li lub moos.

Rau F-Tile JESD204C IP, SYSREF multiplier (SYSREF_MULP) ntawm SYSREF tswj sau npe txhais lub sijhawm SYSREF, uas yog n-tus lej ntau ntawm E parameter.

Koj yuav tsum xyuas kom meej E*SYSREF_MULP ≤16. Rau example, yog E=1, qhov kev cai lij choj rau SYSREF_MULP yuav tsum tsis pub dhau 1–16, thiab yog E=3, qhov kev cai lij choj rau SYSREF_MULP yuav tsum nyob rau hauv 1–5.

Nco tseg:  Yog tias koj teeb tsa qhov tsis sib xws SYSREF_MULP, SYSREF lub tshuab hluav taws xob yuav kho qhov chaw rau SYSREF_MULP=1.
Koj tuaj yeem xaiv seb koj xav tau hom SYSREF los ua ib qho kev txhaj tshuaj mem tes, ntu ntu, lossis gapped lub sijhawm dhau los ntawm Example Tsim tab hauv F-Tile JESD204C Intel FPGA IP parameter editor.

Table 9. Examples of Periodic and Gapped Periodic SYSREF Counter

E	SYSREF_MULP	SYSREF PERIOD (E*SYSREF_MULP* 32)	Lub luag hauj lwm Cycle	Kev piav qhia
1	1	32	1..31 ib (Programmable)	Gapped Periodic
1	1	32	16 (Txuas)	Lub caij nyoog
1	2	64	1..63 ib (Programmable)	Gapped Periodic
1	2	64	32 (Txuas)	Lub caij nyoog
1	16	512	1..511 ib (Programmable)	Gapped Periodic
1	16	512	256 (Txuas)	Lub caij nyoog
2	3	19	1..191 ib (Programmable)	Gapped Periodic
2	3	192	96 (Txuas)	Lub caij nyoog
2	8	512	1..511 ib (Programmable)	Gapped Periodic
2	8	512	256 (Txuas)	Lub caij nyoog
2	9 (Tsis raug cai)	64	32 (Txuas)	Gapped Periodic
2	9 (Tsis raug cai)	64	32 (Txuas)	Lub caij nyoog

 

Table 10. SYSREF Control Registers
Koj tuaj yeem hloov kho qhov kev teeb tsa SYSREF tswj kev sau npe yog tias qhov chaw sau npe txawv dua li qhov chaw koj tau teev tseg thaum koj tsim cov qauv tsim.ample. Configure SYSREF cov npe ua ntej F-Tile JESD204C Intel FPGA IP tsis rov pib dua. Yog tias koj xaiv lub tshuab hluav taws xob sab nraud SYSREF los ntawm
sysref_ctrl[7] sau npe me ntsis, koj tuaj yeem tsis quav ntsej cov chaw rau SYSREF hom, tus lej sib npaug, lub voj voog lub luag haujlwm thiab theem.

Cov khoom	Default tus nqi	Kev piav qhia
sysref_ctrl[1:0] ib	2b00: ib 2b01 :ua 2'b10: Gapped periodic	SYSREF hom. Lub neej ntawd tus nqi nyob ntawm SYSREF hom teeb tsa hauv Examptsim tab hauv F-Tile JESD204C Intel FPGA IP parameter editor.
sysref_ctrl[6:2] ib	5b00001 XNUMX	SYSREF multiplier. SYSREF_MULP daim teb no muaj feem xyuam rau lub sijhawm thiab gapped-periodic SYSREF hom. Koj yuav tsum teeb tsa tus nqi sib npaug kom ntseeg tau tias E*SYSREF_MULP tus nqi nyob nruab nrab ntawm 1 txog 16 ua ntej F-Tile JESD204C IP tsis rov pib dua. Yog tias tus E*SYSREF_MULP tus nqi tawm ntawm qhov ntau, tus nqi sib npaug ua rau 5'b00001.
sysref_ctrl[7]	Duplex datapath: 1'b1 Simplex TX or RX datapath: 1'b0	SYSREF xaiv. Tus nqi pib nyob ntawm cov ntaub ntawv txoj kev teeb tsa hauv Example Tsim tab hauv F-Tile JESD204C Intel FPGA IP parameter editor. 0: Simplex TX or RX (External SYSREF) 1: Duplex (Internal SYSREF)
sysref_ctrl[16:8] ib	9h0 ua	SYSREF lub luag haujlwm lub voj voog thaum SYSREF hom yog ncua sij hawm lossis gapped lub sijhawm. Koj yuav tsum teeb tsa lub voj voog ua haujlwm ua ntej F-Tile JESD204C IP tsis rov pib dua. Tus nqi siab tshaj = (E*SYSREF_MULP*32)-1 For example: 50% lub luag haujlwm voj voog = (E*SYSREF_MULP*32)/2 Lub luag haujlwm lub voj voog ua haujlwm tsis raug rau 50% yog tias koj tsis teeb tsa daim ntawv teev npe no, lossis yog tias koj teeb tsa cov ntawv sau npe rau 0 lossis ntau dua li qhov siab tshaj plaws tau tso cai.
sysref_ctrl[17]	1b0 XNUMX	Kev tuav tswj thaum SYSREF hom yog txhaj ib zaug. Sau 1 los teeb SYSREF teeb liab kom siab. Sau 0 los teeb tsa SYSREF teeb liab kom qis. Koj yuav tsum sau tus 1 ces a 0 los tsim SYSREF mem tes hauv ib hom txhaj tshuaj.
sysref_ctrl[31:18] ib	22h0 ua	Khaws tseg.

Pib dua Sequencers
Qhov no tsim example muaj ob lub reset sequencers:

• Pib dua Sequence 0-Tau qhov pib dua rau TX/RX Avalon streaming domain, Avalon nco-mapped domain, core PLL, TX PHY, TX core, thiab SYSREF generator.
• Rov pib dua ib ntus 1-Tau qhov rov pib dua rau RX PHY thiab RX Core.

3-Wire SPI
Cov qauv no yog xaiv tau los hloov SPI interface rau 3-hlau.

System PLL
F-tile muaj peb lub hauv paus system PLLs. Cov kab ke PLLs no yog lub moos tseem ceeb rau kev nyuaj IP (MAC, PCS, thiab FEC) thiab EMIB hla. Qhov no txhais tau hais tias, thaum koj siv lub kaw lus PLL clocking hom, cov blocks tsis clocked los ntawm PMA moos thiab tsis nyob ntawm lub moos los ntawm FPGA core. Txhua qhov system PLL tsuas yog tsim lub moos cuam tshuam nrog ib qho kev sib txuas zaus. Rau example, koj xav tau ob qhov system PLLs khiav ib qho interface ntawm 1 GHz thiab ib qho interface ntawm 500 MHz. Siv lub kaw lus PLL tso cai rau koj siv txhua txoj kab ntawm nws tus kheej yam tsis muaj txoj kab kev hloov pauv cuam tshuam rau txoj kab nyob sib ze.
Txhua lub kaw lus PLL tuaj yeem siv ib qho ntawm yim FGT siv moos. System PLLs tuaj yeem qhia cov moos siv lossis muaj cov moos siv sib txawv. Txhua qhov kev sib txuas tuaj yeem xaiv qhov system PLL nws siv, tab sis, ib zaug xaiv, nws raug kho, tsis tuaj yeem siv rov ua dua tshiab.

Cov ntaub ntawv ntsig txog
F-tile Architecture thiab PMA thiab FEC Direct PHY IP Tus Neeg Siv Qhia

Xav paub ntau ntxiv txog lub system PLL clocking hom hauv Intel Agilex F-tile li.

Qauv Generator thiab Checker
Tus qauv generator thiab checker muaj txiaj ntsig los tsim cov ntaub ntawv samples thiab saib xyuas rau lub hom phiaj kev xeem.
Rooj 11. Txhawb Cov Qauv Tsim Qauv

Qauv Generator	Kev piav qhia
PRBS qauv generator	F-Tile JESD204C tsim example PRBS qauv generator txhawb cov qib hauv qab no ntawm polynomials: PRBS23: X23+X18+1 PRBS15: X15+X14+1 PRBS9: X9+X5+1 PRBS7: X7+X6+1
Ramp qauv generator	Cov ramp qauv tus nqi nce ntxiv los ntawm 1 rau txhua qhov tom ntej sample nrog lub tshuab hluav taws xob dav ntawm N, thiab dov mus rau 0 thaum tag nrho cov khoom hauv sampua le1. Qhib lub ramp qauv generator los ntawm kev sau ib 1 mus rau ntsis 2 ntawm tst_ctl sau npe ntawm ED tswj thaiv.
Command channel ramp qauv generator	F-Tile JESD204C tsim example txhawb command channel ramp qauv generator ib txoj kab. Cov ramp qauv tus nqi nce los ntawm 1 rau 6 khoom ntawm cov lus txib. Cov noob pib yog ib qho kev nce ntxiv hauv txhua txoj kab.

Table 12. Txhawb Tus Qauv Ntsuas

Qauv Checker	Kev piav qhia
PRBS qauv checker	Cov noob scrambling nyob rau hauv tus qauv checker yog nws tus kheej synchronized thaum F-Tile JESD204C IP ua tiav deskew alignment. Tus qauv checker xav tau 8 octets rau cov noob scrambling rau nws tus kheej synchronize.
Ramp tus qauv checker	Thawj cov ntaub ntawv siv tau sample rau txhua lub converter (M) yog loaded raws li tus nqi pib ntawm ramp qauv. Cov ntaub ntawv tom qab samples qhov tseem ceeb yuav tsum nce los ntawm 1 hauv txhua lub voj voog mus txog qhov siab tshaj plaws thiab tom qab ntawd dov mus rau 0.

Qauv Checker	Kev piav qhia
	Rau example, thaum S = 1, N = 16 thiab WIDTH_MULP = 2, cov ntaub ntawv dav ib converter yog S * WIDTH_MULP * N = 32. Qhov siab tshaj plaws cov ntaub ntawv sample tus nqi yog 0xFFFF. Cov ramp pattern checker xyuas tias cov qauv zoo tib yam tau txais thoob plaws txhua lub converters.
Command channel ramp tus qauv checker	F-Tile JESD204C tsim example txhawb command channel ramp tus qauv checker. Thawj lo lus txib (6 ntsis) tau txais yog loaded raws li tus nqi pib. Cov lus txib tom ntej hauv tib txoj kab yuav tsum nce mus txog 0x3F thiab dov mus rau 0x00. Cov lus txib channel ramp qauv checker checks rau ramp cov qauv thoob plaws txhua txoj kab.

F-Tile JESD204C TX and RX IP
Qhov no tsim example tso cai rau koj los teeb tsa txhua TX / RX hauv hom simplex lossis duplex hom.
Duplex configurations tso cai rau tus IP ua haujlwm ua qauv qhia siv sab hauv lossis sab nraud serial loopback. CSRs hauv IP tsis tau kho kom zoo tam sim ntawd tso cai rau kev tswj hwm tus IP thiab saib xyuas xwm txheej.

F-Tile JESD204C Tsim Example Clock and Reset

F-Tile JESD204C tsim example muaj ib txheej teev thiab pib dua cov cim.

Table 13.Tsim Example Clocks

Mloog Teeb Meem	Kev taw qhia	Kev piav qhia
mgmt_clk	Tswv yim	LVDS sib txawv moos nrog zaus ntawm 100 MHz.
refclk_xcvr	Tswv yim	Transceiver siv moos nrog zaus ntawm cov ntaub ntawv tus nqi / qhov tseem ceeb ntawm 33.
refclk_core	Tswv yim	Core siv moos nrog tib zaus li refclk_xcvr.
hauv_sysref	Tswv yim	SYSREF signal. Qhov siab tshaj plaws SYSREF zaus yog cov ntaub ntawv tus nqi / (66x32xE).
sysref_out	Tso zis
txlink_clk rxlink_clk	Sab hauv	TX thiab RX txuas moos nrog zaus ntawm cov ntaub ntawv tus nqi / 66.
txframe_clk rxframe_clk	Sab hauv	TX thiab RX ncej moos nrog zaus ntawm cov ntaub ntawv tus nqi / 33 (FCLK_MULP=2) TX thiab RX ncej moos nrog zaus ntawm cov ntaub ntawv tus nqi / 66 (FCLK_MULP=1)
tx_fclk rx_fclk	Sab hauv	TX thiab RX theem moos nrog zaus ntawm cov ntaub ntawv tus nqi / 66 (FCLK_MULP=2) TX thiab RX theem moos yog ib txwm siab (1'b1) thaum FCLK_MULP=1
spi_SCLK	Tso zis	SPI baud tus nqi moos nrog zaus ntawm 20 MHz.

Thaum koj thauj tus tsim example rau hauv FPGA ntaus ntawv, ib qho kev tshwm sim sab hauv ninit_done ua kom ntseeg tau tias JTAG mus rau Avalon Master choj yog nyob rau hauv pib dua nrog rau tag nrho lwm cov blocks.

Lub tshuab hluav taws xob SYSREF muaj nws txoj kev ywj pheej rov pib dua los txhaj rau kev sib raug zoo asynchronous rau txlink_clk thiab rxlink_clk moos. Txoj kev no muaj ntau dua nyob rau hauv emulating SYSREF teeb liab los ntawm lwm lub moos nti.

Table 14. Tsim Example Resets

Pib dua teeb liab	Kev taw qhia	Kev piav qhia
global_rst_n	Tswv yim	Push khawm thoob ntiaj teb rov pib dua rau txhua qhov thaiv, tshwj tsis yog JTAG mus rau Avalon Master choj.
ninit_ua	Sab hauv	Tso zis los ntawm Reset Release IP rau JTAG mus rau Avalon Master choj.
edctl_rst_n ua	Sab hauv	ED Control thaiv yog rov pib dua los ntawm JTAG mus rau Avalon Master choj. Lub hw_rst thiab global_rst_n chaw nres nkoj tsis rov pib dua ED Control thaiv.
hw_rst	Sab hauv	Assert thiab deassert hw_rst los ntawm kev sau ntawv mus rau rst_ctl sau npe ntawm ED Control block. mgmt_rst_in_n asserts thaum hw_rst asserted.
mgmt_rst_in_n	Sab hauv	Pib dua rau Avalon nco-mapped interfaces ntawm ntau yam IPs thiab inputs ntawm reset sequencers:  j20c_reconfig_reset rau F-Tile JESD204C IP duplex Native PHY spi_rst_n rau SPI tus tswv pio_rst_n rau PIO xwm txheej thiab tswj reset_in0 chaw nres nkoj ntawm reset sequencer 0 thiab 1 Lub global_rst_n, hw_rst, lossis edctl_rst_n chaw nres nkoj lees tias rov pib dua ntawm mgmt_rst_in_n.
sysref_rst_n	Sab hauv	Rov pib dua rau SYSREF lub tshuab hluav taws xob thaiv hauv ED Control thaiv siv qhov rov pib dua sequencer 0 reset_out2 chaw nres nkoj. Qhov rov pib dua sequencer 0 reset_out2 chaw nres nkoj deasserts qhov rov pib dua yog tias cov tub ntxhais PLL raug kaw.
core_pll_rst	Sab hauv	Resets cov tub ntxhais PLL los ntawm qhov pib dua sequencer 0 reset_out0 chaw nres nkoj. Cov tub ntxhais PLL rov pib dua thaum mgmt_rst_in_n rov pib dua tau lees paub.
j204c_tx_avs_rst_n	Sab hauv	Resets F-Tile JESD204C TX Avalon nco- mapped interface los ntawm kev pib dua sequencer 0. TX Avalon nco-mapped interface lees paub thaum mgmt_rst_in_n tau lees paub.
j204c_rx_avs_rst_n	Sab hauv	Resets F-Tile JESD204C TX Avalon nco- mapped interface los ntawm kev rov pib dua sequencer 1. RX Avalon nco-mapped interface lees paub thaum mgmt_rst_in_n tau lees paub.
j204c_tx_rst_n	Sab hauv	Resets F-Tile JESD204C TX txuas thiab thauj cov khaubncaws sab nraud povtseg hauv txlink_clk, thiab txframe_clk, domains. The reset sequencer 0 reset_out5 port reset j204c_tx_rst_n. Qhov no rov pib dua deasserts yog tias cov tub ntxhais PLL raug kaw, thiab cov cim tx_pma_ready thiab tx_ready tau lees paub.
j204c_rx_rst_n	Sab hauv	Rov pib dua F-Tile JESD204C RX txuas thiab thauj txheej hauv, rxlink_clk, thiab rxframe_clk domains.

Pib dua teeb liab	Kev taw qhia	Kev piav qhia
		Lub reset sequencer 1 reset_out4 chaw nres nkoj pib dua j204c_rx_rst_n. Qhov no rov pib dua deasserts yog tias cov tub ntxhais PLL raug kaw, thiab rx_pma_ready thiab rx_ready signals tau lees paub.
j204c_tx_rst_ack_n	Sab hauv	Pib dua handshakes teeb liab nrog j204c_tx_rst_n.
j204c_rx_rst_ack_n	Sab hauv	Pib dua handshakes teeb liab nrog j204c_rx_rst_n.

Daim duab 8. Timing Diagram rau Design Example Resets

F-Tile JESD204C Tsim Example Signals

Table 15. System Interface Signals

Teeb liab	Kev taw qhia	Kev piav qhia
Clocks thiab Resets
mgmt_clk	Tswv yim	100 MHz moos rau kev tswj hwm qhov system.
refclk_xcvr	Tswv yim	Kev siv moos rau F-tile UX QUAD thiab System PLL. Sib npaug rau cov ntaub ntawv tus nqi / qhov tseem ceeb ntawm 33.
refclk_core	Tswv yim	Core PLL siv moos. Siv tib lub moos zaus li refclk_xcvr.
hauv_sysref	Tswv yim	SYSREF teeb liab los ntawm lwm lub tshuab hluav taws xob SYSREF rau JESD204C Subclass 1 kev siv.
sysref_out	Tso zis	SYSREF teeb liab rau JESD204C Subclass 1 kev siv tsim los ntawm FPGA ntaus ntawv rau tsim example link initialization purpose only.

 

Teeb liab	Kev taw qhia	Kev piav qhia
SPI
spi_SS_n[2:0] os	Tso zis	Active qis, SPI qhev xaiv teeb liab.
spi_SCLK	Tso zis	SPI serial moos.
spi_sdio	Input/Output	Tso cov ntaub ntawv los ntawm tus tswv mus rau lwm tus qhev. Muab cov ntaub ntawv los ntawm tus qhev sab nraud rau tus tswv.

Teeb liab	Kev taw qhia	Kev piav qhia
Nco tseg:Thaum Tsim 3-Wire SPI Module xaiv tau qhib.
spi_MISO Nco tseg: Thaum Tsim 3-Wire SPI Module kev xaiv tsis qhib.	Tswv yim	Muab cov ntaub ntawv los ntawm tus qhev sab nraud mus rau tus tswv SPI.
spi_MOSI Nco tseg: Thaum Tsim 3-Wire SPI Module kev xaiv tsis qhib.	Tso zis	Tso tawm cov ntaub ntawv los ntawm SPI tus tswv rau tus qhev sab nraud.

 

Teeb liab	Kev taw qhia	Kev piav qhia
ADC / DAC
tx_serial_data[LINK*L-1:0]	Tso zis	Sib txawv kev kub ceev serial tso zis cov ntaub ntawv rau DAC. Lub moos yog embedded nyob rau hauv serial cov ntaub ntawv kwj.
tx_serial_data_n[LINK*L-1:0]
rx_serial_data[LINK*L-1:0]	Tswv yim	Sib txawv kev kub ceev serial input cov ntaub ntawv los ntawm ADC. Lub moos tau zoo los ntawm cov ntaub ntawv serial kwj.
rx_serial_data_n[LINK*L-1:0]

 

Teeb liab	Kev taw qhia	Kev piav qhia
Lub Hom Phiaj General I/O
user_led[3:0]	Tso zis	Qhia qhov xwm txheej rau cov xwm txheej hauv qab no: [0]: SPI programming ua tiav [1]: TX link error [2]: RX txuas yuam kev [3]: Txawv checker yuam kev rau Avalon streaming cov ntaub ntawv
user_dip[3:0]	Tswv yim	Tus neeg siv hom DIP hloov tswv yim: [0]: Internal serial loopback pab [1]: FPGA-tsim SYSREF pab [3:2]: Reserved

 

Teeb liab	Kev taw qhia	Kev piav qhia
Out-of-band (OOB) and Status
rx_patchk_data_error[LINK-1:0]	Tso zis	Thaum qhov teeb meem no tau lees paub, nws qhia tias tus qauv kuaj tau kuaj pom qhov yuam kev.
rx_link_error[LINK-1:0]	Tso zis	Thaum qhov teeb meem no tau lees paub, nws qhia tias JESD204C RX IP tau lees paub cuam tshuam.
tx_link_error[LINK-1:0]	Tso zis	Thaum qhov teeb meem no tau lees paub, nws qhia tias JESD204C TX IP tau lees paub cuam tshuam.
emb_lock_out	Tso zis	Thaum qhov teeb meem no tau lees paub, nws qhia tias JESD204C RX IP tau ua tiav EMB xauv.
sh_lock_out	Tso zis	Thaum qhov teeb meem no tau lees paub, nws qhia tias JESD204C RX IP sync header raug kaw.

 

Teeb liab	Kev taw qhia	Kev piav qhia
Avalon Streaming
rx_avst_valid[LINK-1:0]	Tswv yim	Qhia seb tus converter sample cov ntaub ntawv rau daim ntawv thov txheej yog siv tau los yog invalid. 0: Cov ntaub ntawv tsis raug 1: Cov ntaub ntawv siv tau
rx_avst_data[(TOTAL_SAMPLE*N)-1:0 ]	Tswv yim	Hloov sample cov ntaub ntawv mus rau txheej txheej.

F-Tile JESD204C Tsim Example Control Registers

F-Tile JESD204C tsim example sau npe hauv ED Control block siv byte-addressing (32 ntsis).

Table 16. Tsim Example Address Map
Cov 32-ntsis ED Control block sau npe nyob hauv mgmt_clk sau.

Cheebtsam	Chaw nyob
F-Tile JESD204C TX IP	0x000C_0000 – 0x000C_03FF
F-Tile JESD204C RX IP	0x000D_0000 – 0x000D_03FF
SPI Tswj	0x0102_0000 – 0x0102_001F
PIO Tswj	0x0102_0020 – 0x0102_002F
PIO Status	0x0102_0040 – 0x0102_004F
Pib dua Sequencer 0	0x0102_0100 – 0x0102_01FF
Pib dua Sequencer 1	0x0102_0200 – 0x0102_02FF
ED Tswj	0x0102_0400 – 0x0102_04FF
F-Tile JESD204C IP transceiver PHY Reconfig	0x0200_0000 – 0x023F_FFFF

Table 17. Sau npe nkag hom thiab txhais
Cov lus no piav qhia txog hom kev nkag nkag rau Intel FPGA IPs.

Hom kev nkag	Txhais
RO/V	Software nyeem nkaus xwb (tsis cuam tshuam rau kev sau). Tus nqi yuav txawv.
RW	Software nyeem thiab xa cov nqi me ntsis tam sim no. Software sau thiab teeb me ntsis rau tus nqi xav tau.
RWB 1C	Software nyeem thiab xa cov nqi me ntsis tam sim no. Software sau 0 thiab tsis muaj txiaj ntsig. Software sau 1 thiab tshem qhov me ntsis rau 0 yog tias lub ntsis tau teeb tsa rau 1 los ntawm kho vajtse. Hardware teeb lub ntsis rau 1. Software ntshiab muaj qhov tseem ceeb dua li kho vajtse teeb.

Table 18. ED Control Chaw nyob daim ntawv qhia

Offset	Sau npe
0 x 00	rst_ctl ua
0 x 04	rst_sts 0
txuas ntxiv…

Offset	Sau npe
0 x 10	rst_sts_detected0
0 x 40	sysref_ctl ua
0 x 44	sysref_sts
0 x 80	tsw_ctl
0x8c wb	txs_err 0

Table 19. ED Control Block Control thiab Status Registers

Byte Offset	Sau npe	Lub npe	Nkag mus	Rov pib dua	Kev piav qhia
0 x 00	rst_ctl ua	rst_ lus	RW	0 x 0	Rov pib tswj. [0]: Sau 1 kom rov pib dua. (hw_rst) Sau 0 dua rau deassert pib dua. [31:1]: Tswb.
0 x 04	rst_sts 0	rst_ xwm	RO/V	0 x 0	Rov pib dua xwm txheej. [0]: Core PLL xauv xwm txheej. [31:1]: Tswb.
0 x 10	rst_sts_dete cted0	rst_sts_set	RWB 1C	0 x 0	SYSREF ntug kev tshawb nrhiav qhov xwm txheej rau sab hauv lossis sab nraud SYSREF lub tshuab hluav taws xob. [0]: Tus nqi ntawm 1 Qhia txog SYSREF nce ntug yog kuaj pom rau kev ua haujlwm subclass 1. Software tej zaum yuav sau 1 kom tshem tawm qhov me ntsis kom pab tau SYSREF ntug nrhiav pom tshiab. [31:1]: Tswb.
0 x 40	sysref_ctl ua	sysref_contr ol	RW	Duplex datapath ib :0x00080	SYSREF tswj. Xa mus rau Table 10 nyob rau nplooj 17 kom paub ntau ntxiv txog kev siv cov npe no.
				Sijhawm:	Nco tseg: Tus nqi pib dua nyob ntawm
				0 x 00081	hom SYSREF thiab F-Tile
				Gapped- periodic:	JESD204C IP data path parameter nqis.
				0 x 00082
				TX or RX data
				txoj kev
				Ib-shot:
				0 x 00000
				Sijhawm:
				0 x 00001
				Gapped-
				raws sij hawm:
				0 x 00002
0 x 44	sysref_sts	sysref_statu s	RO/V	0 x 0	SYSREF status. Cov ntawv sau npe no muaj lub sijhawm kawg ntawm SYSREF thiab lub luag haujlwm lub voj voog teeb tsa ntawm lub tshuab hluav taws xob sab hauv SYSREF. Xa mus rau Table 9 nyob rau nplooj 16 rau tus nqi raug cai ntawm SYSREF lub sijhawm thiab lub voj voog ua haujlwm.
txuas ntxiv…

Byte Offset	Sau npe	Lub npe	Nkag mus	Rov pib dua	Kev piav qhia
					[8:0]: SYSREF lub sij hawm. Thaum tus nqi yog 0xFF, qhov SYSREF lub sij hawm = 255 Thaum tus nqi yog 0x00, lub sij hawm SYSREF = 256. [17:9]: SYSREF lub luag haujlwm voj voog. [31:18] : Saib.
0 x 80	tsw_ctl	tst_control	RW	0 x 0	Kev tswj xyuas. Siv daim ntawv teev npe no txhawm rau ua kom muaj cov qauv sib txawv rau cov qauv tsim hluav taws xob thiab cov checker. [1:0] = Reserved field [2] = ramp_test_ctl ua 1'b0 = Enables PRBS pattern generator and checker 1'b1 = Enables ramp qauv generator thiab checker [31:3] : Tswb.
0x8c wb	txs_err 0	tzs_error	RWB 1C	0 x 0	Kev ua yuam kev chij rau Link 0. Thaum lub ntsis yog 1'b1, nws qhia tau hais tias qhov yuam kev tau tshwm sim. Koj yuav tsum daws qhov yuam kev ua ntej sau 1'b1 mus rau qhov sib txawv me ntsis kom tshem tawm qhov yuam kev. [0] = Pattern checker error [1] = tx_link_error [2] = rx_link_error [3] = Command pattern checker error [31:4]: Reserved.

Cov ntaub ntawv kho dua tshiab rau F-Tile JESD204C Intel FPGA IP Tsim Example User Guide

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2021.10.11	21.3	1.0.0	Kev tso tawm thawj zaug.

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