DisplayPort Agilex F-Tile FPGA IP Design Example
Fa'aoga Taiala
Fa'afou mo le Intel® Quartus® Prime Design Suite: 21.4
IP Version: 21.0.0
DisplayPort Intel FPGA IP Design Example Taiala Amata vave
Le DisplayPort Intel® FPGA IP design examples mo Intel Agilex™ F-tile masini o loʻo faʻaalia ai se suʻega faʻataʻitaʻiga ma se mamanu meafaigaluega e lagolagoina le tuʻufaʻatasia ma suʻega meafaigaluega.
O le DisplayPort Intel FPGA IP o loʻo ofoina atu le faʻataʻitaʻiga leaamples:
- Fa'aaligaPort SST fa'ata'ita'i fa'atasi e aunoa ma le Pixel Clock Recovery (PCR) module i le fua fa'atatau
A e fatuina se mamanu example, e otometi lava ona fatuina e le faatonu parameter le files e manaʻomia e faʻataʻitaʻi, faʻapipiʻi, ma suʻe le mamanu i meafaigaluega.
Fa'aaliga: Intel Quartus® Prime 21.4 software version na'o le lagolagoina o le Preliminary Design Example mo le Fa'ata'ita'iga, Fa'asologa, Tu'ufa'atasi, ma fa'amoemoega o su'esu'ega Taimi. E le'o fa'amaonia atoatoa le fa'aogaina o meafaigaluega.
Ata 1. Atina'e Stages
Fa'amatalaga Fa'atatau
- DisplayPort Intel FPGA IP Taiala Tagata Fa'aoga
- Fa'asolo ile Intel Quartus Prime Pro Edition
1.1. Fa'atonuga Fa'atonu
Ata 2. Fa'atonuga Fa'atonu
Laulau 1. Fuafuaga Example Vaega
| Folders | Files |
| rtl/core | dp_core.ip |
| dp_rx.ip | |
| dp_tx.ip | |
| rtl/rx_phy | dp_gxb_rx/ ((DP PMA UX poloka faufale) |
| dp_rx_data_fifo.ip | |
| rx_top_phy.sv | |
| rtl/tx_phy | dp_gxb_rx/ ((DP PMA UX poloka faufale) |
| dp_tx_data_fifo.ip | |
| dp_tx_data_fifo.ip |
1.2. Meafaigaluega ma Polokalama Manaoga
E fa'aogaina e Intel meafaigaluega ma polokalama fa'akomepiuta nei e su'e ai le mamanu exampLe:
Meafaigaluega
- Intel Agilex I-Series Development Kit
Polokalama
- Intel Quartus Palemia
- Synopsys* VCL Simulator
1.3. Fausiaina o le Fuafuaga
Fa'aaoga le DisplayPort Intel FPGA IP fa'atonu fa'atonu i le Intel Quartus Prime software e fa'atupu ai le fa'ata'ita'igaample.
Ata 3. Fa'atupuina o le Fa'asologa o Fuafuaga
- Filifili Meafaigaluega ➤ IP Catalog, ma filifili le Intel Agilex F-tile e avea ma aiga masini faʻamoemoe.
Manatua: O le mamanu exampLe na'o le lagolagoina o masini Intel Agilex F-tile. - I le IP Catalog, su'e ma kiliki fa'alua DisplayPort Intel FPGA IP. Ua aliali mai le fa'amalama New IP Variation.
- Fa'ailoa se igoa pito i luga mo lau suiga masani IP. E fa'asaoina e le fa'atonu fa'amaufa'ailoga le fa'atulagaina o suiga o le IP ile a file igoa .ip.
- E mafai ona e filifilia se masini fa'apitoa Intel Agilex F-tile i totonu o le masini masini, po'o le fa'atumauina le fa'aletonu ole Intel Quartus Prime le filifilia o masini komepiuta.
- Kiliki OK. E aliali mai le fa'atonu fa'amaufa'ailoga.
- Fa'atulaga mea e mana'omia mo TX ma RX
- I luga ole Design Exampi le tab, filifili DisplayPort SST Parallel Loopback e aunoa ma le PCR.
- Filifili Fa'ata'ita'iga e fa'atupu ai le su'ega, ma filifili Fa'atasi e fa'atupuina ai le fa'asologa o meafaigaluegaample. E tatau ona e filifilia se tasi o nei filifiliga e fa'atupu ai le fa'ata'ita'igaample files. Afai e te filifilia uma e lua, o le taimi o le gaosiga e umi atu.
- Kiliki Fausia Example Design.
1.4. Fa'ata'ita'iina o le Fuafuaga
Le DisplayPort Intel FPGA IP design example testbench fa'ata'ita'iina se fa'asologa o le loopback mamanu mai se fa'ata'ita'iga TX i se fa'ata'ita'iga RX. O se masini fa'atupu ata vitio i totonu e fa'aosoina le DisplayPort TX fa'ata'ita'iga ma le RX fa'ata'ita'iga ata vitio e feso'ota'i i siaki CRC i le su'ega.
Ata 4. Fa'asologa Fa'ata'ita'iga Fa'asologa
- Alu ile Synopsys simulator folder ma filifili VCS.
- Fa'ata'ita'i fa'asologa.
Punavai vcs_sim.sh - O le tusitusiga e faʻatino ai le Quartus TLG, faʻapipiʻi ma faʻatautaia le suʻega suʻega i le simulator.
- Iloilo le taunuuga.
O se faʻataʻitaʻiga manuia e faʻamaeʻa i le Source ma Sink SRC faʻatusatusaga.
1.5. Tu'ufa'atasia ma Fa'ata'ita'iina o le Fuafuaga
Ata 5. Tu'ufa'atasia ma Fa'ata'ita'i le Fa'ata'ita'iga
E fa'aputu ma fa'atino se su'ega fa'ata'ita'iga ile meafaigaluega fa'aample mamanu, mulimuli i laasaga nei:
- Ia mautinoa meafaigaluega exampua mae'a le fausiaina o mamanu.
- Tatala le polokalama Intel Quartus Prime Pro Edition ma tatala /quartus/agi_dp_demo.qpf.
- Kiliki Processing ➤ Amata Fa'aopoopo.
- Fa'atali se'ia mae'a le Fa'aopoopo.
Fa'aaliga: Le mamanu exampe le fa'amaonia fa'atino Fuafuaga Muamua Exampi luga o meafaigaluega i lenei faʻasalalauga Quartus.
Fa'amatalaga Fa'atatau
Intel Agilex I-Series FPGA Development Kit Guide Guide
1.6. DisplayPort Intel FPGA IP Design Example Parameter
Laulau 2. DisplayPort Intel FPGA IP Design Example Parameter mo le Intel Agilex F-tile Device
| Parameter | Taua | Fa'amatalaga |
| Avanoa Design Example | ||
| Filifili Design | • Leai • DisplayPort SST Fa'atasi Loopback e aunoa ma se PCR |
Filifili le mamanu example e gaosia. • Leai: Leai se mamanu example avanoa mo le filifiliga parakalafa o lo'o iai nei • DisplayPort SST Parallel Loopback e aunoa ma le PCR: O le mamanu leneiampe fa'aalia le fa'asolo tutusa mai le fa'agogo o le DisplayPort i le puna DisplayPort e aunoa ma se Pixel Clock Recovery (PCR) module pe a e kiina le fa'aagaoioiga Enable Video Input Image Port. |
| Design Example Files | ||
| Fa'ata'oto | Ua pe, ua pe | Fa'aola lenei filifiliga e fa'atupu ai mea e mana'omia files mo le su'ega fa'ata'ita'iga. |
| Fa'asologa | Ua pe, ua pe | Fa'aola lenei filifiliga e fa'atupu ai mea e mana'omia files mo Intel Quartus Prime tu'ufa'atasiga ma mamanu meafaigaluega. |
| Fausia le HDL Format | ||
| Fa'atupu File Fa'asologa | Verilog, VHDL | Filifili lau fa'atulagaga HDL e te mana'o iai mo le fa'ata'ita'iga fa'atupuample fileseti. Fa'aaliga: O lenei filifiliga e na'o le fa'atulagaina mo le fa'atupuina o le tulaga maualuga IP files. O isi uma files (egample testbenches ma le tulaga maualuga files mo meafaigaluega faʻataʻitaʻiga) o loʻo i le Verilog HDL format. |
| Pusa Atina'e Sini | ||
| Filifili le Komiti Faatino | • Leai se Pusa Atina'e • Intel Agilex I-Series Pusa Atina'e |
Filifili le laupapa mo le mamanu fa'atatauample. • Leai se Pusa Atina'e: O lenei filifiliga e le aofia ai vaega uma o meafaigaluega mo le mamanu muamuaample. O le IP autu e setiina uma tofitofiga pine i pine mama. • Intel Agilex I-Series FPGA Development Kit: O lenei filifiliga e otometi lava ona filifilia le masini fa'atatau o le poloketi e fetaui ma le masini i luga o lenei pusa atina'e. E mafai ona e suia le masini fa'atatau i le fa'aogaina o le Suiga o le Fa'atonu Fa'atonu pe a fai e iai se suiga ole masini e iai lau su'ega laupapa. O le IP autu e setiina uma tofitofiga pine e tusa ai ma le pusa atinaʻe. Fa'aaliga: Fuafuaga Muamua Exampe le'o fa'amaonia fa'atino i meafaigaluega i lenei fa'asalalauga Quartus. • Pusa Atina'e Fa'aleaganu'u: O lenei filifiliga e fa'atagaina ai le mamanu fa'aampe fa'ata'ita'iina i se pusa atina'e lona tolu ma se Intel FPGA. Atonu e te mana'omia le setiina e oe lava o tofiga o pine. |
| Meafaigaluega Sini | ||
| Suia Mea Fa'atatau | Ua pe, ua pe | Fa'aola le filifiliga lea ma filifili le mea e sili ona fiafia i ai masini mo le atina'e pusa. |
Fa'atusa Loopback Fa'atasiamples
Le DisplayPort Intel FPGA IP design exampO lo'o fa'aalia le fa'ata'amilosaga tutusa mai le fa'ata'ita'iga DisplayPort RX i le fa'ata'ita'iga DisplayPort TX e aunoa ma le fa'aola ole Pixel Clock Recovery (PCR) i le fua fa'atatau.
Laulau 3. DisplayPort Intel FPGA IP Design Example mo le Intel Agilex F-tile Device
| Design Example | Tofiga | Fua Fa'amatalaga | Faiga Ala | Ituaiga Loopback |
| DisplayPort SST fa'asolo fa'atasi e aunoa ma le PCR | DisplayPort SST | HBR3 | Simplex | Fa'atasi e aunoa ma se PCR |
2.1. Intel Agilex F-tile DisplayPort SST Parallel Loopback Design Features
Le SST parallel loopback design exampO lo'o fa'aalia le tu'uina atu o se ata vitio se tasi mai le fa'agogo DisplayPort i le puna DisplayPort e aunoa ma le Pixel Clock Recovery (PCR) i le fua fa'atatau.
Ata 6. Intel Agilex F-tile DisplayPort SST Parallel Loopback e aunoa ma le PCR
- I lenei fesuiaiga, o le DisplayPort source's parameter, TX_SUPPORT_IM_ENABLE, ua ki ma faʻaoga le ata vitio faʻaoga.
- O le DisplayPort sink e maua ai le vitio ma poʻo le faʻalogo leo mai le puna vitio i fafo e pei o le GPU ma faʻavasegaina i totonu o ata vitio tutusa.
- O le DisplayPort goto vitiō e ave sa'o ai le DisplayPort source video interface ma fa'ailoga i le DisplayPort so'otaga autu a'o le'i tu'uina atu i le mata'itū.
- O le IOPLL e fa'aulu uma le fa'agogo DisplayPort ma fa'apogai uati vitio i se taimi fa'amau.
- Afai o le DisplayPort goto ma le puna MAX_LINK_RATE parakalafa ua configured i HBR3 ma PIXELS_PER_CLOCK configured i Quad, o le uati vitio e tamoe i le 300 MHz e lagolago 8Kp30 pika fua (1188/4 = 297 MHz).
2.2. Fuafuaga uati
O lo'o fa'ailoa mai e le fa'ailoga uati le fa'ailoga uati i le DisplayPort Intel FPGA IP design example.
Ata 7. Intel Agilex F-tile DisplayPort Transceiver polokalame uati
Laulau 4. Fa'ailoga Fa'ailoga Fa'ailoga
| Uati i le ata | Fa'amatalaga |
| SysPLL refclk | F-tile System PLL reference clock lea e mafai ona avea ma so'o se taimi uati e mafai ona vaevae e le System PLL mo lena fa'asologa o galuega. I lenei mamanu example, system_pll_clk_link ma rx/tx refclk_link o lo'o fa'asoa tutusa le SysPLL refclk lea e 150Mhz. E tatau ona avea ma se uati e leai se totogi e feso'ota'i mai se pine uati fa'asinomaga fa'apitoa i le uati fa'aulu o le Fa'asinoga ma le System PLL Uati IP, a'o le'i fa'afeso'ota'i le uati fa'atatau i le DisplayPort Phy Top. |
| system_pll_clk_link | Ole la'ititi ole System PLL ole fa'aulufalega e lagolago uma DisplayPort fua ole 320Mhz. O lenei mamanu exampe fa'aaoga le 900 Mhz (maualuga) fa'alava fa'aulu ina ia mafai ona fa'asoa le SysPLL refclk i le rx/tx refclk_link o le 150 Mhz. |
| rx_cdr_refclk_link/tx_pll_refclk_link | Rx CDR ma Tx PLL Link refclk lea na fa'amauina i le 150 Mhz e lagolago uma ai fa'amatalaga fa'amatalaga DisplayPort. |
| rx_ls_clkout/tx O le clkout | DisplayPort Link Speed Clock i le uati DisplayPort IP autu. Fa'atelega tutusa ma le Fa'amatalaga Fa'amatalaga vaevae i le lautele o fa'amaumauga tutusa. ExampLe: Auala = fua faʻamatalaga / lautele faʻamatalaga = 8.1G (HBR3) / 40bits = 202.5 Mhz |
2.3. Simulation Testbench
O le faʻataʻitaʻiga testbench faʻataʻitaʻiina le DisplayPort TX serial loopback i le RX.
Ata 8. DisplayPort Intel FPGA IP Simplex Mode Simulation Testbench Block Diagram
Laulau 5. Vaega Su'esu'e
| Vaega | Fa'amatalaga |
| Vitio Mamanu Faia | O lenei generator e maua ai mamanu pa lanu e mafai ona e faʻatulagaina. E mafai ona e fa'avasega le taimi fa'atulagaina o le vitio. |
| Su'ega Pulea | O lenei poloka e pulea le faʻasologa o suʻega o le faʻataʻitaʻiga ma faʻatupuina faʻailoga faʻamalosi e manaʻomia i le TX autu. E faitau fo'i e le poloka su'esu'e le tau o le CRC mai le puna ma le goto e fai ai fa'atusatusaga. |
| RX Link Speed Clock Time Checker | E fa'amaonia e le siaki lea pe o fetaui le fa'asologa o le uati o le RX transceiver ma le fua faatatau o fa'amaumauga e mana'omia. |
| TX So'otaga Saosaoa Uati Su'e Fa'asao | E fa'amaonia e le siaki lenei pe a fetaui le TX transceiver toe maua mai le taimi ole uati ma le fua faatatau o fa'amatalaga mana'omia. |
O le simulation testbench e faia faʻamaoniga nei:
Laulau 6. Fa'amaoniga a le Testbench
| Tulaga o Su'ega | Fa'amaoniga |
| • Feso'ota'iga a'oa'oga ile Fa'amaumauga HBR3 • Faitau le resitara o le DPCD e siaki ai pe fa'atulaga e le Tulaga DP ma fua uma le TX ma le RX Link Speed frequency. |
Fa'atasi le Su'esu'ega Fa'asa'o e fua ai le fa'alava ole uati ole Link Speed mai le TX ma le RX transceiver. |
| • Fa'asolo ata vitio mai le TX i le RX. • Fa'amaonia le CRC mo le puna ma le goto e siaki pe fetaui |
• Fa'afeso'ota'i generator mamanu ata vitio i le DisplayPort Source e fa'atupu ai le ata vitio. • O le fa'atonuga o le Testbench e soso'o ai e faitau uma le Source ma le Sink CRC mai le DPTX ma le DPRX resitala ma fa'atusatusa ina ia mautinoa e tutusa uma tau o le CRC. Fa'aaliga: Ina ia mautinoa le fuafuaina o le CRC, e tatau ona e faʻaogaina le lagolago CTS suʻega masini masini. |
Tala'aga Toe Iloiloga o Pepa mo le DisplayPort Intel
Agilex F-tile FPGA IP Design Example User Guide
| Fa'amatalaga Fa'amaumauga | Intel Quartus Prime Version | IP Version | Suiga |
| 2021.12.13 | 21.4 | 21.0.0 | Fa'asalalauga muamua. |
Intel Corporation. Ua taofia aia tatau uma. Intel, le Intel logo, ma isi fa'ailoga Intel o fa'ailoga fa'ailoga a le Intel Corporation po'o ona lala. E fa'amaonia e Intel le fa'atinoina o ana oloa FPGA ma semiconductor i fa'amatalaga o lo'o iai nei e tusa ai ma le fa'atonuga masani a Intel, ae fa'asaoina le aia tatau e fai ai suiga i so'o se oloa ma auaunaga i so'o se taimi e aunoa ma se fa'aaliga. E leai se tiute po'o se noataga e afua mai i le talosaga po'o le fa'aogaina o so'o se fa'amatalaga, oloa, po'o se auaunaga o lo'o fa'amatalaina i i'i se'i vagana ua malilie i ai i se faiga tusitusia e Intel. Ua fautuaina tagata fa'atau Intel ina ia maua le fa'amatalaga lata mai o fa'amatalaga masini a'o le'i fa'alagolago i so'o se fa'amatalaga fa'asalalau ma a'o le'i tu'uina atu oka mo oloa po'o tautua.
*O isi igoa ma fa'ailoga e mafai ona ta'ua o se meatotino a isi.
ISO 9001: 2015 Resitala
Faʻasinomaga Faʻainitaneti
Lauina Manatu
UG-20347
ID: 709308
Fa'aliliuga: 2021.12.13
Pepa / Punaoa
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intel DisplayPort Agilex F-Tile FPGA IP Design Example [pdf] Taiala mo Tagata Fa'aoga DisplayPort Agilex F-Tile FPGA IP Design Example, DisplayPort Agilex, F-Tile FPGA IP Design Example, F-Tile FPGA IP Design, FPGA IP Design Example, IP Design Example, IP Design, UG-20347, 709308 |
