intel AN 837 Design Guidelines mo HDMI FPGA IP
Ta'iala mo le HDMI Intel® FPGA IP
O taiala o mamanu e fesoasoani ia te oe e faʻatinoina le High-Definition Multimedia Interface (HDMI) Intel FPGA IPs e faʻaaoga ai masini FPGA. O nei ta'iala e fa'afaigofie ai le fa'atulagaina o laupapa mo feso'ota'iga vitio HDMI Intel® FPGA IP.
- HDMI Intel FPGA IP Taiala Tagata Fa'aoga
- AN 745: Ta'iala mo le Intel FPGA DisplayPort Interface
HDMI Intel FPGA IP Design Taiala
Ole feso'ota'iga HDMI Intel FPGA o lo'o iai fa'amaumauga ole Transition Minimized Differential Signaling (TMDS) ma ala o le uati. O loʻo faʻapipiʻiina foi e le atinaʻe se Vitio Electronics Standards Association (VESA) Faʻaaliga Faʻamatalaga Faʻamatalaga (DDC). O alaleo TMDS o lo'o feavea'i ata vitio, leo, ma ausilali. Ole DDC e fa'avae ile I2C protocol. O le HDMI Intel FPGA IP core e fa'aoga le DDC e faitau ai Fa'amatalaga Fa'amatalaga Fa'amatalaga Fa'alautele (EDID) ma fa'afesuia'i fa'asologa ma fa'amatalaga tulaga i le va o le HDMI puna ma le goto.
HDMI Intel FPGA IP Board Design Fautuaga
A'o e fuafuaina lau HDMI Intel FPGA IP system, mafaufau i fautuaga a le laupapa o lo'o i lalo.
- Fa'aoga aua le sili atu i le lua vias ile su'ega ma 'alo'ese mai fa'amau
- Fa'afetaui le fa'aeseesega o pa'aga fa'atasi i le fa'alavelave o le feso'ota'iga ma le fa'apotopotoga uaea (100 ohm ± 10%).
- Fa'aiti'itia le skew inter-pair ma intra-pair e fetaui ma le TMDS signal skew mana'omia
- Aloese mai le ta'ita'iina o se paga ese'ese i luga o se va i lalo ole vaalele
- Fa'aaogā faiga fa'ata'ita'iga PCB maualuga maualuga
- Fa'aoga sifi tulaga e fa'amalieina le fa'aeletise i le TX ma le RX
- Fa'aoga uaea malolosi, pei ole uaea Cat2 mo HDMI 2.0
Ata fa'ata'atia
O ata faʻataʻitaʻi Bitec i fesoʻotaʻiga tuʻuina atu o loʻo faʻaalia ai le topology mo le Intel FPGA development boards. O le fa'aogaina o le HDMI 2.0 feso'ota'iga topology e mana'omia ai oe e fa'amalieina le 3.3 V eletise. Ina ia ausia le 3.3 V i luga o masini Intel FPGA, e te manaʻomia le faʻaogaina o se suiga maualuga. Fa'aaoga se DC-coupled redriver po'o le retimer e fai ma suiga maualuga mo le transmitter ma receiver.
O masini fa'atau fafo o le TMDS181 ma le TDP158RSBT, o lo'o ta'avale uma i luga o feso'ota'iga DCcoupled. E te mana'omia se toso a'e lelei i laina CEC e fa'amautinoa ai le fa'atinoina pe a fegalegaleai ma isi masini fa'atau mamao. O ata faʻataʻitaʻiga a le Bitec e faʻamaonia CTS. Ae ui i lea, o le fa'amaoniaga, fa'apitoa tulaga o oloa. Ua fautuaina le au faufale e fa'amaonia le oloa mulimuli mo le fa'atinoina lelei.
Fa'amatalaga Fa'atatau
- Ata fa'ata'atia mo le HSMC HDMI Daughter Card Toe Iloiloga 8
- Ata fa'ata'atia mo FMC HDMI Daughter Card Toe Iloiloga 11
- Ata fa'ata'atia mo FMC HDMI Daughter Card Toe Iloiloga 6
Su'esu'e mo'u vevela (HPD)
E fa'alagolago le fa'ailoga HPD ile fa'ailoga + 5V Malosiaga o lo'o o'o mai, mo se fa'ata'ita'igaample, o le HPD pine e mafai ona faʻamaonia pe a iloa le + 5V Power faailo mai le puna. Ina ia faʻafesoʻotaʻi ma se FPGA, e te manaʻomia le faʻaliliuina o le faailo 5V HPD i le FPGA I/O vol.tage maualuga (VCCIO), faʻaaogaina se voltage fa'aliliu tulaga e pei o le TI TXB0102, lea e leai ni fa'atosina toso fa'atasi. E mana'omia e se fa'apogai HDMI e toso i lalo le fa'ailoga HPD ina ia mafai ona fa'atuatuaina le va'aiga i le va o le fa'ailoga HPD opeopea ma le vol maualuga.tage maualuga faailo HPD. E tatau ona fa'aliliu se fa'ailoga HDMI +5V Malosi i le FPGA I/O voltage tulaga (VCCIO). O le faailo e tatau ona toso vaivai i lalo ma se tetee (10K) e faʻaeseese ai le faʻafefeteina + 5V Power faailo pe a le faʻauluina e se HDMI puna. O le HDMI puna + 5V Malosi'i faailo o loʻo i ai le puipuiga o loʻo i ai nei e le sili atu i le 0.5A.
HDMI Intel FPGA IP Fa'aali Fa'amatalaga Fa'amatalaga (DDC)
O le HDMI Intel FPGA IP DDC e faʻavae i luga o faailo I2C (SCL ma SDA) ma e manaʻomia ni faʻalavelave toso. Ina ia faʻafesoʻotaʻi ma se Intel FPGA, e tatau ona e faʻaliliuina le 5V SCL ma le SDA faʻailoga maualuga ile FPGA I/O voltage maualuga (VCCIO) fa'aaoga se voltage fa'aliliu tulaga, e pei o le TI TXS0102 e pei ona fa'aogaina i le Bitec HDMI 2.0 daughter card. Ole TI TXS0102 voltage tulaga faaliliu masini integrates toso i luga tetee i totonu ina ia leai i luga o le laupapa toso i luga tetee e manaomia.
Fa'amatalaga Toe Iloiloga o Fa'amaumauga mo AN 837: Fa'ata'ita'iga mo le HDMI Intel FPGA IP
| Fa'amatalaga Fa'amaumauga | Suiga |
| 2019.01.28 |
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| Aso | Fa'aliliuga | Suiga |
| Ianuari 2018 | 2018.01.22 | Fa'asalalauga muamua.
Manatua: O lenei pepa o loʻo i ai HDMI Intel FPGA taʻiala mamanu na aveese mai le AN 745: Design Guidelines for DisplayPort ma HDMI Interfaces ma toe faʻaigoaina AN 745: Design Guidelines for Intel FPGA DisplayPort Interface. |
Intel Corporation. Ua taofia aia tatau uma. Intel, le Intel logo, ma isi fa'ailoga Intel o fa'ailoga fa'atau a le Intel Corporation po'o ona lala. E fa'amaonia e Intel le fa'atinoina o ana oloa FPGA ma semiconductor i fa'amatalaga o lo'o iai nei e tusa ai ma le fa'atonuga masani a Intel ae fa'asaoina le aia tatau e fai ai suiga i so'o se oloa ma auaunaga i so'o se taimi e aunoa ma se fa'aaliga. E leai se tiute po'o se noataga e afua mai i le talosaga po'o le fa'aogaina o so'o se fa'amatalaga, oloa, po'o se auaunaga o lo'o fa'amatalaina i i'i se'i vagana ua malilie fa'aalia i se faiga tusitusia e Intel. Ua fautuaina tagata fa'atau Intel e maua le fa'amatalaga lata mai o fa'amatalaga masini a'o le'i fa'alagolago i so'o se fa'amatalaga fa'asalalau ma a'o le'i tu'uina atu oka mo oloa po'o tautua.
O isi igoa ma fa'ailoga e mafai ona ta'ua o se meatotino a isi.
ID: 683677
Fa'aliliuga: 2019-01-28
Pepa / Punaoa
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intel AN 837 Design Guidelines mo HDMI FPGA IP [pdf] Taiala mo Tagata Fa'aoga AN 837 Design Guidelines mo HDMI FPGA IP, AN 837, Design Guidelines mo HDMI FPGA IP, Taiala mo HDMI FPGA IP, HDMI FPGA IP |
