F-Tile JESD204C Intel FPGA IP Design Example

Game da F-Tile JESD204C Intel® FPGA IP Design ExampJagorar Mai Amfani

Wannan jagorar mai amfani yana ba da fasali, jagororin amfani, da cikakken bayanin ƙirar ƙiraampLes don F-Tile JESD204C Intel® FPGA IP ta amfani da na'urorin Intel Agilex™.

Masu Sauraron Niyya

Anyi nufin wannan takarda don:

• Ƙirƙirar ƙirar ƙira don yin zaɓin IP yayin tsarin tsara matakin ƙirar tsarin
• Masu zanen kayan aiki lokacin haɗa IP ɗin cikin ƙirar matakin tsarin su
• Injiniyoyin tabbatarwa yayin ƙirar matakin tsarin da lokacin tabbatar da kayan aiki

Takardu masu alaƙa
Tebur mai zuwa yana lissafin wasu takaddun tunani waɗanda ke da alaƙa da F-Tile JESD204C Intel FPGA IP.

Tebur 1. Takardu masu alaƙa

Magana	Bayani
F-Tile JESD204C Intel FPGA IP Jagorar mai amfani	Yana ba da bayani game da F-Tile JESD204C Intel FPGA IP.
F-Tile JESD204C Bayanan Sakin Intel FPGA IP	Ya lissafa canje-canjen da aka yi don F-Tile JESD204C F-Tile JESD204C a cikin wani saki na musamman.
Bayanan Bayani na Na'urar Intel Agilex	Wannan takaddun yana bayyana halayen lantarki, halayen canzawa, ƙayyadaddun ƙayyadaddun tsari, da lokacin na'urorin Intel Agilex.

Acronyms da ƙamus

Tebur 2. Jerin Gagarumi

Acronym	Fadadawa
LEMC	Agogon Multiblock Mai Girma na Gida
FC	Yawan agogon firam
ADC	Analog zuwa Digital Converter
DAC	Canjin dijital zuwa Analog
DSP	Mai sarrafa siginar Dijital
TX	Mai watsawa
RX	Mai karɓa

Acronym	Fadadawa
DLL	Bayanin haɗin haɗin bayanai
CSR	Gudanarwa da rajistar matsayi
CRU	Agogo da Sake saitin Unit
ISR	Kashe Sabis na Yau da kullun
FIFO	Farko-In-Farko-Fita
SERDES	Serializer Deserializer
ECC	Kuskuren Gyara Code
FEC	Kuskuren Kuskuren Farko
SERR	Gano Kuskure Guda ɗaya (a cikin ECC, ana iya gyarawa)
DERR	Gano Kuskure Biyu (a cikin ECC, mai mutuwa)
PRBS	Tsarin binary na pseudorandom
MAC	Mai Kula da Samun Mai jarida. MAC ya haɗa da sublayer na yarjejeniya, Layer sufuri, da Layer link Layer.
PHY	Layer na Jiki. PHY yawanci ya haɗa da Layer na zahiri, SERDES, direbobi, masu karɓa da CDR.
PCS	Sub-Layer Codeing na Jiki
PMA	Haɗin Matsakaici na Jiki
RBD	RX Buffer Jinkiri
UI	Tazarar Raka'a = Tsawon lokacin serial bit
Farashin RBD	RX Buffer Jinkirta sabuwar hanya
Farashin RBD	RX Buffer Jinkirin sakin damar
SH	Daidaitaccen taken
TL	Jigilar sufuri
EMIB	Ƙaddamar da Multi-die Interconnect Bridge

Tebur 3. Jerin Kalmomi

Lokaci	Bayani
Na'urar Converter	ADC ko DAC Converter
Na'urar dabaru	FPGA ko ASIC
Octet	Ƙungiya na 8 ragowa, yin aiki azaman shigarwa zuwa 64/66 encoder da fitarwa daga mai ƙididdigewa.
Nibble	Saitin 4 ragowa wanda shine rukunin aiki na tushe na ƙayyadaddun JESD204C
Toshe	Alamar 66-bit wanda tsarin tsarin 64/66 ya samar
Layin Layi	Ingantacciyar ƙimar hanyar haɗin yanar gizo Layin Layi = (Mx Sx N'x 66/64 x FC) / L
Agogon haɗin gwiwa	Agogon haɗin gwiwa = Ƙimar Layin Layi/66.
Frame	Saitin octets a jere wanda za'a iya gano matsayin kowane octet ta hanyar la'akari da siginar daidaitawa.
Agogon Frame	Agogon tsarin da ke gudana akan ƙimar firam, wanda dole ne ya zama agogon haɗin gwiwa 1x da 2x.

Lokaci	Bayani
SampLes kowane agogon frame	Samples a kowace agogo, jimlar sampLes a cikin agogon firam don na'urar mai juyawa.
LEMC	Agogon ciki da aka yi amfani da shi don daidaita iyakar faɗaɗɗen katanga tsakanin hanyoyi zuwa cikin abubuwan da ke waje (SYSREF ko Subclass 1).
Subclass 0	Babu goyan bayan latency deterministic. Ya kamata a fitar da bayanai nan da nan akan titin zuwa layin deskew akan mai karɓa.
Subclass 1	Ƙaddara latency ta amfani da SYSREF.
Multipoint Link	Hanyoyin haɗin na'ura tare da na'urori 2 ko fiye da masu juyawa.
64B / 66B sauyawa	Lambar layi wanda ke tsara bayanan 64-bit zuwa 66 ragowa don samar da toshe. Tsarin bayanan matakin tushe wani toshe ne wanda ke farawa da taken daidaitawa na 2-bit.

Tebur 4. Alamomi

Lokaci	Bayani
L	Adadin hanyoyi a kowace na'ura mai canzawa
M	Adadin masu juyawa kowace na'ura
F	Adadin octets a kowane firam akan layi ɗaya
S	Adadin samples watsa kowane guda Converter kowane firam sake zagayowar
N	ƙudurin mai canzawa
N'	Jimlar adadin ragi a kowace sample a cikin tsarin bayanan mai amfani
CS	Adadin raguwar sarrafawa a kowane juzu'i sample
CF	Adadin kalmomin sarrafawa kowane lokacin agogon firam kowace mahaɗi
HD	Tsarin bayanan mai amfani mai girma
E	Adadin katangawa a cikin dogon bulogi

F-Tile JESD204C Intel FPGA IP Design ExampJagorar Farawa Mai sauri

F-Tile JESD204C Intel FPGA IP ƙiraamples don na'urorin Intel Agilex suna da simulating testbench da ƙirar kayan masarufi waɗanda ke goyan bayan haɗawa da gwajin kayan aiki.
Kuna iya ƙirƙirar ƙirar F-Tile JESD204C exampta hanyar kasidar IP a cikin Intel Quartus® Prime Pro Edition software.

Hoto 1. Ci gaban Stages don Design Example

Zane Exampda Block zane

Hoto 2. F-Tile JESD204C Zane ExampZane-zane na Babban matakin Block

Zane example ya ƙunshi abubuwa masu zuwa:

• Tsarin Tsarin Platform
  • F-Tile JESD204C Intel FPGA IP
  • JTAG zuwa Avalon Master Bridge
  • Parallel I/O (PIO) mai sarrafawa
  • Serial Port Interface (SPI) — babban module — IOPLL
  • SYSREF janareta
  • Exampda Design (ED) Sarrafa CSR
  • Sake saitin jerin abubuwa
• Tsarin PLL
• Tsarin janareta
• Mai duba tsari

Tebur 5. Zane Exampda Modules

Abubuwan da aka gyara	Bayani
Tsarin Tsarin Platform	Tsarin Platform Designer yana aiwatar da hanyar F-Tile JESD204C ta hanyar bayanan IP da masu goyan baya.
F-Tile JESD204C Intel FPGA IP	Wannan Tsarin Tsarin Tsarin Platform yana ƙunshe da TX da RX F-Tile JESD204C IPs tare da PHY duplex.
JTAG zuwa Avalon Master Bridge	Wannan gada tana ba da damar na'ura mai ba da hanya tsakanin hanyoyin sadarwa zuwa IP mai taswirar ƙwaƙwalwar ajiya a cikin ƙira ta hanyar JTAG dubawa.
Parallel I/O (PIO) mai sarrafawa	Wannan mai sarrafa yana ba da ƙa'idar ƙwaƙwalwar taswira don sampling da tuki gabaɗaya I/O tashoshin jiragen ruwa.
Babban darajar SPI	Wannan ƙirar tana ɗaukar serial canja wurin bayanan sanyi zuwa ƙirar SPI akan ƙarshen mai juyawa.
SYSREF janareta	SYSREF janareta yana amfani da agogon hanyar haɗi azaman agogon tunani kuma yana haifar da bugun jini na SYSREF don F-Tile JESD204C IP. Lura: Wannan zane exampLe yana amfani da janareta na SYSREF don nuna duplex F-Tile JESD204C IP haɗin farawa. A cikin aikace-aikacen matakin tsarin F-Tile JESD204C subclass 1, dole ne ku samar da SYSREF daga tushe ɗaya da agogon na'ura.
IOPLL	Wannan zane exampLe yana amfani da IOPLL don samar da agogon mai amfani don watsa bayanai cikin F-Tile JESD204C IP.
ED Control CSR	Wannan tsarin yana ba da kulawar ganowa da matsayi na SYSREF, da gwajin sarrafawa da matsayi.
Sake saitin jerin abubuwa	Wannan zane exampLe ya ƙunshi jerin sake saiti guda 2: Sake saitin Jeri 0- Yana riƙe da sake saiti zuwa TX/RX Avalon® yanki mai yawo, yankin Avalon memory-mapped, core PLL, TX PHY, TX core, da SYSREF janareta. Sake saitin Jeri na 1 - Yana ɗaukar sake saiti zuwa RX PHY da RX core.
Tsarin PLL	Tushen agogo na farko don F-tile hard IP da EMIB.
Tsarin janareta	Samfurin janareta yana haifar da PRBS ko ramp tsari.
Mai duba tsari	Mai duba ƙirar yana tabbatar da PRBS ko ramp samfurin da aka karɓa, kuma yana nuna kuskure lokacin da ya sami rashin daidaituwa na bayanan sample.

Bukatun Software

Intel yana amfani da software mai zuwa don gwada ƙirar ƙiraampa cikin tsarin Linux:

• Intel Quartus Prime Pro Edition software
• Questa*/ModelSim* ko VCS*/VCS MX na'urar kwaikwayo

Samar da Zane

Don samar da zane example daga editan sigar IP:

1. Ƙirƙiri aikin da ke niyya dangin na'urar Intel Agilex F-tile kuma zaɓi na'urar da ake so.
2. A cikin IP Catalog, Kayan aiki ➤ IP Catalog, zaɓi F-Tile JESD204C Intel FPGA IP.
3. Ƙayyade sunan babban matakin da babban fayil don bambancin IP na al'ada. Danna Ok. Editan siga yana ƙara babban matakin .ip file zuwa aikin na yanzu ta atomatik. Idan an sa ka ƙara da .ip file zuwa aikin, danna Project ➤ Ƙara / Cire Files a cikin Project don ƙara da file.
4. Karkashin Example Design tab, saka zane example sigogi kamar yadda aka bayyana a Design Exampda Parameters.
5. Danna Ƙirƙirar Exampda Design.

Software yana haifar da duk ƙira files a cikin sub-directory. Wadannan fileAna buƙatar s don gudanar da simulation da haɗawa.

Zane Exampda Parameters
F-Tile JESD204C Intel FPGA IP editan siga ya haɗa da ExampLe Design shafin don saka wasu sigogi kafin samar da zane example.

Tebur 6. Ma'auni a cikin Exampda Design Tab

Siga	Zabuka	Bayani
Zaɓi Zane	Sarrafa Console System Babu	Zaɓi tsarin kula da na'ura wasan bidiyo don samun dama ga ƙira examphanyar data ta hanyar na'ura mai kwakwalwa.
kwaikwayo	Kunnawa, Kashe	Kunna IP ɗin don samar da abin da ake buƙata files don simulating da zane example.
Magana	Kunnawa, Kashe	Kunna IP ɗin don samar da abin da ake buƙata files don Haɗin Intel Quartus Prime da nunin kayan aiki.
Tsarin HDL (don kwaikwayo)	Verilog Farashin VDHL	Zaɓi tsarin HDL na RTL files don kwaikwayo.
Tsarin HDL (don hadawa)	Verilog kawai	Zaɓi tsarin HDL na RTL files don kira.

Siga	Zabuka	Bayani
Ƙirƙirar 3- waya SPI module	Kunnawa, Kashe	Kunna don kunna 3-waya SPI dubawa maimakon 4-waya.
Yanayin Sysref	harbi daya Na lokaci-lokaci Gapped lokaci-lokaci	Zaɓi ko kuna son daidaitawar SYSREF ta zama yanayin bugun bugun jini guda ɗaya, na lokaci-lokaci, ko tazara na lokaci-lokaci, dangane da buƙatun ƙira da sassaucin lokaci. Shot Daya — Zaɓi wannan zaɓi don baiwa SYSREF damar zama yanayin bugun bugun jini ɗaya. Ƙimar sysref_ctrl[17] rijistar bit shine 0. Bayan F-Tile JESD204C IP sake saitin kayan zaki, canza darajar sysref_ctrl[17] daga 0 zuwa 1, sannan zuwa 0, don bugun bugun SYSREF mai harbi daya. Lokaci-lokaci-SYSREF a cikin yanayin lokaci-lokaci yana da 50:50 zagayowar ayyuka. Lokacin SYSREF shine E*SYSREF_MULP. Gapped lokaci-SYSREF yana da shirye-shirye na aikin sake zagayowar granularity na mahaɗin agogo 1. Lokacin SYSREF shine E*SYSREF_MULP. Don saitin sake zagayowar ayyuka na waje, toshewar SYSREF ya kamata ya ba da damar sake zagayowar ayyuka 50:50 ta atomatik. Koma zuwa ga SYSREF Generator sashe don ƙarin bayani game da SYSREF lokaci.
Zaɓi allo	Babu	Zaɓi allon don ƙira example. Babu-Wannan zaɓin ya keɓance abubuwan kayan masarufi don ƙirar tsohuwarample. Duk ayyukan fil za a saita su zuwa fil masu kama-da-wane.
Tsarin Gwaji	Bayanan Bayani na PRBS-7 Bayanan Bayani na PRBS-9 Bayanan Bayani na PRBS-15 Bayanan Bayani na PRBS-23 Ramp	Zaɓi janareta ƙirar ƙira da ƙirar gwajin duba. Samfurin Samfura-JESD204C yana goyan bayan janareta ƙirar ƙirar PRBS akan kowane sample. Wannan yana nufin cewa faɗin bayanan zaɓin N+CS ne. PRBS janareta da mai duba suna da amfani don ƙirƙirar bayanan sample stimulus don gwaji kuma bai dace da yanayin gwajin PRBS akan mai sauya ADC/DAC ba. Ramp Samfuran Generator-JESD204C Layer mahada yana aiki akai-akai amma jigilar kaya daga baya ba a kashe kuma an yi watsi da shigarwar daga mai tsarawa. Kowane layi yana watsa rafin octet iri ɗaya wanda ke ƙaruwa daga 0x00 zuwa 0xFF sannan kuma yana maimaitawa. Ramp Ana kunna gwajin ƙirar ta prbs_test_ctl. PRBS Pattern Checker-JESD204C PRBS scrambler yana aiki tare da kai kuma ana tsammanin lokacin da tushen IP ya sami damar yanke hanyar haɗin gwiwa, zuriyar ta riga ta daidaita. PRBS scrambling iri zai ɗauki octets 8 don farawa da kansa. Ramp Mai duba Ala-JESD204C scrambling yana aiki tare da kai kuma ana sa ran lokacin da tushen IP ya sami damar yanke hanyar haɗin gwiwa, zuriyar ɓarna an riga an daidaita su. Ana loda madaidaicin octet na farko azaman ramp ƙimar farko. Bayanan da ke gaba dole ne su ƙaru har zuwa 0xFF kuma su mirgine zuwa 0x00. Ramp ya kamata mai duba tsari ya bincika irin wannan tsari a duk hanyoyi.
Kunna madauki serial na ciki	Kunnawa, Kashe	Zaɓi madauki serial na ciki.
Kunna Tashar Umurni	Kunnawa, Kashe	Zaɓi tsarin tashar umarni.

Tsarin Jagora
F-Tile JESD204C zane exampkundayen adireshi sun ƙunshi ƙirƙira files don zane examples.

Hoto na 3. Tsarin Jagora don F-Tile JESD204C Intel Agilex Design Example

Tebura 7. Jagora Files

Jakunkuna	Files
ed/rtl	tx j204c_f_tx_ip.qsys j204c_f tx_ss.qsys altera_s10_user_rst_clkgate_0.ip j204c f_se_outbuf_1bit.ip
kwaikwayo / jagora	modelim_sim.tcl tb_top_waveform.do
kwaikwayo / synopsys	vcs vcs_sim.sh tb_top_wave_ed.do vcsmx vcsmx_sim.sh tb_top_wave_ed.do

Simulating da Design Exampda Testbench

Zane example testbench yana kwaikwayar ƙirar da kuka ƙirƙira.

Hoto 4. Tsari

Don kwaikwayi ƙirar, yi matakai masu zuwa:

1. Canja littafin aiki zuwaample_design_directory>/simulation/ .
2. A cikin layin umarni, gudanar da rubutun kwaikwayo. Teburin da ke ƙasa yana nuna umarni don gudanar da na'urar kwaikwayo masu goyan baya.

Na'urar kwaikwayo	Umurni
Questa/ModelSim	vsim -do modelim_sim.tcl
	vsim -c -do modelim_sim.tcl (ba tare da Questa/ ModelSim GUI ba)
VCS	shvcs_sim.sh
Farashin VCS MX	shvcsmx_sim.sh

Simulation ya ƙare da saƙonnin da ke nuna ko gudu ya yi nasara ko a'a.

Hoto 5. Nasarar Kwaikwayo
Wannan adadi yana nuna nasarar nasarar saƙon kwaikwayo na VCS na'urar kwaikwayo.

Haɗa Zane Example

Don haɗa tarin-kawai exampdon aikin, bi waɗannan matakan:

1. Tabbatar da ƙirar ƙira example tsara ya cika.
2. A cikin software na Intel Quartus Prime Pro Edition, buɗe aikin Intel Quartus Prime Pro Editionample_ design_ directory>/ed/quartus.
3. A cikin menu na sarrafawa, danna Fara Tari.

Cikakken Bayani don F-Tile JESD204C Design Example

F-Tile JESD204C zane example yana nuna ayyukan watsa bayanai ta amfani da yanayin loopback.
Kuna iya ƙididdige saitunan sigogi na zaɓinku kuma samar da ƙira example.
Zane example yana samuwa ne kawai a cikin yanayin duplex don duka Base da bambancin PHY. Kuna iya zaɓar Base kawai ko PHY kawai bambance-bambancen amma IP zai haifar da ƙiraample don duka Base da PHY.

Lura:  Wasu manyan saitunan ƙimar bayanai na iya gazawar lokaci. Don guje wa gazawar lokaci, yi la'akari da ƙididdige ƙimar mitar agogon ƙananan firam (FCLK_MULP) a cikin Saitunan shafin na F-Tile JESD204C Intel FPGA IP editan siga.

Abubuwan Tsari

F-Tile JESD204C zane example yana ba da kwararar sarrafawa ta tushen software wanda ke amfani da naúrar sarrafawa tare da ko ba tare da goyon bayan na'ura mai ba da hanya tsakanin hanyoyin sadarwa.

Zane exampyana ba da damar haɗin kai ta atomatik a cikin yanayin madauki na ciki da na waje.

JTAG zuwa Avalon Master Bridge
A JTAG zuwa ga Avalon Master Bridge yana ba da haɗin kai tsakanin tsarin mai watsa shiri don samun damar F-Tile JESD204C IP da aka yi amfani da ƙwaƙwalwar ajiya da kuma kula da IP na gefe da rajista ta hanyar J.TAG dubawa.

Hoto na 6. System tare da JTAG zuwa Avalon Master Bridge Core

Lura:  Dole ne agogon tsarin ya zama aƙalla 2X da sauri fiye da JTAG agogo. Agogon tsarin shine mgmt_clk (100MHz) a cikin wannan ƙirar misaliample.

Parallel I/O (PIO) Core
Madaidaicin shigarwa / fitarwa (PIO) core tare da Avalon interface yana ba da damar yin amfani da taswirar ƙwaƙwalwar ajiya tsakanin tashar jiragen ruwa na Avalon da aka yi taswirar ƙwaƙwalwar ajiya da maƙallan I / O na gaba ɗaya. Tashar jiragen ruwa na I/O suna haɗa ko dai zuwa tunanin mai amfani akan guntu, ko zuwa fil ɗin I/O waɗanda ke haɗa na'urori na waje zuwa FPGA.

Hoto na 7. PIO Core tare da Tashoshin shigarwa, Tashoshin fitarwa, da Tallafin IRQ
Ta hanyar tsoho, ɓangaren Mai tsara Platform yana hana Layin Sabis na Katse (IRQ).

Ana sanya tashoshin jiragen ruwa na PIO I/O a matakin babban matakin HDL file ( Matsayin io_ don shigar da tashar jiragen ruwa, io_ iko don tashoshin fitarwa).

Teburin da ke ƙasa yana kwatanta haɗin siginar don matsayi da iko da tashar I / O zuwa maɓallin DIP da LED akan kayan haɓakawa.

Tebur 8. PIO Core I/O Ports

Port	Bit	Sigina
Out_port	0	An yi shirye-shiryen USER_LED SPI
	31:1	Ajiye
A cikin_port	0	USER_DIP serial loopback na ciki yana kunna kashewa = 1 Na = 0
	1	USER_DIP SYSREF mai samar da FPGA yana kunna kashe = 1 Na = 0
	31:2	Ajiye

Babban darajar SPI
SPI master module shine ma'auni na Platform Designer a cikin daidaitaccen ɗakin karatu na Catalog na IP. Wannan tsarin yana amfani da ka'idar SPI don sauƙaƙe daidaitawar masu sauya waje (misaliample, ADC, DAC, da masu samar da agogo na waje) ta hanyar sararin rajistar da aka tsara a cikin waɗannan na'urori.

Maigidan SPI yana da ƙirar ƙwaƙwalwar ajiya ta Avalon wacce ke haɗawa da Avalon master (JTAG zuwa Avalon master gada) ta hanyar haɗin gwiwar Avalon da aka yi taswirar ƙwaƙwalwar ajiya. Maigidan SPI yana karɓar umarnin daidaitawa daga maigidan Avalon.

Babban tsarin SPI yana sarrafa bayin SPI masu zaman kansu 32. An saita ƙimar baud na SCLK zuwa 20 MHz (wanda aka raba ta 5).
An saita wannan tsarin zuwa waya mai 4-bit, 24-bit interface interface. Idan aka zaɓi zaɓin Ƙirƙirar 3-Wire SPI Module, ƙarin ƙirar yana nan take don canza fitarwa mai waya 4 na SPI master zuwa 3-waya.

IOPLL
IOPLL yana haifar da agogon da ake buƙata don samar da frame_clk da link_clk. Ana iya daidaita agogon tunani zuwa PLL amma yana iyakance ga ƙimar bayanai/factor na 33.

• Domin zane exampwanda ke goyan bayan ƙimar bayanai na 24.33024 Gbps, ƙimar agogo don frame_clk da link_clk shine 368.64 MHz.
• Domin zane exampwanda ke goyan bayan ƙimar bayanai na 32 Gbps, ƙimar agogo don frame_clk da link_clk shine 484.848 MHz.

SYSREF Generator
SYSREF siginar lokaci ce mai mahimmanci don masu canza bayanai tare da F-Tile JESD204C interface.

SYSREF janareta a cikin zane example ana amfani da duplex JESD204C IP mahada farkon nunin manufar kawai. A cikin aikace-aikacen matakin tsarin JESD204C subclass 1, dole ne ku samar da SYSREF daga tushe ɗaya da agogon na'ura.

Don F-Tile JESD204C IP, SYSREF multiplier (SYSREF_MULP) na rajistar sarrafa SYSREF yana bayyana lokacin SYSREF, wanda shine n-integer mahara na ma'aunin E.

Dole ne ku tabbatar da E*SYSREF_MULP ≤16. Don misaliample, idan E=1, saitin doka na SYSREF_MULP dole ne ya kasance tsakanin 1-16, kuma idan E=3, saitin doka na SYSREF_MULP ya kasance tsakanin 1-5.

Lura:  Idan kun saita SYSREF_MULP mara iyaka, janareta na SYSREF zai gyara saitin zuwa SYSREF_MULP=1.
Kuna iya zaɓar ko kuna son nau'in SYSREF ya zama bugun bugun jini, lokaci-lokaci, ko tazara ta lokaci-lokaci ta hanyar Ex.ampLe Design shafin a cikin F-Tile JESD204C Intel FPGA IP editan siga.

Tebur 9. ExampLes na lokaci-lokaci da Gapped Periodic SYSREF Counter

E	SYSREF_MULP	LOKACIN SYSREF (E*SYSREF_MULP* 32)	Zagayen aiki	Bayani
1	1	32	1..31 (Mai shiri)	Tsawon Lokaci
1	1	32	16 (Kafaffen)	Na lokaci-lokaci
1	2	64	1..63 (Mai shiri)	Tsawon Lokaci
1	2	64	32 (Kafaffen)	Na lokaci-lokaci
1	16	512	1..511 (Mai shiri)	Tsawon Lokaci
1	16	512	256 (Kafaffen)	Na lokaci-lokaci
2	3	19	1..191 (Mai shiri)	Tsawon Lokaci
2	3	192	96 (Kafaffen)	Na lokaci-lokaci
2	8	512	1..511 (Mai shiri)	Tsawon Lokaci
2	8	512	256 (Kafaffen)	Na lokaci-lokaci
2	9 (Ba bisa doka ba)	64	32 (Kafaffen)	Tsawon Lokaci
2	9 (Ba bisa doka ba)	64	32 (Kafaffen)	Na lokaci-lokaci

 

Table 10. SYSREF Gudanar da Rajista
Kuna iya sake saita rajistar sarrafa SYSREF idan tsarin rajista ya bambanta da saitin da kuka ayyana lokacin da kuka ƙirƙiri tsohon ƙira.ample. Sanya rajistar SYSREF kafin F-Tile JESD204C Intel FPGA IP bai sake saiti ba. Idan ka zaɓi janareta na SYSREF na waje ta hanyar
sysref_ctrl[7] rejista bit, za ka iya watsi da saituna don SYSREF nau'in, multiplier, duty cycle da phase.

Bits	Default Value	Bayani
sysref_ctrl[1:0]	2'b00: harbi daya 2'b01: lokaci-lokaci 2'b10: Tsawon lokaci	Nau'in SYSREF. Ƙimar tsohowar ta dogara da tsarin tsarin SYSREF a cikin Exampda Design shafin a cikin F-Tile JESD204C Intel FPGA IP editan siga.
sysref_ctrl[6:2]	5 b00001 ku	SYSREF mai yawa. Wannan filin SYSREF_MULP yana da amfani ga nau'in SYSREF na lokaci-lokaci da tazara. Dole ne ku saita ƙimar ninkawa don tabbatar da ƙimar E*SYSREF_MULP tsakanin 1 zuwa 16 kafin F-Tile JESD204C IP ya fita daga sake saiti. Idan darajar E*SYSREF_MULP ba ta cikin wannan kewayon, ƙimar ninkawa ta gaza zuwa 5'b00001.
sysref_ctrl[7]	Hanyar bayanai ta Duplex: 1'b1 Hanyar hanyar bayanai ta Simplex TX ko RX: 1'b0	SYSREF zaɓi. Ƙimar tsoho ya dogara da saitin hanyar bayanai a cikin ExampLe Design shafin a cikin F-Tile JESD204C Intel FPGA IP editan siga. 0: Simplex TX ko RX (SYSREF na waje) 1: Duplex (SYSREF na ciki)
sysref_ctrl[16:8]	9'h0	Zagayowar aikin SYSREF lokacin da nau'in SYSREF ke zama na lokaci-lokaci ko kuma na ɗan lokaci. Dole ne ku saita zagayowar aiki kafin F-Tile JESD204C IP bai sake saiti ba. Matsakaicin ƙima = (E*SYSREF_MULP*32)-1 Ga misaliampda: Zagayowar aikin 50% = (E*SYSREF_MULP*32)/2 Tsarin sake zagayowar aiki ya ƙare zuwa 50% idan ba ku saita wannan filin rajista ba, ko kuma idan kun saita filin rajista zuwa 0 ko fiye fiye da matsakaicin ƙimar da aka yarda.
sysref_ctrl[17]	1 b0 ku	Ikon hannun hannu lokacin da nau'in SYSREF shine harbi daya. Rubuta 1 don saita siginar SYSREF zuwa sama. Rubuta 0 don saita siginar SYSREF zuwa ƙasa. Kuna buƙatar rubuta 1 sannan 0 don ƙirƙirar bugun bugun SYSREF a yanayin harbi ɗaya.
sysref_ctrl[31:18]	22'h0	Ajiye

Sake saitin Mabiyoyi
Wannan zane example ya ƙunshi jerin sake saiti guda biyu:

• Sake saitin Jeri 0 - Yana ɗaukar sake saiti zuwa yankin rafi na TX/RX Avalon, yankin ƙwaƙwalwar ajiyar Avalon, ainihin PLL, TX PHY, TX core, da janareta na SYSREF.
• Sake saitin Jeri na 1 - Yana ɗaukar sake saiti zuwa RX PHY da RX Core.

3-Way SPI
Wannan tsarin zaɓin zaɓi ne don canza ƙa'idar SPI zuwa waya 3.

Tsarin PLL
F-tile yana da tsarin PLL guda uku akan allo. Wadannan tsarin PLLs sune tushen agogo na farko don IP mai wuya (MAC, PCS, da FEC) da EMIB. Wannan yana nufin cewa, lokacin da kake amfani da tsarin PLL clocking yanayin, ba a rufe tubalan da agogon PMA kuma ba su dogara da agogon da ke fitowa daga ainihin FPGA ba. Kowane tsarin PLL yana haifar da agogon da ke da alaƙa da mitar mitoci ɗaya kawai. Domin misaliampHar ila yau, kuna buƙatar tsarin PLLs guda biyu don gudanar da dubawa ɗaya a 1 GHz da kuma dubawa ɗaya a 500 MHz. Amfani da tsarin PLL yana ba ku damar amfani da kowane layi da kansa ba tare da canjin agogon layin da ya shafi layin makwabta ba.
Kowane tsarin PLL na iya amfani da kowane ɗayan agogon nunin FGT guda takwas. Tsarin PLLs na iya raba agogon tunani ko samun agogon tunani daban-daban. Kowane mai dubawa zai iya zaɓar tsarin PLL ɗin da yake amfani da shi, amma, da zarar an zaɓa, an gyara shi, ba za a sake daidaita shi ta amfani da sake daidaitawa mai ƙarfi ba.

Bayanai masu alaƙa
F-tile Architecture da PMA da FEC Direct PHY IP Jagorar Mai amfani

Ƙarin bayani game da tsarin PLL clocking yanayin a cikin Intel Agilex F-tile na'urorin.

Samfuran Generator da Checker
Na'urar janareta da mai duba suna da amfani don ƙirƙirar bayanan samples da saka idanu don dalilai na gwaji.
Tebur 11. Mai Goyan bayan Samfurin Samfura

Tsarin Generator	Bayani
PRBS tsarin janareta	F-Tile JESD204C zane exampLe PRBS janareta mai ƙira yana goyan bayan digiri mai zuwa na polynomials: PRBS23: X23+X18+1 PRBS15: X15+X14+1 PRBS9: X9+X5+1 PRBS7: X7+X6+1
Ramp janareta samfurin	A ramp ƙimar ƙirar ta ƙaru da 1 ga kowane s na gabaample tare da faɗin janareta na N, kuma yana jujjuyawa zuwa 0 lokacin da duk ragi a cikin sampku su 1. Kunna ramp janareta ta hanyar rubuta 1 zuwa bit 2 na rajistar tst_ctl na toshe sarrafa ED.
Umurnin tashar ramp janareta samfurin	F-Tile JESD204C zane example goyan bayan tashar umarni ramp janareta samfurin kowane layi. A ramp Ƙimar tsari yana ƙaruwa da 1 cikin rago 6 na kalmomin umarni. Iri na farawa shine tsarin haɓakawa a duk hanyoyi.

Tebura 12. Mai Tallafawa Alamar Dubawa

Mai duba tsari	Bayani
Mai duba tsarin PRBS	Iri mai ɓarna a cikin mai duba ƙirar yana aiki tare da kansa lokacin da F-Tile JESD204C IP ta cimma daidaitawar tebur. Mai duba ƙirar yana buƙatar octets 8 don iri mai ɓarna don yin aiki tare da kai.
Ramp mai duba tsari	Ingantattun bayanai na farko sample ga kowane mai juyawa (M) ana loda shi azaman ƙimar farko na ramp tsari. Bayanan da suka biyo baya sampLes ƙima dole ne su ƙaru da 1 a kowane zagayowar agogo har zuwa matsakaicin sa'an nan kuma mirgine zuwa 0.

Mai duba tsari	Bayani
	Don misaliample, lokacin da S=1, N=16 da WIDTH_MULP = 2, fadin bayanan kowane mai canzawa shine S * WIDTH_MULP * N = 32. Matsakaicin bayanai sampLe darajar ne 0xFFFF. A ramp Mai duba tsari yana tabbatar da cewa ana karɓar samfura iri ɗaya a duk masu juyawa.
Umurnin tashar ramp mai duba tsari	F-Tile JESD204C zane example goyan bayan tashar umarni ramp mai duba tsari. Ana loda kalmar umarni ta farko (bits 6) da aka karɓa azaman ƙimar farko. Kalmomin umarni na gaba a cikin layi ɗaya dole ne su ƙaru har zuwa 0x3F kuma su mirgine zuwa 0x00. Tashar umarni ramp duban tsari don ramp alamu a duk hanyoyi.

F-Tile JESD204C TX da RX IP
Wannan zane example yana ba ku damar saita kowane TX/RX a cikin yanayin simplex ko yanayin duplex.
Saitunan Duplex suna ba da damar nunin ayyukan IP ta amfani da ko dai na ciki ko na waje serial loopback. CSRs a cikin IP ba a inganta su ba don ba da izinin sarrafa IP da lura da matsayi.

F-Tile JESD204C Zane ExampAgogo da Sake saiti

F-Tile JESD204C zane example yana da saitin agogo da sake saitin sigina.

Tebur 13.Zane Exampda Clocks

Alamar Agogo	Hanyar	Bayani
mgmt_clk	Shigarwa	Agogon bambancin LVDS tare da mitar 100 MHz.
refclk_xcvr	Shigarwa	Agogon tunani mai jujjuyawa tare da mitar ƙimar bayanai/factor na 33.
refclk_core	Shigarwa	Agogon tunani mai mahimmanci tare da mitar guda ɗaya kamar refclk_xcvr.
in_sysref	Shigarwa	Alamar SYSREF. Matsakaicin mitar SYSREF shine ƙimar bayanai/(66x32xE).
sysref_out	Fitowa
txlink_clk rxlink_clk	Na ciki	Agogon haɗin TX da RX tare da mitar ƙimar bayanai/66.
txframe_clk rxframe_clk	Na ciki	TX da agogon firam ɗin RX tare da mitar ƙimar bayanai/33 (FCLK_MULP=2) TX da agogon firam ɗin RX tare da mitar ƙimar bayanai/66 (FCLK_MULP=1)
tx_fclk rx_fclk	Na ciki	TX da agogon lokaci na RX tare da mitar ƙimar bayanai/66 (FCLK_MULP=2) Agogon lokaci na TX da RX koyaushe yana da girma (1'b1) lokacin FCLK_MULP=1
spi_SCLK	Fitowa	Agogon ƙimar baud na SPI tare da mitar 20 MHz.

Lokacin da ka loda zane exampshiga cikin na'urar FPGA, wani taron ninit_done na ciki yana tabbatar da cewa JTAG zuwa gadar Avalon Master tana cikin sake saitawa da kuma duk sauran tubalan.

Generator na SYSREF yana da sake saitin sa mai zaman kansa don ƙaddamar da alaƙar da ba ta dace ba don agogon txlink_clk da rxlink_clk. Wannan hanya ta fi dacewa wajen yin koyi da siginar SYSREF daga guntu agogon waje.

Tebur 14. Zane Example Sake saiti

Sake saitin sigina	Hanyar	Bayani
duniya_rst_n	Shigarwa	Maɓallin sake saitin duniya don duk tubalan, ban da JTAG zuwa Avalon Master Bridge.
nit_yi	Na ciki	Fitowa daga Sake saitin Sakin IP don JTAG zuwa Avalon Master Bridge.
edctl_rst_n	Na ciki	An sake saita toshewar ED Control ta JTAG zuwa Avalon Master Bridge. Tashoshin hw_rst da global_rst_n basa sake saita toshewar ED Control.
hw_rst	Na ciki	Sanya da kayan zaki hw_rst ta rubuta zuwa rijistar rst_ctl na ED Control block. mgmt_rst_in_n yana tabbatarwa lokacin da aka tabbatar da hw_rst.
mgmt_rst_in_n	Na ciki	Sake saitin don musanya taswirar ƙwaƙwalwar ajiya na Avalon na IP daban-daban da abubuwan shigar da masu sake saiti:  j20c_reconfig_reset don F-Tile JESD204C IP duplex Native PHY spi_rst_n don SPI master pio_rst_n don matsayin PIO da sarrafawa reset_in0 tashar sake saiti na 0 da 1 Global_rst_n, hw_rst, ko edctl_rst_n tashar jiragen ruwa suna tabbatar da sake saiti akan mgmt_rst_in_n.
sysref_rst_n	Na ciki	Sake saitin SYSREF janareta toshe a cikin ED Control block ta amfani da sake saitin sequencer 0 reset_out2 tashar jiragen ruwa. Mabiyi na sake saitin tashar 0 reset_out2 yana satar da sake saitin idan ainihin PLL ta kulle.
ainihin_pll_rst	Na ciki	Yana sake saita ainihin PLL ta hanyar sake saiti 0 reset_out0 tashar jiragen ruwa. Babban PLL yana sake saitawa lokacin da aka tabbatar da sake saitin mgmt_rst_in_n.
j204c_tx_avs_rst_n	Na ciki	Yana sake saita tsarin F-Tile JESD204C TX Avalon da aka tsara taswirar taswira ta hanyar sake saiti 0. TX Avalon memory-mapped interface yana faɗi lokacin da aka tabbatar da mgmt_rst_in_n.
j204c_rx_avs_rst_n	Na ciki	Yana sake saita tsarin F-Tile JESD204C TX Avalon da aka tsara taswirar taswirar taswirar ta hanyar sake saiti 1. RX Avalon memory-mapped interface interface yana tabbatarwa lokacin da aka tabbatar da mgmt_rst_in_n.
j204c_tx_rst_n	Na ciki	Yana sake saita hanyar haɗin F-Tile JESD204C TX da jigilar kayayyaki a cikin txlink_clk, da txframe_clk, yanki. Sake saitin tashar 0 reset_out5 ta sake saitin tashar j204c_tx_rst_n. Wannan sake saita kayan zaki idan an kulle ainihin PLL, kuma an tabbatar da siginar tx_pma_ready da tx_ready.
j204c_rx_rst_n	Na ciki	Yana sake saita hanyar haɗin F-Tile JESD204C RX da jigilar kayayyaki a cikin, rxlink_clk, da rxframe_clk.

Sake saitin sigina	Hanyar	Bayani
		Sake saitin tashar 1 reset_out4 ta sake saita j204c_rx_rst_n. Wannan sake saita kayan zaki idan an kulle ainihin PLL, kuma ana tabbatar da siginar rx_pma_ready da rx_ready.
j204c_tx_rst_ack_n	Na ciki	Sake saita siginar musafiha tare da j204c_tx_rst_n.
j204c_rx_rst_ack_n	Na ciki	Sake saita siginar musafiha tare da j204c_rx_rst_n.

Hoto na 8. Jadawalin lokaci don Zane Example Sake saiti

F-Tile JESD204C Zane Exampda Sigina

Tebur 15. Sigina na Interface System

Sigina	Hanyar	Bayani
Agogo da Sake saiti
mgmt_clk	Shigarwa	Agogon 100 MHz don sarrafa tsarin.
refclk_xcvr	Shigarwa	Agogon magana don F-tile UX QUAD da Tsarin PLL. Daidai da ƙimar bayanai/fasali na 33.
refclk_core	Shigarwa	Core PLL nuni agogo. Yana aiki da mitar agogo ɗaya kamar refclk_xcvr.
in_sysref	Shigarwa	Siginar SYSREF daga janareta na SYSREF na waje don aiwatar da JESD204C Subclass 1.
sysref_out	Fitowa	Siginar SYSREF don aiwatarwa na JESD204C Subclass 1 wanda na'urar FPGA ta haifar don ƙira exampdalilin farawa kawai.

 

Sigina	Hanyar	Bayani
SPI
spi_SS_n [2:0]	Fitowa	Ƙananan aiki, SPI bawan zaɓi sigina.
spi_SCLK	Fitowa	Serial agogon SPI.
spi_sdio	Shigarwa/fitarwa	Bayanan fitarwa daga maigida zuwa bawa na waje. Bayanan shigarwa daga bawa na waje zuwa maigida.

Sigina	Hanyar	Bayani
Lura:Lokacin Ƙirƙirar 3-Wire SPI Module zaɓin ya kunna.
spi_MISO Lura: Lokacin da ba a kunna zaɓin Module 3-Wire SPI ba.	Shigarwa	Bayanan shigarwa daga bawa na waje zuwa mai kula da SPI.
spi_MOSI Lura: Lokacin da ba a kunna zaɓin Module 3-Wire SPI ba.	Fitowa	Bayanan fitarwa daga SPI master zuwa bawa na waje.

 

Sigina	Hanyar	Bayani
ADC / DAC
tx_serial_data[LINK*L-1:0]	Fitowa	Bambance-banbance bayanan fitarwa na serial mai girma zuwa DAC. An saka agogon a cikin jerin bayanan.
tx_serial_data_n[LINK*L-1:0]
rx_serial_data[LINK*L-1:0]	Shigarwa	Daban-daban bayanan shigarwar serial mai girma daga ADC. Ana dawo da agogon daga rafin bayanai na serial.
rx_serial_data_n[LINK*L-1:0]

 

Sigina	Hanyar	Bayani
Babban Manufar I/O
mai amfani_led[3:0]	Fitowa	Yana nuna matsayi na waɗannan sharuɗɗa masu zuwa: [0]: An yi shirye-shiryen SPI [1]: Kuskuren hanyar haɗin TX [2]: Kuskuren hanyar haɗin RX [3]: Kuskuren mai duba tsari don bayanan kwararar Avalon
mai amfani[3:0]	Shigarwa	Yanayin mai amfani DIP shigarwar sauyawa: [0]: Yana ba da damar dawo da siriyal na ciki [1]: SYSREF mai samar da FPGA [3:2]: Ajiye

 

Sigina	Hanyar	Bayani
Out-of-band (OOB) da Matsayi
rx_patchk_data_error[LINK-1:0]	Fitowa	Lokacin da aka tabbatar da wannan siginar, yana nuna mai duba ƙirar ya gano kuskure.
rx_link_error[LINK-1:0]	Fitowa	Lokacin da aka tabbatar da wannan siginar, yana nuna JESD204C RX IP ya tabbatar da katsewa.
tx_link_error[LINK-1:0]	Fitowa	Lokacin da aka tabbatar da wannan siginar, yana nuna JESD204C TX IP ya tabbatar da katsewa.
emb_lock_out	Fitowa	Lokacin da aka tabbatar da wannan siginar, yana nuna JESD204C RX IP ta sami nasarar kulle EMB.
sh_lock_out	Fitowa	Lokacin da aka tabbatar da wannan siginar, yana nuna JESD204C RX IP sync header an kulle.

 

Sigina	Hanyar	Bayani
Avalon Streaming
rx_avst_valid[LINK-1:0]	Shigarwa	Yana nuna ko mai juyawa sampbayanan da ke cikin Layer ɗin aikace-aikacen yana da inganci ko mara inganci. 0: Bayanai ba su da inganci 1: Data yana aiki
rx_avst_data[(TOTAL_SAMPLE*N)-1:0 ]	Shigarwa	Mai juyawa sample data zuwa aikace-aikace Layer.

F-Tile JESD204C Zane Exampda Gudanar da Rajista

F-Tile JESD204C zane exampYi rijista a cikin ED Control toshe amfani da adireshin byte (32 ragowa).

Tebur 16. Zane Examptaswirar adireshin
Waɗannan 32-bit ED Control block rajista suna cikin yankin mgmt_clk.

Bangaren	Adireshi
Saukewa: F-Tile JESD204C TX	0x000C_0000 – 0x000C_03FF
Saukewa: F-Tile JESD204C RX	0x000D_0000 – 0x000D_03FF
SPI Sarrafa	0x0102_0000 – 0x0102_001F
Gudanar da PIO	0x0102_0020 – 0x0102_002F
Matsayin PIO	0x0102_0040 – 0x0102_004F
Sake saitin Sequencer 0	0x0102_0100 – 0x0102_01FF
Sake saitin Sequencer 1	0x0102_0200 – 0x0102_02FF
Gudanar da ED	0x0102_0400 – 0x0102_04FF
F-Tile JESD204C IP transceiver PHY Reconfig	0x0200_0000 – 0x023F_FFFF

Tebur 17. Nau'in Samun Rijista da Ma'anar
Wannan tebur yana bayyana nau'in samun damar yin rijista don Intel FPGA IPs.

Nau'in Samun shiga	Ma'anarsa
RO/V	karantawa-kawai software (babu tasiri akan rubutu). Ƙimar na iya bambanta.
RW	Software yana karantawa kuma yana mayar da ƙimar bit na yanzu. Software yana rubutawa kuma yana saita bit zuwa ƙimar da ake so.
RW1C	Software yana karantawa kuma yana mayar da ƙimar bit na yanzu. Software yana rubuta 0 kuma ba shi da wani tasiri. Software yana rubuta 1 kuma yana share bit zuwa 0 idan hardware an saita bit zuwa 1. Hardware yana saita bit zuwa 1. Bayyanar software yana da fifiko mafi girma fiye da saitin kayan masarufi.

Tebur 18. Taswirar Adireshin Kula da ED

Kashewa	Sunan Rajista
0 x00	rst_ctl
0 x04	farko_sts0
ci gaba…

Kashewa	Sunan Rajista
0 x10	rst_sts_detected0
0 x40	sysref_ctl
0 x44	sysref_sts
0 x80	tst_ctl
0x8c ku	tst_err0

Table 19. ED Control Block Control da Status Register

Byte Kashewa	Yi rijista	Suna	Shiga	Sake saiti	Bayani
0 x00	rst_ctl	farkon_tabbatar	RW	0 x0	Sake saita sarrafawa. [0]: Rubuta 1 don tabbatar da sake saiti. (hw_rst) Rubuta 0 don sake saiti. [31:1]: Ajiye.
0 x04	farko_sts0	Matsayin farko	RO/V	0 x0	Sake saita matsayi. [0]: Matsayin kulle Core PLL. [31:1]: Ajiye.
0 x10	rst_sts_dete cted0	farkon_sts_set	RW1C	0 x0	Matsayin gano gefen SYSREF don janareta na SYSREF na ciki ko na waje. [0]: Ƙimar 1 yana nuna an gano gefen tashin SYSREF don aiki na subclass 1. Software na iya rubuta 1 don share wannan bit don ba da damar sabon gano gefen SYSREF. [31:1]: Ajiye.
0 x40	sysref_ctl	sysref_contr ol	RW	Duplex data hanya Saukewa: 0x00080	SYSREF iko. Koma zuwa Tebur 10 shafi na 17 don ƙarin bayani game da amfani da wannan rijistar.
				Lokaci -lokaci:	Lura: Ƙimar sake saitin ya dogara
				0 x00081	nau'in SYSREF da F-Tile
				Gapped- lokaci-lokaci:	JESD204C Saitunan sigar bayanan hanyar IP.
				0 x00082
				TX ko RX bayanai
				hanya
				-Aya daga cikin harbi:
				0 x00000
				Lokaci -lokaci:
				0 x00001
				Bata-
				lokaci-lokaci:
				0 x00002
0 x44	sysref_sts	sysref_statu s	RO/V	0 x0	Matsayin SYSREF. Wannan rijistar ta ƙunshi sabon lokacin SYSREF da saitunan sake zagayowar aiki na janareta na SYSREF na ciki. Koma zuwa Tebur 9 shafi na 16 don ƙimar shari'a na lokacin SYSREF da sake zagayowar aiki.
ci gaba…

Byte Kashewa	Yi rijista	Suna	Shiga	Sake saiti	Bayani
					[8:0]: Lokacin SYSREF. Lokacin da darajar ta kasance 0xFF, da Lokacin SYSREF = 255 Lokacin da darajar idan 0x00, lokacin SYSREF = 256. [17:9]: SYSREF duty cycle. [31:18]: Ajiye.
0 x80	tst_ctl	tst_control	RW	0 x0	Gwajin gwaji. Yi amfani da wannan rijistar don ba da damar samfuran gwaji daban-daban don janareta da abin dubawa. [1:0] = Filin da aka keɓe [2] = ramp_gwajin_ctl 1'b0 = Yana ba da damar janareta na ƙirar PRBS da mai duba 1'b1 = Yana ba da damar ramp janareta da abin dubawa [31:3]: Ajiye.
0x8c ku	tst_err0	tst_kuskure	RW1C	0 x0	Tutar kuskure don Link 0. Lokacin da bit ya kasance 1'b1, yana nuna kuskure ya faru. Ya kamata ku warware kuskuren kafin rubuta 1'b1 zuwa kowane bit don share tutar kuskure. [0] = Kuskuren mai duba tsari [1] = tx_link_error [2] = rx_link_error [3] = Kuskuren duba tsarin umarni [31:4]: Ajiye.

Tarihin Bita na Takardu don F-Tile JESD204C Intel FPGA IP Design ExampJagorar Mai Amfani

Sigar Takardu	Intel Quartus Prime Version	Sigar IP	Canje-canje
2021.10.11	21.3	1.0.0	Sakin farko.

Takardu / Albarkatu

intel F-Tile JESD204C Intel FPGA IP Design Example [pdf] Jagorar mai amfani F-Tile JESD204C Intel FPGA IP Design Example, F-Tile JESD204C, Intel FPGA IP Design Example, IP Design Example, Design Example

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