F-Tile JESD204C Intel FPGA IP Design Example

Malunga ne-F-Tile JESD204C Intel® FPGA IP Design Example Isikhokelo somsebenzisi

Esi sikhokelo somsebenzisi sibonelela ngeempawu, izikhokelo zokusetyenziswa, kunye nenkcazo eneenkcukacha malunga noyilo examples ye-F-Tile JESD204C Intel® FPGA IP usebenzisa izixhobo ze-Intel Agilex™.

Abaphulaphuli ekujoliswe kubo

Olu xwebhu lulungiselelwe:

• Umyili woyilo ukwenza ukhetho lwe-IP ngexesha lenqanaba lenqanaba loyilo loyilo lwenqanaba
• Abaqulunqi be-Hardware xa bedibanisa i-IP kuyilo lwenqanaba lenkqubo yabo
• Iinjineli zokuqinisekisa ngexesha lokulinganisa kwinqanaba lenkqubo kunye nesigaba sokuqinisekiswa kwehardware

Amaxwebhu anxulumeneyo
Le theyibhile ilandelayo idwelisa amanye amaxwebhu ereferensi anxulumene ne-F-Tile JESD204C Intel FPGA IP.

Uluhlu 1. Amaxwebhu anxulumeneyo

Isalathiso	Inkcazo
F-Tile JESD204C Intel FPGA IP User Guide	Ibonelela ngolwazi malunga ne-F-Tile JESD204C Intel FPGA IP.
I-F-Tile JESD204C Intel FPGA IP amanqaku okukhutshwa	Udwelisa utshintsho olwenzelwe i-F-Tile JESD204C F-Tile JESD204C kukhupho oluthile.
Iphepha leDatha leSixhobo se-Intel Agilex	Olu xwebhu luchaza iimpawu zombane, iimpawu zokutshintsha, iinkcukacha zokucwangciswa, kunye nexesha lezixhobo ze-Intel Agilex.

Izifinyezo kunye noluhlu lweenkcazelo

Uluhlu 2. Uluhlu lwesifinyezo

Isifinyezo	Ukwandiswa
I-LEMC	Ikloko eyandisiweyo yeMultiblock yasekuhlaleni
FC	Isantya sewotshi yesakhelo
ADC	I-Analog kwi-Digital Converter
I-DAC	Digital ukuba Analog Converter
I-DSP	Digital Signal Processor
TX	Isidluliseli
RX	Umamkeli

Isifinyezo	Ukwandiswa
DLL	Umaleko wekhonkco ledatha
CSR	Ulawulo kunye nerejista yobume
I-CRU	Ikloko kunye neYunithi yokuSeta kwakhona
ISR	Ukuphazamisa inkqubo yeNkonzo
FIFO	Okokuqala-In-Okokuqala-Ngaphandle
I-SERDES	I-serializer Deserializer
ECC	Ikhowudi yokulungisa impazamo
I-FEC	Phambili ukulungiswa kwempazamo
I-SERR	Ukufunyanwa kwempazamo enye (kwi-ECC, iyalungiswa)
I-DERR	Ukufunyanwa kwemposiso ephindwe kabini (kwi-ECC, yingozi)
PRBS	I-Pseudorandom yokulandelelana kokubini
IMAC	UMlawuli woFikelelo kwiMedia. I-MAC ibandakanya i-protocol sublayer, umaleko wezothutho, kunye ne-data link layer.
PHY	Umaleko woMzimba. I-PHY ibandakanya umaleko womzimba, i-SERDES, abaqhubi, abamkeli kunye ne-CDR.
PCS	Ulwaleko oluphantsi lweKhowudi yePhysical
PMA	I-Physical Medium Attachment
RBD	Ukulibaziseka kwe-RX Buffer
UI	Isithuba seYunithi = ubude beserial bit
Ukubala kwe-RBD	I-RX Buffer Libazisa ukufika kwendlela yamva nje
Ukulinganisa kwe-RBD	I-RX Buffer Libazise ithuba lokukhulula
SH	Ngqamanisa isihloko
TL	Umaleko wezothutho
I-EMIB	Ibhulorho eFakelwe i-Multi-die Interconnect

Itheyibhile 3. Uluhlu Lweenkcazelo

Ixesha	Inkcazo
Isixhobo sokuguqulela	ADC okanye DAC converter
Isixhobo esinengqondo	FPGA okanye ASIC
Octet	Iqela lamasuntswana asi-8, elisebenza njengegalelo kwi-encoder ye-64/66 kunye nemveliso evela kwidikhowuda.
Nibble	Iseti yeebhithi ezi-4 ezisisiseko sokusebenza kweenkcukacha zeJESD204C
Vimba	Isimboli se-66-bit esiveliswe yi-64/66 ye-encoding scheme
Ireyithi yomgca	Ireyithi esebenzayo yedatha yekhonkco le-serial Ireyithi yeLane Line = (Mx Sx N'x 66/64 x FC) / L
Ikloko yekhonkco	Ikloko yekhonkco = Ireyithi yeLane Line/66.
Isakhelo	Iseti yee-octet ezilandelelanayo apho indawo ye-octet nganye inokuchongwa ngokubhekisele kwisignali yokulungelelanisa isakhelo.
Ikloko yesakhelo	Iwotshi yesixokelelwano ebaleka ngesantya sesakhelo, ekufuneka sibe yi-1x kunye ne-2x yewotshi yekhonkco.

Ixesha	Inkcazo
Sampngaphantsi kwiwotshi nganye yesakhelo	Sampngaphantsi ngewotshi nganye, iyonke sampkwikloko yesakhelo sesixhobo somguquleli.
I-LEMC	Ikloko yangaphakathi esetyenziselwa ukulungelelanisa umda we-multiblock eyandisiweyo phakathi kweendlela kunye neereferensi zangaphandle (SYSREF okanye i-Subclass 1).
Udidi oluphantsi 0	Akukho nkxaso ye-deantistic latency. Idatha kufuneka ikhutshwe ngokukhawuleza kwindlela ukuya kwindlela yedeskew kumamkeli.
Udidi oluphantsi 1	I-Deterministic latency usebenzisa i-SYSREF.
Multipoint Link	I-Inter-device links ene-2 ​​okanye ngaphezulu izixhobo zokuguqulela.
64B/66B Ufakelo lweekhowudi	Ikhowudi yomgca ebonisa i-64-bit data ukuya kwi-bits engama-66 ukwenza ibhloko. Ubume bedatha yesiseko yibhloko eqala nge-2-bit sync header.

Uluhlu 4. Iimpawu

Ixesha	Inkcazo
L	Inani leendlela kwisixhobo sokuguqula ngasinye
M	Inani labaguquli ngesixhobo ngasinye
F	Inani lee-octets kwifreyimu nganye kwindlela enye
S	Inani le-sampLes isasazwe ngokwesiguquli esinye kumjikelo wesakhelo
N	Isisombululo somguquleli
N'	Lilonke inani lamasuntswana ngokwe sample kwifomati yedatha yomsebenzisi
CS	Inani lamasuntswana olawulo kwinguquko nganye sample
CF	Inani lamagama olawulo ngokwesakhelo sewotshi kwikhonkco ngalinye
HD	Uxinaniso oluphezulu lwefomathi yedatha yomsebenzisi
E	Inani leebhloko ezininzi kwibhloko eyandisiweyo

F-Tile JESD204C Intel FPGA IP Design Example Quick Start Guide

I-F-Tile JESD204C Intel FPGA IP yoyilo exampI-les yezixhobo ze-Intel Agilex zine-testbench yokulinganisa kunye noyilo lwe-hardware oluxhasa ukuhlanganisa kunye novavanyo lwe-hardware.
Unokwenza i-F-Tile JESD204C yoyilo exampngaphantsi kwekhathalogu ye-IP kwi-software ye-Intel Quartus® Prime Pro Edition.

Umfanekiso 1. Uphuhliso Stages yoYilo Eksample

Uyilo Eksample Block Diagram

Umzobo 2. F-Tile JESD204C Design Example High-level Block Diagram

Uyilo example iqulathe ezi modyuli zilandelayo:

• Inkqubo yoMyili weQonga
  • F-Tile JESD204C Intel FPGA IP
  • JTAG ukuya kwibhulorho eyi-Avalon Master
  • I-Parallel I/O (PIO) isilawuli
  • I-Serial Port Interface (SPI)-imodyuli enkulu- IOPLL
  • SYSREF generator
  • Example Uyilo (ED) Ulawulo lwe-CSR
  • Seta kwakhona izilandeleli
• Inkqubo yePLL
• Iphethini yejenereyitha
• Umkhangeli wepateni

Uluhlu 5. Uyilo Eksample Iimodyuli

Amacandelo	Inkcazo
Inkqubo yoMyili weQonga	Inkqubo yoMyili wePlatform iqinisekisa indlela yedatha ye-F-Tile JESD204C IP kunye neeperipherals ezixhasayo.
F-Tile JESD204C Intel FPGA IP	Esi sixokelelwano soMyili wePlatform siqulathe i-TX kunye ne-RX F-Tile JESD204C IPs eqiniswe kunye ne-duplex PHY.
JTAG ukuya kwibhulorho eyi-Avalon Master	Le bhulorho ibonelela ngofikelelo lwenkqubo yekhonsoli kwi-IP ebhalwe ngememori kuyilo ngeJTAG ujongano.
I-Parallel I/O (PIO) isilawuli	Lo mlawuli ubonelela ngenkumbulo-maphu ujongano sampling kunye nokuqhuba injongo jikelele I/O kumazibuko.
SPI inkosi	Le modyuli iphethe ukudluliselwa kweserial yedatha yoqwalaselo kujongano lweSPI kwisiphelo somguquli.
SYSREF generator	I-generator ye-SYSREF isebenzisa ikloko yekhonkco njengewotshi yereferensi kwaye ivelise i-SYSREF pulses ye-F-Tile JESD204C IP. Phawula: Lo mzekelo woyiloample isebenzisa i-SYSREF generator ukubonisa i-duplex ye-F-Tile JESD204C yokuqalisa ikhonkco le-IP. Kwi-F-Tile JESD204C subclass 1 inkqubo yenkqubo yosetyenziso, kufuneka uvelise i-SYSREF kumthombo ofanayo njengewotshi yesixhobo.
IOPLL	Lo mzekelo woyiloample isebenzisa i-IOPLL ukuvelisa iwotshi yomsebenzisi yokuhambisa idatha kwi-F-Tile JESD204C IP.
Ulawulo lwe-ED CSR	Le modyuli ibonelela nge-SYSREF yolawulo lobhaqo kunye nobume, kunye nolawulo lwepateni yovavanyo kunye nobume.
Seta kwakhona izilandeleli	Lo mzekelo woyiloample iqulathe 2 ukusetha ngokutsha abalandelelanisi: Ukuseta kwakhona ulandelelwano 0-Iphatha ukusetha kwakhona kwi-TX/RX Avalon® isizinda sokusakaza, i-Avalon memory-mapped domain, i-core PLL, i-TX PHY, i-TX core, kunye ne-SYSREF generator. Seta kwakhona ulandelelwano 1-Iphatha ukuseta kwakhona kwi-RX PHY kunye ne-RX core.
Inkqubo yePLL	Umthombo wewotshi ephambili ye-F-tile enzima ye-IP kunye ne-EMIB yokuwela.
Iphethini yejenereyitha	Umenzi wepateni uvelisa i-PRBS okanye i-ramp ipateni.
Umkhangeli wepateni	Umkhangeli wepateni uqinisekisa i-PRBS okanye i-ramp ipateni efunyenweyo, kwaye iflegi yempazamo xa ifumana ukungangqinelani kwedatha sample.

IiMfuno zeSoftware

Intel isebenzisa le software ilandelayo ukuvavanya uyilo exampngaphantsi kwindlela yeLinux:

• Intel Quartus Prime Pro Edition software
• Questa*/ModelSim* okanye VCS*/VCS MX isilingisi

Ukuvelisa uYilo

Ukuvelisa i-design example isuka kumhleli weparameter ye IP:

1. Yenza iprojekthi ejolise kwi-Intel Agilex F-tile isixhobo sosapho kwaye ukhethe isixhobo esifunwayo.
2. Kwikhathalogu ye-IP, Izixhobo ➤ Ikhathalogu ye-IP, khetha i-F-Tile JESD204C Intel FPGA IP.
3. Chaza igama lomgangatho ophezulu kunye nefolda yokwahluka kwe-IP yakho. Cofa u-Kulungile. Umhleli weparameter wongeza inqanaba eliphezulu .ip file kwiprojekthi yangoku ngokuzenzekelayo. Ukuba uyacelwa ukuba wongeze ngesandla i.ip file kwiprojekthi, cofa iProjekthi ➤ Yongeza/ Susa Files kwiProjekthi yokongeza i file.
4. Ngaphantsi kwe-Example Yila isithuba, khankanya uyilo example parameters njengoko kuchaziwe kuYilo Eksample Parameters.
5. Cofa uVelisa Example Design.

Isoftware yenza lonke uyilo files kuluhlu lwabalawuli. Ezi files ziyafuneka ukuqhuba ukulinganisa kunye nokudibanisa.

Uyilo Eksample Parameters
Umhleli wepharamitha ye-F-Tile JESD204C Intel FPGA IP iquka iExample Yila isithuba sokuba uchaze iparameters ezithile phambi kokwenza uyilo example.

Uluhlu loku-6. Iiparamitha kwiEksample Tab yoYilo

Ipharamitha	Iinketho	Inkcazo
Khetha uyilo	Ulawulo lweConsole yeNkqubo Akukho nanye	Khetha isixokelelwano solawulo lokufikelela kuyilo example data indlela ngapha kwenkqubo console.
Ukulinganisa	Layita icima	Vula i-IP ukuvelisa okuyimfuneko files yokulinganisa uyilo example.
Ukudibanisa	Layita icima	Vula i-IP ukuvelisa okuyimfuneko files for Intel Quartus Prime ukuhlanganiswa kunye nomboniso hardware.
ifomathi ye-HDL (ukulinganisa)	Verilog VDHL	Khetha ifomathi ye-HDL ye-RTL files yokulinganisa.
ifomathi ye-HDL (yeyodibaniso)	Verilog kuphela	Khetha ifomathi ye-HDL ye-RTL files yokudibanisa.

Ipharamitha	Iinketho	Inkcazo
Yenza imodyuli ye-SPI ye-3-ingcingo	Layita icima	Layita ukuze uvule i-3-wire SPI interface endaweni ye-4-ingcingo.
Imowudi yeSysref	Ishot enye Ngamaxesha athile I-Gapped periodic	Khetha ukuba uyafuna na ukuba ulungelelwaniso lwe-SYSREF lube yimowudi ye-pulse-shot-shot, ngamaxesha, okanye i-gapped periodic, ngokusekelwe kwiimfuno zakho zoyilo kunye nokuguquguquka kwexesha. I-One-shot-Khetha olu khetho ukwenza i-SYSREF ibe yimowudi ye-pulse-shot enye. I-sysref_ctrl[17] ixabiso lebhithi yerejista ngu-0. Emva kwe-F-Tile JESD204C IP yokusetha ngokutsha iideserts, tshintsha ixabiso lerejista ye-sysref_ctrl[17] ukusuka ku-0 ukuya ku-1, emva koko ukuya ku-0, kwi-SYSREF yokudubula okunye. I-Periodic—SYSREF kwimowudi ye periodic ine-50:50 yomjikelo womsebenzi. Ixesha le-SYSREF yi-E*SYSREF_MULP. I-Gapped periodic-SYSREF inomjikelo womsebenzi ocwangcisekileyo we-granularity ye-1 ikhonkco lomjikelo wewotshi. Ixesha le-SYSREF yi-E*SYSREF_MULP. Ukulungiselela ukusetwa komjikelo ongaphandle koluhlu, ibhloko yokuvelisa i-SYSREF kufuneka ithintele ngokuzenzekelayo i-50:50 yomjikelo womsebenzi. Jonga kwi I-SYSREF Ijenereyitha icandelo lolwazi oluninzi malunga ne-SYSREF ixesha.
Khetha ibhodi	Akukho nanye	Khetha ibhodi yoyilo example. Akukho-Olu khetho alubandakanyi imiba yehardware yoyilo example. Zonke izabelo ze-pin ziyakusetwa kwizikhonkwane zenyani.
Ipatheni yoVavanyo	I-PRBS-7 I-PRBS-9 I-PRBS-15 I-PRBS-23 Ramp	Khetha ipateni yejenereyitha kunye nepateni yokuhlola umkhangeli. iPattern Generator-JESD204C ixhasa i-PRBS iphethini yejenereyitha ngokwedatha sample. Oku kuthetha ukuba ububanzi bedatha lukhetho lwe-N + CS. PRBS iphethini generator kunye umhloli ziluncedo ekudaleni data sample stimulus yokuvavanya kwaye ayihambelani nemowudi yovavanyo ye-PRBS kwi-ADC/DAC converter. Ramp I-Pattern Generator-JESD204C umaleko wekhonkco usebenza ngesiqhelo kodwa uthutho kamva luvaliwe kwaye igalelo elisuka kwisilungisi alihoywa. Umzila ngamnye usasaza umsinga we-octet ofanayo onyuka ukusuka ku-0x00 ukuya ku-0xFF kwaye uphinda-phinda. Ramp Uvavanyo lwepateni luvulwa nge-prbs_test_ctl. I-PRBS Pattern Checker-JESD204C PRBS scrambler iyazilungelelanisa kwaye ilindeleke ukuba xa undoqo we-IP ukwazi ukucacisa ikhonkco, imbewu ekralayo sele ilungelelanisiwe. I-PRBS yokukrazula imbewu iyakuthatha ii-octets ezisi-8 ukuziqalela ngokwakho. Ramp Ipateni yokuHlola-JESD204C ukukrazula kukuzilungelelanisa kwaye kulindelekile ukuba xa undoqo we-IP ukwazi ukucacisa ikhonkco, imbewu ekhuhlazayo sele ilungelelanisiwe. I-octet yokuqala esebenzayo ilayishwe njenge-ramp ixabiso lokuqala. Idatha elandelayo kufuneka inyuke iye kuthi ga kwi-0xFF kwaye iqengqeleke iye ku-0x00. Ramp Umkhangeli wepateni kufuneka ujonge iipateni ezifanayo kuzo zonke iindlela.
Vula uthotho lwangaphakathi lweloopback	Layita icima	Khetha uthotho lwangaphakathi loopback.
Vula Umjelo woMyalelo	Layita icima	Khetha ipateni yesitishi somyalelo.

Ulwakhiwo lukavimba weefayili
Uyilo lwe-F-Tile JESD204C example abalawuli ziqulathe ezenziwe files yoyilo examples.

Umzobo 3. Ulwakhiwo loluhlu lwe-F-Tile JESD204C Intel Agilex Design Example

Uluhlu 7. Uluhlu Files

Iifolda	Files
ed/rtl	tx j204c_f_tx_ip.qsys j204c_f tx_ss.qsys altera_s10_user_rst_clkgate_0.ip j204c f_se_outbuf_1bit.ip
ukulinganisa/umcebisi	iimodelim_sim.tcl tb_top_waveform.do
Ukulinganisa/ukulinganisa	vcs vcs_sim.sh tb_top_wave_ed.do vcsmx vcsmx_sim.sh tb_top_wave_ed.do

Ukulinganisa i-Design Example Testbench

Uyilo example testbench ilinganisa uyilo lwakho olwenziweyo.

Umzobo 4. Inkqubo

Ukulinganisa uyilo, yenza la manyathelo alandelayo:

1. Guqula uvimba weefayili osebenzayo ubeample_design_directory>/ukulinganisa/ .
2. Kumgca womyalelo, sebenzisa iskripthi sokulinganisa. Itheyibhile engezantsi ibonisa imiyalelo yokusebenzisa izilingisi ezixhaswayo.

Isifanisi	Umyalelo
Questa/ModelSim	vsim -yenza iimodelim_sim.tcl
	vsim -c -do modelsim_sim.tcl (ngaphandle kwe-Questa/ ModelSim GUI)
VCS	sh vcs_sim.sh
VCS MX	sh vcsmx_sim.sh

Ukulinganisa kugqiba ngemiyalezo ebonisa ukuba ingaba umqhubi uphumelele okanye hayi.

Umzobo 5. Ukulinganisa okuyimpumelelo
Eli nani libonisa umyalezo oyimpumelelo wokulinganisa we-VCS simulator.

Ukuqulunqa i-Design Example

Ukuqulunqa umdibaniso-kuphela exampkwiprojekthi, landela la manyathelo:

1. Qinisekisa uyilo lokuhlanganisa exampisizukulwana sigqityiwe.
2. Kwisoftware ye-Intel Quartus Prime Pro Edition, vula iprojekthi ye-Intel Quartus Prime Pro Editionample_ design_ directory>/ed/quartus.
3. Kwi-Processing menu, cofa Qala ukuHlanganisa.

Inkcazelo eneenkcukacha ye-F-Tile JESD204C yoYilo Example

Uyilo lwe-F-Tile JESD204C example ibonisa umsebenzi wokusasazwa kwedatha usebenzisa imowudi yeloopback.
Ungakhankanya useto lweparameters ozikhethileyo kwaye uvelise uyilo example.
Uyilo example ifumaneka kuphela kwimowudi ephindwe kabini kuzo zombini iBase kunye nePHY eyahlukileyo. Unokukhetha iSiseko kuphela okanye i-PHY kuphela eyahlukileyo kodwa i-IP iyakuvelisa uyilo example kuzo zombini iSiseko kunye ne-PHY.

Phawula:  Olunye ulungelelwaniso oluphezulu lwezinga ledatha lunokusilela ekubekeni ixesha. Ukunqanda ukusilela kwexesha, cinga ngokukhankanya ixabiso elisezantsi lesakhelo sewotshi yophinda-phindo (FCLK_MULP) ixabiso kwiLuqwalaselo ithebhu ye-F-Tile JESD204C Intel FPGA IP ipharamitha yomhleli.

Amacandelo eNkqubo

Uyilo lwe-F-Tile JESD204C example ibonelela ngokuqukuqela kolawulo olusekwe kwisoftware esebenzisa iyunithi yolawulo olunzima kunye okanye ngaphandle kwenkxaso yenkqubo yekhonsoli.

Uyilo example yenza ikhonkco elizenzekelayo phezulu kwiimowudi zangaphakathi nezangaphandle zeluphu emva.

JTAG ukuya eAvalon Master Bridge
Inkqubo kaJTAG ukuya kwi-Avalon Master Bridge ibonelela ngonxibelelwano phakathi kwenkqubo yenginginya ukufikelela kwimaphu yenkumbulo ye-F-Tile JESD204C IP kunye nolawulo lweperipheral ye-IP kunye neerejista zobume nge-J.TAG ujongano.

Umzobo 6. Inkqubo ene-JTAG ukuya kwiAvalon Master Bridge Core

Phawula:  Iwotshi yenkqubo kufuneka ibe yi-2X ubuncinane ngokukhawuleza kune-JTAG iwotshi. Iwotshi yenkqubo ngu mgmt_clk (100MHz) koluyilo example.

I-Parallel I/O (PIO) Ingundoqo
I-parallel input/output (PIO) ingundoqo kunye ne-Avalon interface inika ujongano lwenkumbulo-maphu phakathi kwe-Avalon memory-mapped izibuko lekhoboka kunye nenjongo jikelele I/O izibuko. Amazibuko e-I/O aqhagamshela nokuba kwi-chip logic yomsebenzisi, okanye kwi-I/O izikhonkwane eziqhagamshela izixhobo ezingaphandle kwiFPGA.

Umzobo 7. I-PIO Core eneZibuko zokuNgena, iZibuko zokuPhuma, kunye neNkxaso ye-IRQ
Ngokungagqibekanga, icandelo loMyili wePlatform likhubaza i-Interrupt Service Line (IRQ).

Amazibuko e-PIO I/O anikezelwe kwinqanaba eliphezulu le-HDL file (io_ ubume bamazibuko ongeniso, io_ ulawulo lwamazibuko emveliso).

Itheyibhile engezantsi ichaza uxhulumaniso lwesignali yesimo kunye nolawulo lwezibuko ze-I / O kwi-DIP yokutshintsha kunye ne-LED kwikhithi yophuhliso.

Itheyibhile 8. PIO Core I/O Ports

Izibuko	Kancinci	Umqondiso
Ngaphandle_kwizibuko	0	USER_LED SPI inkqubo yenziwe
	31:1	Igciniwe
Kwi_kwizibuko	0	USER_DIP yangaphakathi yothotho loopback yenza Cima = 1 Kwi = 0
	1	USER_DIP I-FPGA eyenziwe yi-SYSREF yenza Cima = 1 Kwi = 0
	31:2	Igciniwe.

SPI Master
Imodyuli eyintloko yeSPI yinxalenye yoMyili weQonga elisemgangathweni kwithala leencwadi elisemgangathweni leCatalog ye-IP. Le modyuli isebenzisa umthetho olandelwayo weSPI ukwenza lula uqwalaselo lwabaguquli bangaphandle (ngokomzekeloample, ADC, DAC, kunye neejenereyitha iwotshi yangaphandle) ngokusebenzisa isithuba irejista ecwangcisiweyo ngaphakathi kwezi zixhobo.

Inkosi ye-SPI inojongano lwenkumbulo ye-Avalon edibanisa kwi-Avalon master (JTAG ukuya eAvalon master bridge) ngeAvalon memory-mapped interconnect. I-SPI master ifumana imiyalelo yoqwalaselo kwi-Avalon master.

Imodyuli eyintloko yeSPI ilawula ukuya kuthi ga kwi-32 yamakhoboka eSPI azimeleyo. Izinga le-baud ye-SCLK iqwalaselwe kwi-20 MHz (yahlulahlulwa nge-5).
Le modyuli iqwalaselwe kujongano lwe-4-wire, 24-bit ububanzi. Ukuba i-Gererate 3-Wire SPI Module ikhethiwe, imodyuli eyongezelelweyo ifakwe ukuguqula i-4-wire output ye-SPI master ukuya kwi-3-wire.

IOPLL
I-IOPLL yenza iwotshi efunekayo ukwenza isakhelo_clk kunye nekhonkco_clk. Iwotshi yereferensi kwi-PLL iyalungiseka kodwa ilinganiselwe kumyinge wedatha / into engama-33.

• Kuyilo example exhasa izinga ledatha ye-24.33024 Gbps, ireyithi yewotshi yesakhelo_clk kunye ne-link_clk yi-368.64 MHz.
• Kuyilo example exhasa izinga ledatha ye-32 Gbps, ireyithi yewotshi yesakhelo_clk kunye ne-link_clk yi-484.848 MHz.

Ijenereyitha yeSYSREF
I-SYSREF luphawu olubalulekileyo lwexesha lokuguqula idatha kunye ne-F-Tile JESD204C interface.

I SYSREF generator kuyilo exampI-le isetyenziselwa i-duplex ye-JESD204C IP yekhonkco lokumisela injongo yokubonisa kuphela. Kwinqanaba lenkqubo ye-JESD204C subclass 1, kufuneka uvelise i-SYSREF kumthombo ofanayo njengewotshi yesixhobo.

Kwi-F-Tile JESD204C IP, i-SYSREF multiplier (SYSREF_MULP) yerejista yolawulo ye-SYSREF ichaza ixesha le-SYSREF, eliyi-n-integer multiple of E parameter.

Kufuneka uqinisekise E*SYSREF_MULP ≤16. Umzekeloample, ukuba E=1, ukusetwa okusemthethweni kwe-SYSREF_MULP kufuneka kube ngaphakathi kwe-1–16, kwaye ukuba E=3, useto olusemthethweni lwe-SYSREF_MULP kufuneka lube phakathi kwe-1–5.

Phawula:  Ukuba umisela i-out-of-range SYSREF_MULP, i-SYSREF generator iya kulungisa ukusetwa ku-SYSREF_MULP=1.
Ungakhetha ukuba uyalufuna na uhlobo lwe SYSREF ibe yipulse-shot enye, ngamaxesha, okanye isithuba sexesha nge Ex.ample Yila ithebhu kwi-F-Tile JESD204C Intel FPGA IP ipharamitha yomhleli.

Uluhlu loku-9. Examples yePeriodic kunye neGapped Periodic SYSREF Counter

E	SYSREF_MULP	IXESHA LE-SYSREF (E*SYSREF_MULP* 32)	Isekile yomsebenzi	Inkcazo
1	1	32	1..31 (Kunokucwangciswa)	IGapped Periodic
1	1	32	16 (Zilungisiwe)	Ngamaxesha athile
1	2	64	1..63 (Kunokucwangciswa)	IGapped Periodic
1	2	64	32 (Zilungisiwe)	Ngamaxesha athile
1	16	512	1..511 (Kunokucwangciswa)	IGapped Periodic
1	16	512	256 (Zilungisiwe)	Ngamaxesha athile
2	3	19	1..191 (Kunokucwangciswa)	IGapped Periodic
2	3	192	96 (Zilungisiwe)	Ngamaxesha athile
2	8	512	1..511 (Kunokucwangciswa)	IGapped Periodic
2	8	512	256 (Zilungisiwe)	Ngamaxesha athile
2	9 (Akukho mthethweni)	64	32 (Zilungisiwe)	IGapped Periodic
2	9 (Akukho mthethweni)	64	32 (Zilungisiwe)	Ngamaxesha athile

 

Uluhlu 10. Iirejista zoLawulo lweSYSREF
Ungaqwalasela ngamandla iirejista zolawulo ze SYSREF ukuba isicwangciso serejista sahlukile kunocwangciso oluxelileyo xa usenza uyilo ex.ample. Qwalasela iirejista ze-SYSREF phambi kokuba i-F-Tile JESD204C Intel FPGA IP iphelelwe lixesha. Ukuba ukhetha i-SYSREF yangaphandle generator nge
sysref_ctrl[7] irejista kancinane, ungazihoyi izicwangciso zodidi lweSYSREF, umphindi, umjikelo womsebenzi kunye nesigaba.

Amasuntswana	Ixabiso eliMiselweyo	Inkcazo
sysref_ctrl[1:0]	2'b00: One-shot 2'b01: Ngamaxesha athile I-2'b10: I-Gapped periodic	Uhlobo lwe-SYSREF. Ixabiso elingagqibekanga lixhomekeke kulungiselelo lwemo ye SYSREF kwi Example Design ithebhu kwi-F-Tile JESD204C Intel FPGA IP ipharamitha yomhleli.
sysref_ctrl[6:2]	5'b00001	Isiphindaphindi se-SYSREF. Lo mmandla we-SYSREF_MULP uyasebenza kuhlobo lwe-SYSREF lwexesha kunye ne-gapped-periodic. Kufuneka uqwalasele ixabiso lokuphindaphinda ukuze uqinisekise ukuba ixabiso le-E*SYSREF_MULP liphakathi kwe-1 ukuya kwe-16 ngaphambi kokuba i-F-Tile JESD204C IP iphelelwe lixesha. Ukuba ixabiso le-E*SYSREF_MULP lingaphandle kolu luhlu, ixabiso lophinda-phindi liyashiyeka ukuya ku-5'b00001.
sysref_ctrl[7]	I-Duplex yedatapath: 1'b1 I-Simplex TX okanye i-RX yedatha yedatha: 1'b0	SYSREF khetha. Ixabiso elingagqibekanga lixhomekeke kwisicwangciso sendlela yedatha kwiExample Yila ithebhu kwi-F-Tile JESD204C Intel FPGA IP ipharamitha yomhleli. 0: Simplex TX okanye RX (SYSREF yangaphandle) 1: I-Duplex (Yangaphakathi SYSREF)
sysref_ctrl[16:8]	9'h0	Umjikelo womsebenzi we-SYSREF xa uhlobo lwe-SYSREF lusenziwa ngamaxesha athile okanye lunesithuba sexesha. Kufuneka uqwalasele umjikelo womsebenzi phambi kokuba i-F-Tile JESD204C IP iphelelwe kusetwa ngokutsha. Elona xabiso liphezulu = (E*SYSREF_MULP*32)-1 Kuba example: 50% umjikelo womsebenzi = (E*SYSREF_MULP*32)/2 Umjikelo womsebenzi awugqibekanga ukuya kuma-50% ukuba awuqwalaseli le ndawo yerejista, okanye ukuba uqwalasela indawo yokubhalisa ku-0 okanye ngaphezulu kwexabiso eliphezulu elivunyelweyo.
sysref_ctrl[17]	1'b0	Ulawulo lwezandla xa uhlobo lwe-SYSREF ludubula olunye. Bhala i-1 ukuseta uphawu lwe-SYSREF phezulu. Bhala i-0 ukuseta isignali ye-SYSREF ibe phantsi. Kufuneka ubhale u-1 emva koko u-0 ukwenza i-SYSREF pulse kwimowudi yokudutyulwa enye.
sysref_ctrl[31:18]	22'h0	Igciniwe.

Seta kwakhona izilandelelanisi
Lo mzekelo woyiloample iqulathe abalandelelanisi ababini:

• Ukuseta kwakhona ulandelelwano 0-Iphatha ukusetha kwakhona kwi-TX/RX Avalon yokusakaza i-domain, i-Avalon memory-mapped domain, i-core PLL, i-TX PHY, i-TX core, kunye ne-SYSREF generator.
• Seta kwakhona ulandelelwano 1-Iphatha ukusetha kwakhona kwi-RX PHY kunye ne-RX Core.

3-Ucingo SPI
Lo mnqongo ungakhetha ukuguqula ujongano lweSPI ukuya kucingo olu-3.

Inkqubo yePLL
I-F-tile ineebhodi ezintathu ze-PLL zenkqubo. Ezi nkqubo ze-PLL ziyimithombo yewotshi ephambili ye-IP enzima (MAC, PCS, kunye ne-FEC) kunye ne-EMIB yokuwela. Oku kuthetha ukuba, xa usebenzisa indlela yewotshi ye-PLL, iibhloko azivalwanga yiwotshi ye-PMA kwaye azixhomekekanga kwiwotshi evela kumbindi weFPGA. Inkqubo nganye ye-PLL ivelisa kuphela iwotshi enxulumene nojongano lwamaza. UmzekeloampLe, udinga ii-PLL ezimbini zokusebenzisa ujongano olunye kwi-1 GHz kunye nojongano olunye kwi-500 MHz. Ukusebenzisa inkqubo ye-PLL ikuvumela ukuba usebenzise indlela nganye ngokuzimeleyo ngaphandle kokutshintsha kwewotshi yelayini echaphazela indlela engummelwane.
Inkqubo nganye ye-PLL inokusebenzisa naziphi na iiwotshi ezisibhozo ze-FGT. Ii-PLL zeNkqubo zinokwabelana ngewotshi yereferensi okanye zineewotshi ezahlukeneyo zokubhekisela. Ujongano ngalunye lunokukhetha ukuba yeyiphi inkqubo ye-PLL eyisebenzisayo, kodwa, xa sele ikhethiwe, ilungisiwe, ayiphindi iqwalaselwe kusetyenziswa uqwalaselo ngokutsha oluguqukayo.

Ulwazi olunxulumeneyo
I-F-tile Architecture kunye ne-PMA kunye ne-FEC Direct PHY IP User Guide

Ulwazi oluninzi malunga nenkqubo ye-PLL yokuvala imowudi kwizixhobo ze-Intel Agilex F-tile.

I-Pattern Generator kunye ne-Checker
Umenzi wepateni kunye nomhloli ziluncedo ekudaleni idatha samples kunye nokubeka iliso ngeenjongo zovavanyo.
Uluhlu lwe-11. Ijenereyitha yepateni exhaswayo

Ijenereyitha yoMfanekiso	Inkcazo
PRBS iphethini generator	Uyilo lwe-F-Tile JESD204C example PRBS iphethini yejenereyitha ixhasa idigri elandelayo yeepolynomials: PRBS23: X23+X18+1 PRBS15: X15+X14+1 PRBS9: X9+X5+1 PRBS7: X7+X6+1
Ramp iphethini generator	I-ramp ipateni yonyuso lwexabiso ngo-1 kwi-s nganye elandelayoample ngobubanzi bejeneretha ye N, kwaye iqengqeleka ukuya ku-0 xa zonke iibits kwisampngu 1. Yenza i-ramp iphethini generator ngokubhala i-1 ukuya kwi-bit ye-2 yerejista ye-tst_ctl yebhloko yolawulo lwe-ED.
Umjelo womyalelo ramp iphethini generator	Uyilo lwe-F-Tile JESD204C example ixhasa umyalelo wejelo ramp iphethini yejenereyitha kwindlela nganye. I-ramp ixabiso lepateni liyanyuswa ngo-1 ngamasuntswana ama-6 omyalelo. Imbewu yokuqala yipateni yokunyuswa kuzo zonke iindlela.

ITheyibhile 12. IsiHloli sePhatheni esixhaswayo

Umhloli wePatheni	Inkcazo
PRBS umkhangeli wepateni	Imbewu echwechwelayo kwisikhangeli sepateni iyazilungelelanisa xa i-F-Tile JESD204C IP ifezekisa ulungelelwaniso lwedeskew. Umkhangeli wepateni ufuna ii-octet ezisi-8 ukuze imbewu ekrazukileyo izenzele ungqamaniso.
Ramp umkhangeli wepateni	Idatha yokuqala esebenzayo sample kumguquleli ngamnye (M) ilayishwe njengexabiso lokuqala le-ramp ipateni. Idatha elandelayo sampLes amaxabiso kufuneka anyuke ngo-1 kumjikelo wewotshi nganye aye kubuninzi aze aqengqeleke aye ku-0.

Umhloli wePatheni	Inkcazo
	Umzekeloample, xa i-S=1, N=16 kunye ne-WIDTH_MULP = 2, ububanzi bedatha kwi-converter nganye yi-S * WIDTH_MULP * N = 32. Ubuninzi bedatha sample ixabiso ngu 0xFFFF. I-ramp umkhangeli wepateni uqinisekisa ukuba iipateni ezifanayo zamkelwa kuzo zonke iziguquli.
Umjelo womyalelo ramp umkhangeli wepateni	Uyilo lwe-F-Tile JESD204C example ixhasa umyalelo wejelo ramp umkhangeli wepateni. Igama lokuqala lomyalelo (amasuntswana ama-6) elifunyenweyo lilayishwe njengexabiso lokuqala. Amagama omyalelo alandelayo akwindlela enye kufuneka anyuke aye ku-0x3F aze aqengqeleke aye ku-0x00. Ijelo lomyalelo ramp iphethini umkhangeli iitshekhi ramp iipateni kuzo zonke iindlela.

I-F-Tile JESD204C TX kunye ne-RX IP
Lo mzekelo woyiloample ikuvumela ukuba uqwalasele i-TX/RX nganye kwimowudi ye-simplex okanye imo eyi-duplex.
Ulungelelwaniso lweDuplex luvumela umboniso wokusebenza kwe-IP usebenzisa i-loopback yesiriyali yangaphakathi okanye yangaphandle. I-CSRs ngaphakathi kwe-IP ayilungiswanga kude ukuze ivumele ulawulo lwe-IP kunye nokuqwalaselwa kwesimo.

F-Tile JESD204C Design Example Clock kunye nokuSeta kwakhona

Uyilo lwe-F-Tile JESD204C example ineseti yewotshi kunye neempawu zokuphinda zisete kwakhona.

Uluhlu loku-13.Uyilo Eksample Iiwotshi

Umqondiso wewotshi	Isalathiso	Inkcazo
mgmt_clk	Igalelo	Iwotshi yokwahluka kwe-LVDS ene-frequency ye-100 MHz.
refclk_xcvr	Igalelo	Iwotshi yereferensi ye-Transceiver kunye nesantya sereyithi yedatha / into engama-33.
refclk_core	Igalelo	Iwotshi yereferensi engundoqo enezakhelo ezifanayo refclk_xcvr.
kwi_sysref	Igalelo	Umqondiso we-SYSREF. Ubuninzi be-SYSREF frequency yireyithi yedatha/(66x32xE).
sysref_out	Isiphumo
txlink_clk rxlink_clk	Ngaphakathi	I-TX kunye ne-RX ikhonkco yewotshi kunye nesantya sezinga ledatha / 66.
txframe_clk rxframe_clk	Ngaphakathi	I-TX kunye ne-RX yesakhelo iwotshi enesantya sesantya sedatha/33 (FCLK_MULP=2) I-TX kunye ne-RX yesakhelo iwotshi enesantya sesantya sedatha/66 (FCLK_MULP=1)
tx_fclk rx_fclk	Ngaphakathi	I-TX kunye ne-RX yesigaba sewotshi enesantya sezinga ledatha/66 (FCLK_MULP=2) I-TX kunye ne-RX yesigaba iwotshi ihlala iphezulu (1'b1) xa FCLK_MULP=1
spi_SCLK	Isiphumo	SPI baud izinga iwotshi kunye frequency 20 MHz.

Xa ulayisha uyilo example kwisixhobo seFPGA, isiganeko sangaphakathi ninit_done siqinisekisa ukuba iJTAG ukuya kwibhulorho ye-Avalon Master isetiwe ngokutsha kunye nazo zonke ezinye iibhloko.

I-generator ye-SYSREF ine-reset yayo ezimeleyo ukuze ifake ubudlelwane obusondeleyo be-asynchronous kwi-txlink_clk kunye ne-rxlink_clk clocks. Le ndlela ibanzi ngakumbi ekulinganiseni umqondiso we-SYSREF ovela kwitshiphu yewotshi yangaphandle.

Uluhlu loku-14. Uyilo Eksample Ukusetha kwakhona

Seta kwakhona uMqondiso	Isalathiso	Inkcazo
global_rst_n	Igalelo	Cofa iqhosha lokuseta kwakhona umhlaba kuzo zonke iibhloko, ngaphandle kweJTAG ukuya kwibhulorho eyi-Avalon Master.
ninit_kwenziwe	Ngaphakathi	Imveliso evela kuSeta ngokutsha ukuKhupha iIP yeJTAG ukuya kwibhulorho eyi-Avalon Master.
edctl_rst_n	Ngaphakathi	Ibhloko yoLawulo lwe-ED isetwa ngokutsha ngu-JTAG ukuya kwibhulorho eyi-Avalon Master. I-hw_rst kunye ne-global_rst_n izibuko aziseti ngokutsha ibhloko yoLawulo lwe-ED.
hw_kuqala	Ngaphakathi	Assert kunye nedeassert hw_rst ngokubhalela kwirejista ye-rst_ctl ye-ED Control block. mgmt_rst_in_n uyaqinisekisa xa u-hw_rst ebangwa.
mgmt_rst_in_n	Ngaphakathi	Seta kwakhona ujongano lwenkumbulo ye-Avalon enemephu yee-IP ezahlukeneyo kunye negalelo lokuseta ngokutsha abalandelelanisi:  j20c_reconfig_reset for F-Tile JESD204C IP duplex Native PHY spi_rst_n ye-SPI inkosi pio_rst_n ye-PIO ubume kunye nolawulo reset_in0 izibuko yokusetha kwakhona ulandelelwano 0 kunye 1 I-global_rst_n, hw_rst, okanye edctl_rst_n port asserts isetyenziselwe kwakhona kwi mgmt_rst_in_n.
sysref_rst_n	Ngaphakathi	Phinda umisele ibhloko ye-generator ye-SYSREF kwibhloko yoLawulo lwe-ED usebenzisa i-reset sequencer 0 reset_out2 port. Isilandeleli sokusetha kwakhona 0 reset_out2 port dessserts ukusetwa kwakhona ukuba i-PLL engundoqo itshixiwe.
undoqo_pll_kuqala	Ngaphakathi	Iseta kwakhona undoqo we-PLL ngokusebenzisa i-reset 0 reset_out0 port. Undoqo we-PLL ucwangcisa kwakhona xa i-mgmt_rst_in_n iphinda ibekiwe.
j204c_tx_avs_rst_n	Ngaphakathi	Iseta kwakhona i-F-Tile JESD204C TX inkumbulo ye-Avalon-ujongano olufakwe kwimaphu ngokuseta ngokutsha i-sequencer 0. Ujongano lwe-TX Avalon lwenkumbulo-maphulwe iqinisekisa xa i-mgmt_rst_in_n isenziwa.
j204c_rx_avs_rst_n	Ngaphakathi	Iseta kwakhona i-F-Tile JESD204C TX inkumbulo ye-Avalon-ujongano olufakwe kwimaphu ngokuseta ngokutsha i-sequencer 1. Ujongano lwe-RX Avalon yememori-mapped iqinisekisa xa i-mgmt_rst_in_n ibangwa.
j204c_tx_rst_n	Ngaphakathi	Iseta kwakhona i-F-Tile JESD204C TX ikhonkco kunye neengqimba zothutho kwi-txlink_clk, kunye ne-txframe_clk, imimandla. Isilandeleli sokusetha ngokutsha 0 reset_out5 izibuko iphinda imisele j204c_tx_rst_n. Oku kuseta ngokutsha iideserts ukuba i-PLL engundoqo itshixiwe, kwaye i-tx_pma_ready kunye ne-tx_ready iimpawu ziyabaniswa.
j204c_rx_rst_n	Ngaphakathi	Iseta kwakhona ikhonkco le-F-Tile JESD204C RX kunye nemigangatho yezothutho kwi, rxlink_clk, kunye ne-rxframe_clk imimandla.

Seta kwakhona uMqondiso	Isalathiso	Inkcazo
		Ukusetha kwakhona isilandeleli 1 reset_out4 izibuko iphinda imisele i-j204c_rx_rst_n. Oku kuseta ngokutsha iideserts ukuba i-PLL engundoqo itshixiwe, kwaye i-rx_pma_ready kunye ne-rx_ready iimpawu ziyabaniswa.
j204c_tx_rst_ack_n	Ngaphakathi	Lungisa kwakhona umqondiso wokuxhawula izandla nge-j204c_tx_rst_n.
j204c_rx_rst_ack_n	Ngaphakathi	Lungisa kwakhona umqondiso wokuxhawula izandla nge-j204c_rx_rst_n.

Umzobo 8. Umzobo wexesha woYilo Example Ukusetha kwakhona

F-Tile JESD204C Design Example Imiqondiso

Itheyibhile 15. Iimpawu zeNxibelelwano yeNkqubo

Umqondiso	Isalathiso	Inkcazo
Iiwotshi kunye nokuSeta kwakhona
mgmt_clk	Igalelo	100 MHz iwotshi yolawulo lwenkqubo.
refclk_xcvr	Igalelo	Ikloko yereferensi ye-F-tile UX QUAD kunye neNkqubo yePLL. Ilingana nereyithi yedatha/into ye-33.
refclk_core	Igalelo	Iwotshi yereferensi engundoqo ye-PLL. Isebenzisa amaza ewotshi afana ne-refclk_xcvr.
kwi_sysref	Igalelo	Umqondiso we-SYSREF ovela kwijenereyitha ye-SYSREF yangaphandle yokuphunyezwa kweJESD204C Udidi oluphantsi lwe-1.
sysref_out	Isiphumo	Umqondiso we-SYSREF we-JESD204C Umgangatho ophantsi we-1 uphunyezo oluveliswe sisixhobo se-FPGA kuyilo lwe-ex.ample njongo yokuqalisa ikhonkco kuphela.

 

Umqondiso	Isalathiso	Inkcazo
SPI
spi_SS_n[2:0]	Isiphumo	Esezantsi esebenzayo, i-SPI yokhetho uphawu lwekhoboka.
spi_SCLK	Isiphumo	SPI iwotshi yothotho.
spi_sdio	Igalelo/Imveliso	Idatha yeziphumo ukusuka kwinkosi ukuya kwikhoboka langaphandle. Faka idatha ukusuka kwikhoboka langaphandle ukuya kwinkosi.

Umqondiso	Isalathiso	Inkcazo
Phawula:Xa Ukuvelisa i-3-Wire SPI Module ukhetho luvuliwe.
spi_MISO Phawula: Xa Ukuvelisa i-3-Wire SPI Module ukhetho aluvulwanga.	Igalelo	Idatha yokufaka esuka kwikhoboka langaphandle ukuya kumphathi weSPI.
spi_MOSI Phawula: Xa Ukuvelisa i-3-Wire SPI Module ukhetho aluvulwanga.	Isiphumo	Idatha yemveliso esuka kwi-SPI master ukuya kwikhoboka langaphandle.

 

Umqondiso	Isalathiso	Inkcazo
ADC/DAC
tx_serial_data[LINK*L-1:0]	Isiphumo	Umahluko wedatha yemveliso yeserial enesantya esiphezulu kwiDAC. Iwotshi ifakwe kwi-serial data stream.
tx_serial_data_n[LINK*L-1:0]
rx_serial_data[LINK*L-1:0]	Igalelo	Umahluko ngesantya esiphezulu data igalelo serial ukusuka ADC. Iwotshi ifunyanwa kuthotho lwedatha.
rx_serial_data_n[LINK*L-1:0]

 

Umqondiso	Isalathiso	Inkcazo
Injongo ngokubanzi I/O
umsebenzisi_ukhokela[3:0]	Isiphumo	Ibonisa imeko yezi meko zilandelayo: [0]: SPI inkqubo yenziwe [1]: Impazamo yekhonkco yeTX [2]: Impazamo yekhonkco ye-RX [3]: Impazamo yomkhangeli wepateni yedatha yeAvalon yostrimisho
umsebenzisi_dip[3:0]	Igalelo	Imo yomsebenzisi igalelo lokutshintsha i-DIP: [0]: Yangaphakathi uthotho loopback vumela [1]: I-SYSREF eyenziwe yiFPGA yenza ukuba isebenze [3:2]: Igciniwe

 

Umqondiso	Isalathiso	Inkcazo
Ngaphandle kwebhendi (OOB) kunye neSimo
rx_patchk_data_error[LINK-1:0]	Isiphumo	Xa olu phawu lubasiwe, lubonisa ukuba umkhangeli wepateni ufumene impazamo.
rx_link_error[LINK-1:0]	Isiphumo	Xa olu phawu lubangwa, lubonisa ukuba iJESD204C RX IP ithe uphazamiseko.
tx_link_error[LINK-1:0]	Isiphumo	Xa olu phawu lubasiwe, lubonisa ukuba iJESD204C TX IP iqinisekise uphazamiseko.
emb_lock_ngaphandle	Isiphumo	Xa olu phawu lubasiwe, lubonisa i-JESD204C RX IP iphumelele iqhaga le-EMB.
sh_tshixa_ngaphandle	Isiphumo	Xa olu phawu lubasiwe, lubonisa i-JESD204C RX i-header yongqamaniso ye-IP itshixiwe.

 

Umqondiso	Isalathiso	Inkcazo
Ukusasazwa kweAvalon
rx_avst_valid[LINK-1:0]	Igalelo	Ibonisa ukuba isiguquli sample data kumaleko wesicelo iyasebenza okanye ayisebenzi. 0: Idatha ayisebenzi 1: Idatha iyasebenza
rx_avst_data[(TOTAL_SAMPLE*N)-1:0 ]	Igalelo	Isiguquli sample data kumaleko wesicelo.

F-Tile JESD204C Design Example Iirejista zoLawulo

Uyilo lwe-F-Tile JESD204C exampiirejista kwi-ED Control block sebenzisa i-byte-addressing (32 bits).

Uluhlu loku-16. Uyilo Eksample Imephu yeedilesi
Ezi rejista zebhloko ye-32-bit ye-ED zikwi-mgmt_clk domain.

Icandelo	Idilesi
F-Tile JESD204C TX IP	0x000C_0000 – 0x000C_03FF
F-Tile JESD204C RX IP	0x000D_0000 – 0x000D_03FF
Ulawulo lweSPI	0x0102_0000 – 0x0102_001F
Ulawulo lwePIO	0x0102_0020 – 0x0102_002F
Isimo sePIO	0x0102_0040 – 0x0102_004F
Phinda umisele iSequencer 0	0x0102_0100 – 0x0102_01FF
Phinda umisele iSequencer 1	0x0102_0200 – 0x0102_02FF
Ulawulo lwe-ED	0x0102_0400 – 0x0102_04FF
F-Tile JESD204C IP transceiver PHY Reconfig	0x0200_0000 – 0x023F_FFFF

Uluhlu 17. Uhlobo loFikelelo lokuBhalisa kunye neNkcazo
Le theyibhile ichaza uhlobo lofikelelo lwerejista ye-Intel FPGA IPs.

Uhlobo lokufikelela	Ingcaciso
RO/V	Isoftware efundwayo kuphela (akukho mpembelelo ekubhaleni). Ixabiso linokwahluka.
RW	Isoftware ifunda kwaye ibuyisela ixabiso lebit langoku. Isoftware ibhala kwaye icwangcisa isuntswana kwixabiso elifunekayo.
RW1C	Isoftware ifunda kwaye ibuyisela ixabiso lebit langoku. Isoftware ibhala i-0 kwaye ayinasiphumo. I-Software ibhala i-1 kwaye icoca i-bit ukuya ku-0 ukuba i-bit imiselwe ku-1 yi-hardware. I-Hardware iseta bit ukuya ku-1. Isoftware ecacileyo inokubaluleka okuphezulu kuneseti yehardware.

Uluhlu 18. Imephu yedilesi yolawulo lwe-ED

Offset	Bhalisa Igama
0x00	Okokuqala_ctl
0x04	rst_sts0
iqhubekile...

Offset	Bhalisa Igama
0x10	rst_sts_detected0
0x40	sysref_ctl
0x44	sysref_sts
0x80	tst_ctl
0x8c	tst_err0

Itheyibhile 19. Ulawulo lweBlock ye-ED kunye neerejista zesimo

Byte Offset	Bhalisa	Igama	Ukufikelela	Lungisa kwakhona	Inkcazo
0x00	Okokuqala_ctl	Okokuqala_assert	RW	0x0	Lungisa kwakhona ulawulo. [0]: Bhala isi-1 ukumisela ukusetwa kwakhona. (hw_rst) Bhala u-0 kwakhona ukuseta kwakhona ideassert. [31:1]: Sigciniwe.
0x04	rst_sts0	Imo_yokuqala	RO/V	0x0	Seta kwakhona ubume. [0]: Imo ye-PLL itshixiwe. [31:1]: Sigciniwe.
0x10	rst_sts_dete cted0	rst_sts_set	RW1C	0x0	I-SYSREF edge yokubona imeko ye-SYSREF yangaphakathi okanye yangaphandle yejeneretha. [0]: Ixabiso le-1 Ibonisa i-SYSREF edge yokunyuka ifunyenwe kwi-subclass ye-1 yokusebenza. Isoftware inokubhala u-1 ukucima le bit ukwenza ukuba ubhaqo olutsha lwe-SYSREF lusebenze. [31:1]: Sigciniwe.
0x40	sysref_ctl	sysref_contr ol	RW	I-Duplex yedatapath Ifoto enye: 0x00080	Ulawulo lwe-SYSREF. Ibhekisele ku Uluhlu loku-10 kwiphepha le-17 ngolwazi oluthe vetshe malunga nokusetyenziswa kwale rejista.
				Amaxesha ngamaxesha:	Phawula: Ixabiso lokuseta ngokutsha lixhomekeke kwi
				0x00081	uhlobo lwe-SYSREF kunye ne-F-Tile
				Ikhefu- ngamaxesha:	JESD204C IP useto lweparamitha yedatha yedata.
				0x00082
				TX okanye RX data
				indlela
				Ishot enye:
				0x00000
				Amaxesha ngamaxesha:
				0x00001
				Isikhewu-
				amaxesha ngamaxesha:
				0x00002
0x44	sysref_sts	sysref_statu s	RO/V	0x0	Ubume be-SYSREF. Le rejista iqulethe ixesha lamva nje le-SYSREF kunye nezicwangciso zomjikelo womsebenzi we-SYSREF generator yangaphakathi. Ibhekisele ku Uluhlu loku-9 kwiphepha le-16 ngexabiso elisemthethweni lexesha le-SYSREF kunye nomjikelo womsebenzi.
iqhubekile...

Byte Offset	Bhalisa	Igama	Ukufikelela	Lungisa kwakhona	Inkcazo
					[8:0]: Ixesha le-SYSREF. Xa ixabiso lingu-0xFF, i Ixesha le-SYSREF = 255 Xa ixabiso ukuba 0x00, ixesha SYSREF = 256. [17:9]: SYSREF umsebenzi umjikelo. [31:18]: Sigciniwe.
0x80	tst_ctl	tst_control	RW	0x0	Ulawulo lovavanyo. Sebenzisa le rejista ukwenza iipatheni zovavanyo ezahlukeneyo zepateni yejenereyitha kunye nomkhangeli. [1:0] = Intsimi egciniweyo [2] = ramp_uvavanyo_ctl 1'b0 = Yenza i-PRBS iphethini yejenereyitha kunye nomhloli 1'b1 = Yenza i-ramp iphethini yejenereyitha kunye nomhloli [31:3]: Sigciniwe.
0x8c	tst_err0	tst_impazamo	RW1C	0x0	Error flag for Link 0. When the bit is 1’b1, it indicates an error has happened. You should resolve the error before writing 1’b1 to the respective bit to clear the error flag. [0] = Pattern checker error [1] = tx_link_error [2] = rx_link_error [3] = Command pattern checker error [31:4]: Reserved.

Uhlaziyo lweMbali yoXwebhu lwe-F-Tile JESD204C Intel FPGA IP Design Example Isikhokelo somsebenzisi

Inguqulelo yoXwebhu	Intel Quartus Prime Version	IP Version	Iinguqu
2021.10.11	21.3	1.0.0	Ukukhutshwa kokuqala.

Amaxwebhu / Izibonelelo

intel F-Tile JESD204C Intel FPGA IP Design Example [pdf] Isikhokelo somsebenzisi F-Tile JESD204C Intel FPGA IP Design Example, F-Tile JESD204C, Intel FPGA IP Design Example, IP Design Example, Uyilo Eksample

Iimbekiselo

• Incwadi yokusebenzisa