Litaba pata
1 F-Tile JESD204C Intel FPGA IP Design Example
2 Mabapi le F-Tile JESD204C Intel® FPGA IP Design Example Bukana ea Mosebelisi
2.1 Bamameli ba Reriloeng
3 F-Tile JESD204C Intel FPGA IP Design Example Quick Start Guide
3.1 Moqapi Example Block Diagram
3.2 Litlhoko tsa Software
3.3 Ho Hlahisa Moralo
3.4 Ho Etsisa Moralo Example Testbench
3.5 Ho Kopanya Moralo Example
4 Tlhaloso e Felletseng bakeng sa Moetso oa F-Tile JESD204C Example
4.1 Likaroloana tsa Tsamaiso
4.2 F-Tile JESD204C Design Example Clock le Reset
4.3 F-Tile JESD204C Design Example Lipontšo
4.4 F-Tile JESD204C Design Example Control Registers
5 Nalane ea Phetoho ea Litokomane bakeng sa F-Tile JESD204C Intel FPGA IP Design Example Bukana ea Mosebelisi
6 Litokomane / Lisebelisoa
6.1 Litšupiso
7 Related Posts

INTEL-LGO

F-Tile JESD204C Intel FPGA IP Design Example

F-Tile-JESD204C-Intel-FPGA-IP-Design-Example-PRODUCT-SETŠOANTŠO

Mabapi le F-Tile JESD204C Intel® FPGA IP Design Example Bukana ea Mosebelisi

Tataiso ena ea mosebelisi e fana ka likarolo, litataiso tsa tšebeliso, le tlhaloso e qaqileng mabapi le moralo oa examples bakeng sa F-Tile JESD204C Intel® FPGA IP e sebelisang lisebelisoa tsa Intel Agilex™.

Bamameli ba Reriloeng

Tokomane ena e reretsoe:

  • Moqapi oa meralo ea ho etsa khetho ea IP nakong ea mohato oa moralo oa moralo oa sistimi
  • Baqapi ba li-Hardware ha ba kopanya IP ho moralo oa boemo ba bona ba sistimi
  • Baenjineri ba netefatso nakong ea ketsiso ea boemo ba sistimi le mohato oa netefatso ea lisebelisoa

Litokomane Tse Amanang
Tafole e latelang e thathamisa litokomane tse ling tsa litšupiso tse amanang le F-Tile JESD204C Intel FPGA IP.

Lethathamo la 1. Litokomane Tse Amanang

Referense Tlhaloso
F-Tile JESD204C Intel FPGA IP User Guide E fana ka leseli mabapi le F-Tile JESD204C Intel FPGA IP.
F-Tile JESD204C Lintlha tsa Phallo tsa Intel FPGA IP E thathamisa liphetoho tse entsoeng bakeng sa F-Tile JESD204C F-Tile JESD204C tokollong e itseng.
Leqephe la Lintlha tsa Sesebelisoa sa Intel Agilex Tokomane ena e hlalosa litšobotsi tsa motlakase, litšoaneleho tsa ho fetola, litlhaloso tsa tlhophiso, le nako ea lisebelisoa tsa Intel Agilex.

Acronyms le Glossary

Lethathamo la 2. Lethathamo la Acronym

Kgutsufatso Katoloso
LEMC Sebaka se Atolositsoeng sa Multiblock Clock
FC Sekhahla sa oache ea foreimi
ADC Analog ho Digital Converter
DAC Sefetoleli sa Digital ho Analog
DSP Digital Signal Processor
TX Phetiso
RX Moamoheli
Kgutsufatso Katoloso
DLL Lera la khokahanyo ea data
CSR Rejisetara ea taolo le maemo
CRU Oache le Seta Yuniti bocha
ISR Khaotsa kemiso ea litšebeletso
FIFO Pele-pele-pele
SERDES Seriizer Deserializer
ECC Phoso ea ho Lokisa Khouto
FEC Tsoela Pele Phoso Khalemelo
SERR Ho Fumana Phoso e le 'Ngoe (ho ECC, e ka lokisoa)
DERR Ho fumanoa ha Liphoso Habeli (ho ECC, ho bolaea)
PRBS Pseudorandom binary tatelano
MAC Selaoli sa phihlello ea litaba. MAC e kenyelletsa protocol sublayer, transport layer, le data link layer.
PHY Lera la 'Mele. PHY hangata e kenyelletsa lera la 'mele, SERDES, bakhanni, baamoheli le CDR.
PCS Physical Coding Lera
PMA Boimahanyo ba 'mele bo Bohareng
RBD RX Buffer Ho lieha
UI Sekhahla sa Yuniti = nako ea serial bit
Palo ea RBD RX Buffer Delay ea ho fihla ha morao tjena
RBD e fokotsehile RX Buffer Delay monyetla oa ho lokolloa
SH Kopanya hlooho
TL Lera la lipalangoang
EMIB Embedded Multi-die Interconnect Bridge

Lethathamo la 3. Lenane la Bukana

Nako Tlhaloso
Sesebelisoa sa Converter ADC kapa DAC converter
Sesebelisoa sa logic FPGA kapa ASIC
Octet Sehlopha sa li-bits tse 8, tse sebetsang e le kenyelletso ho 64/66 encoder le tlhahiso ho tsoa ho decoder.
Nibble Sehlopha sa li-bits tse 4 e leng motheo oa ts'ebetso oa JESD204C
Thibela Letšoao la 66-bit le hlahisoang ke 64/66 encoding scheme
Tekanyo ea Line Sekhahla se sebetsang hantle sa lihokelo tsa serial

Sekhahla sa Lane Line = (Mx Sx N'x 66/64 x FC) / L
Khokahano oache Khokahano oache = Lane Line Rate/66.
Foreimi Sehlopha sa li-octet tse latellanang moo boemo ba octet e 'ngoe le e' ngoe bo ka khetholloang ka pontšo ea letšoao la ho tsamaisa foreimi.
Oache ea foreimi Oache ea tsamaiso e sebetsang ka sekhahla sa foreimi, e tlamehang ho ba 1x le 2x link clock.
Nako Tlhaloso
Samphanyane ka hora ea foreimi Sampka tlase ho oache, kakaretso ea sampLes ka foreimi oache bakeng sa sesebediswa converter.
LEMC Oache e kahare e sebelisetsoang ho hokahanya moeli oa li-multiblock tse atolositsoeng lipakeng tsa litselana le litšupiso tsa kantle (SYSREF kapa Subclass 1).
Sehlopha sa 0 Ha ho tšehetso bakeng sa deterministic latency. Lintlha li lokela ho hlahisoa hang-hang tseleng ea ho tsamaisa deskew ho moamoheli.
Sehlopha sa 1 Ho lieha ha nako ho sebelisa SYSREF.
Multipoint Link Lihokelo tsa li-inter-device tse nang le lisebelisoa tse 2 kapa ho feta tsa converter.
64B / 66B khouto Khoutu ea mohala e bonts'ang data ea 64-bit ho li-bits tse 66 ho theha boloko. Sebopeho sa data sa boemo ba motheo ke "block" e qalang ka hlooho ea sync ea 2-bit.

Tafole ea 4. Matšoao

Nako Tlhaloso
L Palo ea litselana ka sesebelisoa sa converter
M Palo ea li-converter ka sesebelisoa
F Nomoro ea li-octet ka foreime ka tsela e le 'ngoe
S Nomoro ea sampLes a tšoaetsanoa ka 'ngoe converter ka foreimi potoloho
N Qeto ea ho fetolela
N' Kakaretso ea palo ea li-bits ka sample ka sebopeho sa data sa mosebelisi
CS Palo ea li-control bits ka phetoho sample
CF Nomoro ea mantsoe a laolang nako ka nako ea oache ea foreimi ka sehokelo
HD Sebopeho sa data sa High Density user data
E Palo ea li-multiblocks ho multiblock e atolositsoeng

F-Tile JESD204C Intel FPGA IP Design Example Quick Start Guide

Moetso oa F-Tile JESD204C Intel FPGA IP examples bakeng sa lisebelisoa tsa Intel Agilex li na le testbench e etsisang le moralo oa hardware o tšehetsang ho bokella le ho hlahloba lisebelisoa.
O ka hlahisa sebopeho sa F-Tile JESD204C exampHo feta ka lethathamo la IP ho software ea Intel Quartus® Prime Pro Edition.

Setšoantšo sa 1. Ntlafatso ea Stages bakeng sa Moqapi Example

F-Tile-JESD204C-Intel-FPGA-IP-Design-Example-01

Moqapi Example Block Diagram

Setšoantšo sa 2. F-Tile JESD204C Design Example Setšoantšo sa Block Block sa boemo bo phahameng

F-Tile-JESD204C-Intel-FPGA-IP-Design-Example-02

Moqapi exampe na le li-module tse latelang:

  • Sistimi ea Moqapi oa sethala
    • F-Tile JESD204C Intel FPGA IP
    • JTAG ho ea borokhong ba Avalon Master
    • Parallel I/O (PIO) molaoli
    • Serial Port Interface (SPI)—mojule o moholo— IOPLL
    • Jenereithara ea SYSREF
    • Example Design (ED) Laola CSR
    • Seta li-sequencers bocha
  • Sistimi ea PLL
  • Jenereithara ea mohlala
  • Mohlahlobi oa mohlala

Lethathamo la 5. Moqapi Example Modules

Likaroloana Tlhaloso
Sistimi ea Moqapi oa sethala Sistimi ea Moqapi oa Platform e tiisa tsela ea data ea F-Tile JESD204C IP le lisebelisoa tse tšehetsang.
F-Tile JESD204C Intel FPGA IP Setsi sena sa Moqapi oa Platform se na le li-IP tsa TX le RX F-Tile JESD204C tse kentsoeng hammoho le duplex PHY.
JTAG ho ea borokhong ba Avalon Master Borokho bona bo fana ka phihlello ea moamoheli oa sistimi ho IP e kentsoeng ka memori ka moralo ka sebopeho sa JTAG segokahanyi.
Parallel I/O (PIO) molaoli Taolo ena e fana ka segokanyimmediamentsi sa memori bakeng sa sampling le ho khanna ka kakaretso sepheo sa I/O likoung.
SPI master Mojule ona o sebetsana le phetiso ea serial ea data ea tlhophiso ho sebopeho sa SPI pheletsong ea converter.
Jenereithara ea SYSREF Jenereithara ea SYSREF e sebelisa oache ea khokahano joalo ka oache ea litšupiso mme e hlahisa li-pulse tsa SYSREF bakeng sa F-Tile JESD204C IP.

Hlokomela: Moqapi ona exampLe e sebelisa jenereithara ea SYSREF ho bonts'a qalo ea sehokelo sa duplex F-Tile JESD204C IP. Ts'ebelisong ea boemo ba sistimi ea F-Tile JESD204C subclass 1, o tlameha ho hlahisa SYSREF ho tsoa mohloling o tšoanang le oache ea sesebelisoa.
IOPLL Moqapi ona example sebelisa IOPLL ho hlahisa oache ea mosebelisi bakeng sa ho fetisetsa data ho F-Tile JESD204C IP.
ED Control CSR Mojule ona o fana ka taolo ea SYSREF ea ho lemoha le boemo, le taolo ea mokhoa oa teko le maemo.
Seta li-sequencers bocha Moqapi ona exampe na le li-sequence tse 2 tsa reset:
  • Seta Sequence 0-E sebetsana le ho seta bocha ho TX/RX Avalon® streaming domain, Avalon memory-mapped domain, core PLL, TX PHY, TX core, le SYSREF jenereithara.
  • Seta Tatelano botjha 1-E sebetsana le ho seta botjha ho RX PHY le RX core.
Sistimi ea PLL Mohloli oa oache oa mantlha oa F-tile hard IP le EMIB crossing.
Jenereithara ea mohlala Jenereithara ea mohlala e hlahisa PRBS kapa ramp mohlala.
Mohlahlobi oa mohlala Sehlahlobi sa mohlala se netefatsa PRBS kapa ramp paterone e amohetse, 'me e tšoaea phoso ha e fumana ho se lumellane ha data sample.
Litlhoko tsa Software

Intel e sebelisa software e latelang ho leka moralo oa exampka har'a sistimi ea Linux:

  • Software ea Intel Quartus Prime Pro Edition
  • Questa*/ModelSim* kapa VCS*/VCS MX simulator
Ho Hlahisa Moralo

F-Tile-JESD204C-Intel-FPGA-IP-Design-Example-03Ho hlahisa moralo exampe tsoa ho mohlophisi oa parameter ea IP:

  1. Theha morero o lebisitseng lelapa la sesebelisoa sa Intel Agilex F-tile ebe u khetha sesebelisoa se lakatsehang.
  2. Lenaneng la IP Catalog, Tools ➤ IP Catalog, khetha F-Tile JESD204C Intel FPGA IP.
  3. Hlalosa lebitso la boemo bo holimo le foldara bakeng sa phapang ea hau ea IP. Tobetsa OK. Mohlophisi oa parameter o eketsa boemo bo holimo .ip file ho morero oa hajoale ka bo eona. Haeba u khothalletsoa ho kenya .ip ka letsoho file ho morero, tobetsa Morero ➤ Eketsa/ Tlosa Files ho Morero ho eketsa file.
  4. Tlas'a Example Design tab, hlakisa sebopeho sa mohlalaample liparamente joalo ka ha ho hlalositsoe ho Design Example Li-Parameters.
  5. Tobetsa Hlahisa Example Design.

Software e hlahisa liqapi tsohle files ho li-directory tse nyane. Tsena files li hlokeha ho tsamaisa ketsiso le pokello.

Moqapi Example Li-Parameters
F-Tile JESD204C Intel FPGA IP paramethara e kenyelletsa Example Design tab hore o hlalose liparamente tse itseng pele o hlahisa moralo oa example.

Lethathamo la 6. Mekhahlelo ho Example Design Tab

Paramethara Dikgetho Tlhaloso
Kgetha Moralo
  • Taolo ea Console ea Sisteme
  • Ha ho letho
 Khetha taolo ea tsamaiso ea console ho fihlella moralo oa examptsela ea data ka har'a console ea tsamaiso.
Ketsiso Bulehile, Tima Bulela IP ho hlahisa tse hlokahalang files bakeng sa ho etsisa moralo example.
Synthesis Bulehile, Tima Bulela IP ho hlahisa tse hlokahalang files bakeng sa pokello ea Intel Quartus Prime le pontšo ea hardware.
HDL sebopeho (bakeng sa papiso)
  • Verilog
  • VDHL
 Khetha mofuta oa HDL oa RTL files bakeng sa ketsiso.
HDL sebopeho (bakeng sa synthesis) Verilog feela Khetha mofuta oa HDL oa RTL files bakeng sa ho kopanya.
Paramethara Dikgetho Tlhaloso
Hlahisa 3- terata SPI module Bulehile, Tima Bulela ho bulela 3-wire SPI interface ho fapana le 4-wire.
Mokhoa oa Sysref
  • Thunya e le 'ngoe
  • Nako le nako
  • Nako le nako
 Khetha hore na u batla hore tekano ea SYSREF e be mokhoa oa ho otla ha molumo o le mong, nako le nako, kapa oa nakoana, ho latela litlhoko tsa moralo oa hau le ho feto-fetoha ha nako.
  • Thunya e le 'ngoe-Khetha khetho ena ho etsa hore SYSREF e be mokhoa oa ho thunngoa ha molumo o le mong. Boleng ba sysref_ctrl[17] register bit's boleng ke 0. Kamora F-Tile JESD204C IP reset desserts, fetola boleng ba sysref_ctrl[17] registering ho tloha ho 0 ho isa ho 1, ebe ho ea ho 0, bakeng sa molumo o le mong oa SYSREF.
  • Periodic-SYSREF ka mokhoa oa nakoana e na le 50:50 potoloho ea mosebetsi. Nako ea SYSREF ke E*SYSREF_MULP.
  • Gapped periodic — SYSREF e na le potoloho e hlophisehileng ea mosebetsi oa granularity ea 1 link clock cycle. Nako ea SYSREF ke E*SYSREF_MULP. Bakeng sa tlhophiso ea potoloho ea mosebetsi o tsoileng matsoho, blockage ea SYSREF e tlameha ho ipeha tlas'a 50:50 cycle cycle.
    Sheba ho SYSREF Jenereithara Bakeng sa tlhaiso-leseling e batsi ka SYSREF
    nako.
Khetha boto Ha ho letho Khetha boto bakeng sa mohlala oa moraloample.
  • Ha ho letho-Khetho ena ha e kenyelle likarolo tsa hardware bakeng sa moralo oa example. Likabelo tsohle tsa phini li tla beoa ho li-virtual pins.
Mohlala oa Teko
  • PRBS-7
  • PRBS-9
  • PRBS-15
  • PRBS-23
  • Ramp
 Khetha mohlala oa jenereithara le mohlala oa tlhahlobo ea tlhahlobo.
  • Mohlala jenereithara-JESD204C tšehetsa PRBS mohlala jenereithara ka data sample. Sena se bolela hore bophara ba data ke khetho ea N + CS. Jenereithara ea mohlala oa PRBS le sehlahlobi li na le thuso bakeng sa ho theha data sample stimulus bakeng sa tlhahlobo mme ha e tsamaellane le mokhoa oa tlhahlobo oa PRBS ho converter ea ADC/DAC.
  • Ramp Sehokelo sa Sehokelo sa Moetso—JESD204C se sebetsa ka mokhoa o tloaelehileng empa sepalangoang hamorao sea koaleha, 'me tlhahiso e tsoang ho sefometha e hlokomolohuoa. Tsela e 'ngoe le e' ngoe e fetisa molapo o ts'oanang oa octet o nyolohang ho tloha 0x00 ho isa 0xFF ebe o pheta. Ramp tlhahlobo ea mohlala e lumelloa ke prbs_test_ctl.
  • PRBS Pattern Checker-JESD204C PRBS scrambler e ikamahanya le eona 'me ho lebeletsoe hore ha IP core e khona ho khetholla sehokelo, peo e ntseng e hohola e se e hokahantsoe. PRBS ho qhekella peo ho tla nka li-octet tse 8 ho iqalla.
  • Ramp Pattern Checker-JESD204C scratching is self-synchronization 'me ho lebeletsoe hore ha IP core e khona ho khetholla sehokelo, peo ea ho qhekella e se e hokahantsoe. Octet ea pele e sebetsang e laeloa joalo ka ramp boleng ba pele. Lintlha tse latelang li tlameha ho eketseha ho fihla ho 0xFF ebe li fetela ho 0x00. Ramp sehlahlobi sa mohlala se lokela ho hlahloba mokhoa o ts'oanang ho litseleng tsohle.
Lumella serile loopback ea ka hare Bulehile, Tima Khetha ka hare ho serial loopback.
Numella Command Channel Bulehile, Tima Khetha mohlala oa mocha oa taelo.

Sebopeho sa Directory
Moetso oa F-Tile JESD204C example li-directory li na le lihlahisoa files bakeng sa moralo examples.

Setšoantšo sa 3. Sebopeho sa Directory bakeng sa F-Tile JESD204C Intel Agilex Design Example

F-Tile-JESD204C-Intel-FPGA-IP-Design-Example-04Lethathamo la 7. Directory Files

Liphutheli Files
ed/rtl
  • tx
    • j204c_f_tx_ip.qsys
    • j204c_f tx_ss.qsys
    • altera_s10_user_rst_clkgate_0.ip
    • j204c f_se_outbuf_1bit.ip
ketsiso/ motataisi
  • modelim_sim.tcl
  • TB_top_waveform.do
ketsiso/sinopsy
  • vcs
    • vcs_sim.sh
    • TB_top_wave_ed.do
  • vcsmx
    • vcsmx_sim.sh
    • TB_top_wave_ed.do
Ho Etsisa Moralo Example Testbench

Moqapi example testbench e etsisa moralo oa hau o hlahisitsoeng.

Setšoantšo sa 4. Mokhoa

F-Tile-JESD204C-Intel-FPGA-IP-Design-Example-05Ho etsisa moralo, etsa mehato e latelang:

  1. Fetola directory ea ho sebetsa hoample_design_directory>/simulation/ .
  2. Moleng oa taelo, tsamaisa script ea simulation. Tafole e ka tlase e bonts'a litaelo tsa ho tsamaisa simulators tse tšehetsoeng.
Moetsisi Taelo
Questa/ModelSim vsim -do modelim_sim.tcl
vsim -c -do modelsim_sim.tcl (ntle le Questa/ ModelSim GUI)
VCS sh vcs_sim.sh
Tlhaloso: VCS MX sh vcsmx_sim.sh

Papiso e qetella ka melaetsa e bontšang hore na ho matha ho atlehile kapa che.

Setšoantšo sa 5. Ketsiso e Atlehileng
Palo ena e bonts'a molaetsa o atlehileng oa ketsiso bakeng sa simulator ea VCS.F-Tile-JESD204C-Intel-FPGA-IP-Design-Example-09

Ho Kopanya Moralo Example

Ho bokella mokhahlelo feela example morero, latela mehato ena:

  1. Netefatsa moetso oa moetso example moloko o felile.
  2. Ho software ea Intel Quartus Prime Pro Edition, bula morero oa Intel Quartus Prime Pro Editionample_ design_ directory>/ed/quartus.
  3. Ho menu ea Processing, tobetsa Start Compilation.

Tlhaloso e Felletseng bakeng sa Moetso oa F-Tile JESD204C Example

Moetso oa F-Tile JESD204C example e bonts'a ts'ebetso ea ho phallela data ka mokhoa oa loopback.
O ka hlakisa litlhophiso tsa liparamente tseo u li khethileng 'me u hlahise moralo oa example.
Moqapi example e fumaneha feela ka mokhoa oa duplex bakeng sa mefuta ea Base le PHY. U ka khetha Base feela kapa PHY e fapaneng feela empa IP e tla hlahisa moralo oa example bakeng sa bobeli Base le PHY.

Hlokomela:  Litlhophiso tse ling tsa sekhahla sa data se phahameng li ka hloleha ho boloka nako. Ho qoba ho hloleha ha nako, nahana ka ho hlakisa boleng bo tlase ba ho atisa oache ea nako (FCLK_MULP) ho "Configurations" tab ya F-Tile JESD204C Intel FPGA IP parameter editor.

Likaroloana tsa Tsamaiso

Moetso oa F-Tile JESD204C example e fana ka phallo ea taolo e thehiloeng ho software e sebelisang yuniti ea taolo e thata e nang le ts'ehetso ea khomphutha ea sistimi kapa ntle le eona.

Moqapi example e nolofalletsa khokahano ea auto ho ea ka mekhoa ea ka hare le ea kantle ea loopback.

JTAG ho ea Avalon Master Bridge
Leano la JTAG ho Avalon Master Bridge e fana ka khokahano lipakeng tsa sistimi e amohelang batho ho fihlella F-Tile JESD204C IP e hahelletsoeng ka mohopolo le taolo ea IP ea peripheral le ngoliso ea maemo ka J.TAG segokahanyi.

Setšoantšo sa 6. Sistimi e nang le JTAG ho Avalon Master Bridge Core

Hlokomela:  Oache ea sistimi e tlameha ho ba bonyane 2X kapele ho feta JTAG oache. Oache ea sistimi ke mgmt_clk (100MHz) molemong oa mohlala onaample.

F-Tile-JESD204C-Intel-FPGA-IP-Design-Example-06Parallel I/O (PIO) Core
The parallel input/output (PIO) konokono le segokanyimmediamentsi sa sebolokigolo sa Avalon se fana ka segokanyimmediamentsi sa memori pakeng tsa boema-kepe ba makgoba bo nang le mohopolo wa Avalon le boema-kepe ba I/O ka kakaretso. Likou tsa I/O li hokahana le mohopolo oa mosebelisi oa on-chip, kapa li-pin tsa I/O tse hokelang lisebelisoa tse kantle ho FPGA.

Setšoantšo sa 7. PIO Core e nang le Boema-kepe ba Lintho Tse Kenang, Boema-kepe ba Lintho, le Tšehetso ea IRQ
Ka linako tsohle, karolo ea Moqapi oa Platform e tima Interrupt Service Line (IRQ).

F-Tile-JESD204C-Intel-FPGA-IP-Design-Example-07Boema-kepe ba PIO I/O bo abetsoe maemong a holimo a HDL file (io_ boemo ba likou tsa ho kenya, taolo ea io_ bakeng sa likou tse hlahisoang).

Tafole e ka tlase e hlalosa khokahano ea lets'oao bakeng sa boemo le boema-kepe ba I/O ho switch ea DIP le LED ho kit ea nts'etsopele.

Letlapa la 8. PIO Core I/O Ports

Boema-kepe Bit Letshwao
Out_port 0 USER_LED ho etsoa mananeo a SPI
31:1 Reserved
Ka_boemakepeng 0 USER_DIP ka hare ho serial loopback e nolofalletsa Off = 1
Ho = 0
1 USER_DIP SYSREF e hlahisitsoeng ke FPGA e nolofalletsa Ho tima = 1
Ho = 0
31:2 Reserved.

SPI Master
Mojule o moholo oa SPI ke karolo e tloaelehileng ea Moqapi oa Platform ho laeborari ea maemo a IP Catalog. Mojule ona o sebelisa protocol ea SPI ho thusa ho hlophisoa ha li-converter tsa kantle (mohlalaample, ADC, DAC, le lijenereithara tsa oache tsa kantle) ka sebaka sa ngoliso se hlophisitsoeng kahare ho lisebelisoa tsena.

Monghali oa SPI o na le sebopeho sa 'mapa sa mohopolo oa Avalon se hokelang ho master ea Avalon (JTAG ho Avalon master bridge) ka khokahano ea 'mapa oa mohopolo oa Avalon. Monghali oa SPI o fumana litaelo tsa tlhophiso ho tsoa ho master ea Avalon.

SPI master module e laola ho fihla ho makhoba a 32 a ikemetseng a SPI. Sekhahla sa SCLK baud se lokiselitsoe ho 20 MHz (e arohanngoa ke 5).
Mojule ona o hlophisitsoe hore e be segokanyimmediamentsi sa 4-wire, 24-bit wide. Haeba khetho ea Hlahisa 3-Wire SPI Module e khethiloe, mojule oa tlatsetso oa hlomelloa ho fetolela tlhahiso ea terata e 4 ea master ea SPI ho terata e 3.

IOPLL
IOPLL e hlahisa oache e hlokahalang ho hlahisa frame_clk le link_clk. Oache ea litšupiso ho PLL e ka lokisoa empa e lekantsoe ho sekhahla sa data / ntlha ea 33.

  • Bakeng sa moralo example e tšehetsang sekhahla sa data sa 24.33024 Gbps, sekhahla sa oache bakeng sa frame_clk le link_clk ke 368.64 MHz.
  • Bakeng sa moralo example e tšehetsang sekhahla sa data sa 32 Gbps, sekhahla sa oache bakeng sa frame_clk le link_clk ke 484.848 MHz.

Jenereithara ea SYSREF
SYSREF ke lets'oao la bohlokoa la nako bakeng sa li-converter tsa data tse nang le sebopeho sa F-Tile JESD204C.

Jenereithara ea SYSREF moetsong oa example e sebelisetsoa morero oa pontšo oa ho qala lihokelo tsa JESD204C IP feela. Ts'ebelisong ea boemo ba sistimi ea JESD204C subclass 1, o tlameha ho hlahisa SYSREF ho tsoa mohloling o tšoanang le oache ea sesebelisoa.

Bakeng sa F-Tile JESD204C IP, SYSREF multiplier (SYSREF_MULP) ea rejisetara ea taolo ea SYSREF e hlalosa nako ea SYSREF, e leng n-integer multiple ea paramethara ea E.

U tlameha ho netefatsa hore E*SYSREF_MULP ≤16. Bakeng sa mohlalaample, haeba E=1, dipeakanyo tsa molao tsa SYSREF_MULP di tlameha ho ba ka hare ho 1–16, mme haeba E=3, dipeakanyo tsa molao tsa SYSREF_MULP di tlameha ho ba ka hare ho 1–5.

Hlokomela:  Haeba u seta SYSREF_MULP e tsoileng tseleng, jenereithara ea SYSREF e tla lokisa litlhophiso ho SYSREF_MULP=1.
U ka khetha hore na u batla hore mofuta oa SYSREF e be molumo o le mong, oa nakoana kapa oa nakoana ka Ex.ample Design tab ho F-Tile JESD204C Intel FPGA IP parameter mohlophisi.

Lethathamo la 9. Examples of Periodic and Gapped Periodic SYSREF Counter

E SYSREF_MULP SYSREF NAKO

(E*SYSREF_MULP* 32)

 Duty Cycle Tlhaloso
1 1 32 1..31
(Ke lenaneo)		 Gapped Periodic
1 1 32 16
(E tsitsitse)		 Nako le nako
1 2 64 1..63
(Ke lenaneo)		 Gapped Periodic
1 2 64 32
(E tsitsitse)		 Nako le nako
1 16 512 1..511
(Ke lenaneo)		 Gapped Periodic
1 16 512 256
(E tsitsitse)		 Nako le nako
2 3 19 1..191
(Ke lenaneo)		 Gapped Periodic
2 3 192 96
(E tsitsitse)		 Nako le nako
2 8 512 1..511
(Ke lenaneo)		 Gapped Periodic
2 8 512 256
(E tsitsitse)		 Nako le nako
2 9
(E seng molaong)		 64 32
(E tsitsitse)		 Gapped Periodic
2 9
(E seng molaong)		 64 32
(E tsitsitse)		 Nako le nako

 

Lethathamo la 10. SYSREF Control Registers
O ka khona ho hlophisa bocha lirejisete tsa taolo tsa SYSREF haeba litlhophiso tsa registara li fapane le litlhophiso tseo u li boletseng ha u ne u etsa moralo oa ex.ample. Beakanya lirejisete tsa SYSREF pele F-Tile JESD204C Intel FPGA IP e felile. Haeba u khetha jenereithara ea kantle ea SYSREF ka ho
sysref_ctrl[7] ngodisa hanyane, o ka iphapanyetsa litlhophiso tsa mofuta oa SYSREF, multiplier, duty cycle le phase.

Bits Boleng ba kamehla Tlhaloso
sysref_ctrl[1:0]
  • 2'b00: Thunya e le 'ngoe
  • 2'b01: Nako le nako
  • 2'b10: Nako le nako e arohaneng
 Mofuta oa SYSREF.

Boleng ba kamehla bo ipapisitse le maemo a SYSREF ho Example Design tab ho F-Tile JESD204C Intel FPGA IP parameter mohlophisi.
sysref_ctrl[6:2] 5b00001 SYSREF e ngatafatsa.

Sebaka sena sa SYSREF_MULP se sebetsa ho mofuta oa SYSREF oa nakoana le oa nakoana.

U tlameha ho lokisa boleng ba multiplier ho netefatsa hore boleng ba E*SYSREF_MULP bo pakeng tsa 1 ho isa ho 16 pele F-Tile JESD204C IP e tsoa ho seta bocha. Haeba boleng ba E*SYSREF_MULP bo le kantle ho mofuta ona, boleng ba se atisang ho fetoha 5'b00001.
sysref_ctrl[7]
  • Lenaneo la data la Duplex: 1'b1
  • Simplex TX kapa RX datapath: 1'b0
 SYSREF khetha.

Boleng ba kamehla bo itšetlehile ka tlhophiso ea tsela ea data ho Example Design tab ho F-Tile JESD204C Intel FPGA IP parameter mohlophisi.

  • 0: Simplex TX kapa RX (Kantle SYSREF)
  • 1: Duplex (SYSREF ea ka hare)
sysref_ctrl[16:8] 9h0 Potoloho ea mosebetsi oa SYSREF ha mofuta oa SYSREF e le oa nakoana kapa oa nakoana.

U tlameha ho lokisa potoloho ea mosebetsi pele F-Tile JESD204C IP e tsoa ho seta bocha.

Boleng bo kaholimo = (E*SYSREF_MULP*32)-1 Bakeng sa mohlalaampLe:

50% potoloho ea mosebetsi = (E*SYSREF_MULP*32)/2

Potoloho ea mosebetsi e ea ho 50% haeba u sa lokise sebaka sena sa ngoliso, kapa haeba u lokisa sebaka sa ngoliso ho 0 kapa ho feta boleng bo phahameng bo lumelletsoeng.
sysref_ctrl[17] 1b0 Taolo ea letsoho ha mofuta oa SYSREF o le thunya e le 'ngoe.
  • Ngola 1 ho beha lets'oao la SYSREF holimo.
  • Ngola 0 ho beha lets'oao la SYSREF tlase.

U hloka ho ngola 1 ebe 0 ho theha molumo oa SYSREF ka mokhoa o le mong oa ho thunya.
sysref_ctrl[31:18] 22h0 Reserved.

Seta Sequencers bocha
Moqapi ona example e na le tse peli tse reset sequencers:

  • Reset Sequence 0-E sebetsana le ho reset ho TX/RX Avalon streaming domain, Avalon memory-mapped domain, core PLL, TX PHY, TX core, le SYSREF jenereithara.
  • Seta Botjha Tatelano 1-E sebetsana le ho seta botjha ho RX PHY le RX Core.

SPI ea terata e 3
Mojule ona ke oa boikhethelo ho fetolela sebopeho sa SPI ho terata e 3.

Sistimi ea PLL
F-tile e na le li-PLL tse tharo tsa on-board system. Sistimi ena ea PLL ke mohloli oa mantlha oa oache oa IP e thata (MAC, PCS, le FEC) le EMIB ho tšela. Sena se bolela hore, ha o sebelisa mokhoa oa ho koala oa PLL, li-block ha li koetsoe ke oache ea PMA 'me ha li itšetlehe ka oache e tsoang mokokotlong oa FPGA. Sistimi ka 'ngoe ea PLL e hlahisa oache feela e amanang le sebopeho se le seng sa frequency. Bakeng sa mohlalaample, o hloka li-PLL tse peli tsa sistimi ho tsamaisa sehokelo se le seng ho 1 GHz le sehokelo se le seng ho 500 MHz. Ho sebelisa sistimi ea PLL ho u lumella ho sebelisa tsela e 'ngoe le e' ngoe ka boikemelo ntle le phetoho ea oache e amang tsela e haufi.
Sistimi e 'ngoe le e' ngoe ea PLL e ka sebelisa lioache tse robeli tsa litšupiso tsa FGT. Li-PLL tsa Sisteme li ka arolelana oache kapa li na le lioache tse fapaneng tsa litšupiso. Khokahano e 'ngoe le e' ngoe e ka khetha hore na e sebelisa sistimi efe ea PLL, empa, hang ha e khethiloe, e tsitsitse, ha e lokisoe bocha ho sebelisoa tlhophiso e matla.

Lintlha Tse Amanang
F-tile Architecture le PMA le FEC Direct PHY IP User Guide

Lintlha tse ling mabapi le mokhoa oa ho koala oa PLL ho lisebelisoa tsa Intel Agilex F-tile.

Jenereithara ea mohlala le Checker
Mohlala oa jenereithara le sehlahlobi li na le thuso bakeng sa ho theha data sample ho beha leihlo bakeng sa liteko.
Letlapa la 11. Jenereithara ea Paterone e Tšehetsoeng

Jenereithara ea mohlala Tlhaloso
PRBS mohlala jenereithara Moetso oa F-Tile JESD204C exampjenereithara ea mohlala ea PRBS e tšehetsa tekanyo e latelang ea polynomials:
  • PRBS23: X23+X18+1
  • PRBS15: X15+X14+1
  • PRBS9: X9+X5+1
  • PRBS7: X7+X6+1
Ramp jenereithara ea mohlala The ramp keketso ea boleng ba mohlala ka 1 bakeng sa lets le leng le le leng le latelangample bophara ba jenereithara ea N, 'me e fetela ho 0 ha likotoana tsohle li le sampke 1.

Etsa hore ramp jenereithara ea mohlala ka ho ngola 1 ho bit 2 ea tst_ctl registareng ea ED control block.
Laela mocha ramp jenereithara ea mohlala Moetso oa F-Tile JESD204C example e ts'ehetsa mocha oa taelo ramp jenereithara ea mohlala ka lane. The ramp paterone boleng increments ka 1 ka likotoana tse 6 tsa mantsoe a taelo.

Peo ea ho qala ke mokhoa oa ho eketseha ho pholletsa le litsela tsohle.

Letlapa la 12. Mohlahlobi oa Paterone o Tšehetsoeng

Mokhoa oa ho hlahloba mohlala Tlhaloso
Mohlahlobi oa mohlala oa PRBS Peo e ts'oarellang sehlahlobing sa mohlala e ikamahanya le eona ha F-Tile JESD204C IP e fihlella tlhophiso ea deskew. Sehlahlobi sa mohlala se hloka li-octet tse 8 hore peō e harolang e ikamahanye.
Ramp sehlahlobi sa mohlala Lintlha tsa pele tse nepahetseng sample bakeng sa converter ka 'ngoe (M) e laeloa e le boleng ba pele ba ramp mohlala. Lintlha tse latelang sampLes boleng bo tlameha ho eketseha ka 1 nakong ea oache e 'ngoe le e 'ngoe ho ea holimo ebe o fetela ho 0.
Mokhoa oa ho hlahloba mohlala Tlhaloso
Bakeng sa mohlalaample, ha S=1, N=16 le WIDTH_MULP = 2, bophara ba data ka converter ke S * WIDTH_MULP * N = 32. The maximum data sampboleng ba le ke 0xFFFF. The ramp Paterone checker e netefatsa hore lipaterone tse tšoanang lia amoheloa ho li-converter tsohle.
Laela mocha ramp sehlahlobi sa mohlala Moetso oa F-Tile JESD204C example e ts'ehetsa mocha oa taelo ramp sehlahlobi sa mohlala. Lentsoe la pele la taelo (6 bits) le amoheloang le laetsoe e le boleng ba pele. Mantsoe a latelang a taelo ka tsela e tšoanang a tlameha ho nyolohela ho 0x3F ebe o fetela ho 0x00.

Kanale ea taelo ramp sehlahlobi sa mohlala se hlahloba ramp mekhoa ea litsela tsohle.

F-Tile JESD204C TX le RX IP
Moqapi ona exampLe e o lumella ho hlophisa TX/RX ka 'ngoe ka mokhoa o bonolo kapa oa duplex.
Litlhophiso tsa Duplex li lumella pontšo ea ts'ebetso ea IP ho sebelisa serial loopback ea kahare kapa kantle. Li-CSR ka har'a IP ha lia ntlafatsoa hole ho lumella taolo ea IP le ho shebella maemo.

F-Tile JESD204C Design Example Clock le Reset

Moetso oa F-Tile JESD204C example na le sete ea oache le ho seta matshwao botjha.

Lethathamo la 13.Moqapi Example Lioache

Letšoao la oache Tataiso Tlhaloso
mgmt_clk Kenyeletso Oache e fapaneng ea LVDS e nang le maqhubu a 100 MHz.
refclk_xcvr Kenyeletso Oache ea litšupiso ea Transceiver e nang le maqhubu a sekhahla sa data / ntlha ea 33.
refclk_core Kenyeletso Oache ea mantlha e nang le maqhubu a tšoanang le a

refclk_xcvr.
ho_sysref Kenyeletso Letšoao la SYSREF.

Boholo ba maqhubu a SYSREF ke sekhahla sa data/(66x32xE).
sysref_out Sephetho
txlink_clk rxlink_clk Ka hare Oache ea khokahano ea TX le RX e nang le sekhahla sa sekhahla sa data/66.
txframe_clk rxframe_clk Ka hare
  • TX le RX foreimi oache e nang le khafetsa sekhahla sa data/33 (FCLK_MULP=2)
  • TX le RX foreimi oache e nang le khafetsa sekhahla sa data/66 (FCLK_MULP=1)
tx_fclk rx_fclk Ka hare
  • TX le RX mohato oache e nang le maqhubu a sekhahla sa data/66 (FCLK_MULP=2)
  • TX le RX phase clock li lula li le holimo (1'b1) ha FCLK_MULP=1
spi_SCLK Sephetho SPI baud rate oache e nang le maqhubu a 20 MHz.

Ha o laela moralo example ho sesebelisoa sa FPGA, ketsahalo ea ka hare ninit_done e tiisa hore JTAG ho Avalon Master borokho bo se bo le teng hammoho le li-blocks tse ling kaofela.

Jenereithara ea SYSREF e na le reset ea eona e ikemetseng ho kenya kamano ea ka boomo ea asynchronous bakeng sa lioache tsa txlink_clk le rxlink_clk. Mokhoa ona o pharalletse haholoanyane mabapi le ho etsisa lets'oao la SYSREF ho tsoa ho chip ea oache e kantle.

Lethathamo la 14. Moqapi Example Resets

Seta Lets'oao bocha Tataiso Tlhaloso
global_rst_n Kenyeletso Tobetsa konopo ea lefats'e bakeng sa li-blocks tsohle, ntle le JTAG ho ea borokhong ba Avalon Master.
Ninit_etsa Ka hare Se hlahisoang ho tsoa ho Reset Release IP bakeng sa JTAG ho ea borokhong ba Avalon Master.
edctl_rst_n Ka hare Sebaka sa ED Control se setiloe bocha ke JTAG ho ea borokhong ba Avalon Master. Boema-kepe ba hw_rst le global_rst_n ha bo boele ba seta ED Control block.
hw_rst Ka hare Assert and dessert hw_rst ka ho ngolla rst_ctl rejisetara ea ED Control block. mgmt_rst_in_n e tiisa ha hw_rst e tiisitsoe.
mgmt_rst_in_n Ka hare Seta bocha bakeng sa li-interface tsa Avalon tse nang le 'mapa oa mohopolo oa li-IP tse fapaneng le likenyelletso tsa li-sequencers tsa reset:
  •  j20c_reconfig_reset bakeng sa F-Tile JESD204C IP duplex Native PHY
  • spi_rst_n bakeng sa SPI master
  • pio_rst_n bakeng sa boemo le taolo ea PIO
  • reset_in0 koung ea reset sequencer 0 le 1 The global_rst_n, hw_rst, or edctl_rst_n port assserts e tla qala bocha ho mgmt_rst_in_n.
sysref_rst_n Ka hare Seta bocha bakeng sa block ea jenereithara ea SYSREF ka har'a ED Control block u sebelisa sequencer reset 0 reset_out2 port. Reset sequencer 0 reset_out2 port deassserts haeba PLL ea mantlha e notletsoe.
mantlha_pll_rst Ka hare E tsosolosa PLL ea mantlha ka sequencer ea reset 0 reset_out0 port. PLL ea mantlha e qala hape ha mgmt_rst_in_n reset e tiisitsoe.
j204c_tx_avs_rst_n Ka hare E seta botjha sebopeho sa memori sa F-Tile JESD204C TX Avalon-mapped ka ho seta botjha sequencer 0. TX Avalon memory-mapped interface e tiisa ha mgmt_rst_in_n e tiiswa.
j204c_rx_avs_rst_n Ka hare E seta botjha sebopeho sa memori sa F-Tile JESD204C TX Avalon-mapped ka sequencer reset 1. RX Avalon memory-mapped interface e tiisa ha mgmt_rst_in_n e tiisetswa.
j204c_tx_rst_n Ka hare E tsosolosa sehokelo sa F-Tile JESD204C TX le likarolo tsa lipalangoang ho txlink_clk, le txframe_clk, libaka.

Sequencer reset 0 reset_out5 port reset j204c_tx_rst_n. Seta sena se secha ha PLL ea mantlha e notletsoe, 'me matšoao a tx_pma_ready le tx_ready a tiisitsoe.
j204c_rx_rst_n Ka hare E seta botjha sehokelo sa F-Tile JESD204C RX le dikarolo tsa dipalangwang ho, rxlink_clk, le rxframe_clk.
Seta Lets'oao bocha Tataiso Tlhaloso
Sequencer 1 reset_out4 port reset j204c_rx_rst_n. Seta sena se secha ha PLL ea mantlha e notletsoe, 'me matšoao a rx_pma_ready le rx_ready a tiisitsoe.
j204c_tx_rst_ack_n Ka hare Seta bocha lets'oao la ho ts'oarana ka matsoho ka j204c_tx_rst_n.
j204c_rx_rst_ack_n Ka hare Seta bocha lets'oao la ho ts'oarana ka matsoho ka j204c_rx_rst_n.

Setšoantšo sa 8. Setšoantšo sa Nako bakeng sa Moralo Example ResetsF-Tile-JESD204C-Intel-FPGA-IP-Design-Example-08

F-Tile JESD204C Design Example Lipontšo

Letlapa la 15. Lipontšo tsa Sebopeho sa Tsamaiso

Letshwao Tataiso Tlhaloso
Lioache le Resets
mgmt_clk Kenyeletso 100 MHz oache bakeng sa tsamaiso ea tsamaiso.
refclk_xcvr Kenyeletso Oache ea litšupiso bakeng sa F-tile UX QUAD le System PLL. E lekana le sekhahla sa data/ntlha ea 33.
refclk_core Kenyeletso Oache ea boits'oaro ea Core PLL. E sebelisa maqhubu a oache joalo ka refclk_xcvr.
ho_sysref Kenyeletso Letšoao la SYSREF ho tsoa ho jenereithara ea kantle ea SYSREF bakeng sa ts'ebetsong ea JESD204C Subclass 1.
sysref_out Sephetho Letšoao la SYSREF bakeng sa ts'ebetsong ea JESD204C Subclass 1 e hlahisoang ke sesebelisoa sa FPGA bakeng sa moralo oa ex.ampsepheo sa ho qala feela.

 

Letshwao Tataiso Tlhaloso
SPI
spi_SS_n[2:0] Sephetho E sebetsa tlase, letšoao la khetho ea lekhoba la SPI.
spi_SCLK Sephetho SPI oache ea serial.
spi_sdio Kenyeletso/Sehlahisoa Lintlha tse tsoang ho mong'a tsona ho ea ho lekhoba la kantle. Kenya data ho tsoa ho lekhoba la kantle ho ea ho monghali.
Letshwao Tataiso Tlhaloso
Hlokomela:Ha Hlahisa 3-Wire SPI Module khetho e nolofalitsoe.
spi_MISO

Hlokomela: Ha Hlahisa 3-Wire SPI Module khetho ha e sebetse.

 Kenyeletso Kenya data ho tsoa ho lekhoba la kantle ho ea ho mong'a SPI.
spi_MOSI

Hlokomela: Ha Hlahisa 3-Wire SPI Module khetho ha e sebetse.

 Sephetho Lintlha tse hlahisoang ho tloha ho mong'a SPI ho ea ho lekhoba la kantle.

 

Letshwao Tataiso Tlhaloso
ADC / DAC
tx_serial_data[LINK*L-1:0]  

Sephetho

  

Lintlha tse fapaneng tsa serial tsa lebelo le phahameng ho DAC. Oache e kentsoe lethathamong la data la serial.
tx_serial_data_n[LINK*L-1:0]
rx_serial_data[LINK*L-1:0]  

Kenyeletso

  

Lintlha tse fapaneng tsa serial tsa lebelo le phahameng ho tsoa ho ADC. Oache e hlaphoheloa ho tswa ho serial data molapo.
rx_serial_data_n[LINK*L-1:0]

 

Letshwao Tataiso Tlhaloso
Kakaretso Morero I/O
mosebelisi [3:0]  

 

Sephetho

 E supa boemo ba maemo a latelang:
  • [0]: Lenaneo la SPI le entsoe
  • [1]: phoso ea khokahano ea TX
  • [2]: phoso ea khokahano ea RX
  • [3]: Phoso ea ho hlahloba mohlala bakeng sa data ea phallo ea Avalon
user_dip[3:0] Kenyeletso Kenyelletso ea phetoho ea DIP ea mosebelisi:
  • [0]: serial loopback ea ka hare e thusa
  • [1]: SYSREF e entsoeng ke FPGA e nolofalletsa
  • [3:2]: Behiloe

 

Letshwao Tataiso Tlhaloso
Out-of-band (OOB) le Boemo
rx_patchk_data_error[LINK-1:0] Sephetho Ha lets'oao lena le tiisitsoe, le bontša hore sehlahlobi sa mohlala se fumane phoso.
rx_link_error[LINK-1:0] Sephetho Ha lets'oao lena le tiisitsoe, le bontša hore JESD204C RX IP e tiisitse tšitiso.
tx_link_error[LINK-1:0] Sephetho Ha lets'oao lena le tiisitsoe, le bontša hore JESD204C TX IP e tiisitse tšitiso.
emb_lock_out Sephetho Ha lets'oao lena le tiisitsoe, le bontša hore JESD204C RX IP e fihletse senotlolo sa EMB.
sh_lock_out Sephetho Ha lets'oao lena le tiisitsoe, le bontša hore hlooho ea sync ea JESD204C RX IP e notletsoe.

 

Letshwao Tataiso Tlhaloso
Phallo ea Avalon
rx_avst_valid[LINK-1:0] Kenyeletso E bontša hore na converter sampLe data ho karolo ea ts'ebeliso e nepahetse kapa ha e sebetse.
  • 0: Lintlha ha li sebetse
  • 1: Lintlha li nepahetse
rx_avst_data[(TOTAL_SAMPLE*N)-1:0

]

 Kenyeletso Mofetoleli sample data ho lera la kopo.
F-Tile JESD204C Design Example Control Registers

Moetso oa F-Tile JESD204C example registe ho ED Control block sebelisa byte-addressing (32 bits).

Lethathamo la 16. Moqapi Example Aterese Map
Lirekoto tsena tsa 32-bit ED Control block li sebakeng sa mgmt_clk.

Karolo Aterese
F-Tile JESD204C TX IP 0x000C_0000 – 0x000C_03FF
F-Tile JESD204C RX IP 0x000D_0000 – 0x000D_03FF
Taolo ea SPI 0x0102_0000 – 0x0102_001F
Taolo ea PIO 0x0102_0020 – 0x0102_002F
Boemo ba PIO 0x0102_0040 – 0x0102_004F
Seta Sequencer 0 bocha 0x0102_0100 – 0x0102_01FF
Seta Sequencer 1 bocha 0x0102_0200 – 0x0102_02FF
ED Control 0x0102_0400 – 0x0102_04FF
F-Tile JESD204C IP transceiver PHY Reconfig 0x0200_0000 – 0x023F_FFFF

Letlapa la 17. Mofuta oa Phihlelo ea Ngoliso le Tlhaloso
Tafole ena e hlalosa mofuta oa phihlello ea ngoliso bakeng sa Intel FPGA IPs.

Mofuta oa ho fihlella Tlhaloso
RO/V Software bala-feela (ha ho na phello ho ngola). Boleng bo ka fapana.
RW
  • Software e bala le ho khutlisa boleng ba hona joale ba biti.
  • Software e ngola le ho seta bonyenyane ho boleng bo lakatsehang.
RW1C
  • Software e bala le ho khutlisa boleng ba hona joale ba biti.
  • Software e ngola 0 mme ha e na phello.
  • Software e ngola 1 mme e hlakola hanyane ho 0 haeba hanyane e behiloe ho 1 ka hardware.
  • Hardware e beha palo ho 1.
  • Software clear e na le bohlokoa bo holimo ho feta hardware set.

Letlapa la 18. ED Control Address Map

Offset Ngolisa Lebitso
0x00 pele_ctl
0x04 rst_st0
e tsoela pele…
Offset Ngolisa Lebitso
0x10 rst_sts_detected0
0x40 sysref_ctl
0x44 sysref_sts
0x80 tst_ctl
0x8c tst_err0

Letlapa la 19. ED Control Block Control le Status Registers

Byte Offset Ngodisa Lebitso Phihlello Seta bocha Tlhaloso
0x00 pele_ctl pele_assert RW 0x0 Seta taolo bocha. [0]: Ngola 1 ho etsa boipiletso botjha. (hw_rst) Ngola 0 hape ho etsa dessert reset. [31:1]: Behiloe.
0x04 rst_st0 boemo_ba_ba pele RO/V 0x0 Seta boemo bocha. [0]: Boemo bo notletsoeng ba Core PLL. [31:1]: Behiloe.
0x10 rst_sts_dete cted0 rst_sts_set RW1C 0x0 Boemo ba SYSREF ba ho lemoha ka hare kapa kantle ho jenereithara ea SYSREF. [0]: Boleng ba 1 bo bonts'a hore SYSREF e phahama e bonoa bakeng sa ts'ebetso ea sehlopha sa 1. Software e kanna ea ngola 1 ho hlakola sekhechana sena ho thusa SYSREF e ncha ea ho lemoha. [31:1]: Behiloe.
0x40 sysref_ctl sysref_contr ol RW Duplex datapath
  • Setšoantšo se le seng: 0x00080
 SYSREF taolo.

Sheba Lethathamo la 10 leqepheng la 17 bakeng sa lintlha tse ling mabapi le tšebeliso ea rejisetara ena.
Nako le nako: Hlokomela: Boleng ba ho tsosolosa bo itšetlehile ka
0x00081 mofuta oa SYSREF le F-Tile
Nako le nako: Litlhophiso tsa tsela ea data ea JESD204C IP.
0x00082
TX kapa RX data
tsela
Thunya e le 'ngoe:
0x00000
Nako le nako:
0x00001
Sekhao-
nako le nako:
0x00002
0x44 sysref_sts sysref_statu s RO/V 0x0 Boemo ba SYSREF. Ngoliso ena e na le nako ea morao-rao ea SYSREF le litlhophiso tsa potoloho ea mosebetsi tsa jenereithara ea kahare ea SYSREF.

Sheba Lethathamo la 9 leqepheng la 16 bakeng sa boleng ba molao ba nako ea SYSREF le potoloho ea mosebetsi.
e tsoela pele…
Byte Offset Ngodisa Lebitso Phihlello Seta bocha Tlhaloso
[8:0]: nako ea SYSREF.
  • Ha boleng e le 0xFF, the
    Nako ea SYSREF = 255
  • Ha boleng haeba 0x00, nako ea SYSREF = 256. [17:9]: SYSREF duty cycle. [31:18]: Behiloe.
0x80 tst_ctl tst_control RW 0x0 Taolo ea teko. Sebelisa rejisetara ena ho thusa lipaterone tse fapaneng tsa liteko bakeng sa jenereithara le sehlahlobi. [1:0] = Tšimo e bolokiloeng [2] = ramp_test_ctl
  • 1'b0 = E nolofalletsa jenereithara le sehlahlobi sa PRBS
  • 1'b1 = E nolofalletsa ramp mohlala jenereithara le checker
[31:3]: Behiloe.
0x8c tst_err0 tst_phoso RW1C 0x0 Folakha ea phoso bakeng sa Sehokelo sa 0. Ha karoloana e le 1'b1, e bontša hore phoso e etsahetse. U lokela ho rarolla phoso pele u ngola 1'b1 ho karolo e fapaneng ho hlakola folakha ea phoso. [0] = Phoso ea ho hlahloba mohlala [1] = tx_link_error [2] = rx_link_error [3] = Phoso ea ho hlahloba mohlala oa taelo [31:4]: E bolokiloe.

Nalane ea Phetoho ea Litokomane bakeng sa F-Tile JESD204C Intel FPGA IP Design Example Bukana ea Mosebelisi

Tokomane Version Intel Quartus Prime Version IP Version Liphetoho
2021.10.11 21.3 1.0.0 Tokollo ea pele.

Litokomane / Lisebelisoa

Intel F-Tile JESD204C Intel FPGA IP Design Example [pdf] Bukana ea Mosebelisi
F-Tile JESD204C Intel FPGA IP Design Example, F-Tile JESD204C, Intel FPGA IP Design Example, IP Design Example, Moqapi Example

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