F-Tile JESD204C Intel FPGA IP Design Example

Banyere F-Tile JESD204C Intel® FPGA IP Design Example ntuziaka onye ọrụ

Ntuziaka onye ọrụ a na-enye atụmatụ, ntuziaka ojiji, na nkọwa zuru ezu gbasara imewe examples maka F-Tile JESD204C Intel® FPGA IP site na iji ngwaọrụ Intel Agilex™.

Ndị na-ege ntị e bu n'obi

Ezubere akwụkwọ a maka:

• Chepụta onye na-ese ụkpụrụ ụlọ iji mee nhọrọ IP n'oge nhazi nhazi ọkwa sistemụ
• Ndị na-emepụta ngwaike mgbe ha na-ejikọta IP n'ime nhazi ọkwa ha
• Ndị injinia na-akwado n'oge ịme anwansị ọkwa sistemu yana oge nkwado ngwaike

Akwụkwọ ndị emetụtara
Tebụlụ na-esote depụtara akwụkwọ ntụaka ndị ọzọ metụtara F-Tile JESD204C Intel FPGA IP.

Tebụl 1. Akwụkwọ ndị metụtara ya

Ntụaka	Nkọwa
F-Tile JESD204C ntuziaka onye ọrụ IP FPGA	Na-enye ozi gbasara F-Tile JESD204C Intel FPGA IP.
F-Tile JESD204C Intel FPGA IP ndetu mwepụta	Na-edepụta mgbanwe ndị emere maka F-Tile JESD204C F-Tile JESD204C n'otu ntọhapụ.
Akwụkwọ data ngwaọrụ Intel Agilex	Akwụkwọ a na-akọwa njirimara eletrik, njirimara mgbanwe, nkọwa nhazi, na oge maka ngwaọrụ Intel Agilex.

Acronyms na Nkọwapụta

Tebụl 2. Ndepụta mkpọ okwu

Mkpọchi okwu	Mgbasawanye
LEMC	Elekere Multiblock gbatịrị mpaghara
FC	Ọnụego elekere etiti
ADC	Ihe Ntụgharị Analog ka Dijitalụ
DAC	Ihe ntụgharị dijitalụ ka ọ bụrụ Analog
DSP	Ihe nrụpụta mgbama dijitalụ
TX	Nnyefe
RX	Onye nnata

Mkpọchi okwu	Mgbasawanye
DLL	Nkọwa njikọ data
CSR	Njikwa na ndekọ ọkwa
CRU	Elekere na Tọgharịa nkeji
ISR	Kwụsị usoro mmemme
FIFO	Mbụ-Na-Mbụ-Mpụ
SERDES	Serializer Deserializer
ECC	Koodu mmezi mperi
FEC	Mmezi mperi n'ihu
SERR	Nchọpụta otu mperi (na ECC, enwere ike idozi)
DERR	Nchọpụta mperi ugboro abụọ (na ECC, na-egbu egbu)
PRBS	Usoro ọnụọgụ abụọ nke pseudorandom
MAC	Njikwa nnweta mgbasa ozi. MAC gụnyere protocol sublayer, iga oyi akwa, na data njikọ oyi akwa.
PHY	oyi akwa anụ ahụ. PHY na-agụnyekarị oyi akwa anụ ahụ, SERDES, ndị ọkwọ ụgbọ ala, ndị nnata na CDR.
PCS	Sub-layer nzuzo
PMA	Mgbakwụnye Ọkara Anụ ahụ
RBD	Ọdịda ihe nchekwa RX
UI	nkeji nkeji = oge nke serial bit
Ọnụọgụ RBD	RX Buffer Delay ụzọ mbata kacha ọhụrụ
Mgbanwe nke RBD	Ohere mwepụta RX Buffer
SH	Mmekọrịta nkụnye eji isi mee
TL	Layergbọ njem oyi akwa
EMIB	Agbanyere Multi-die Interconnect Bridge

Tebụl 3. Ndepụta nkọwa

Oge	Nkọwa
Ngwaọrụ Ntụgharị	ADC ma ọ bụ DAC ntụgharị
Ngwa mgbagha	FPGA ma ọ bụ ASIC
Ọkt	Otu 8 ibe n'ibe, na-eje ozi dị ka ntinye na 64/66 encoder na mmepụta sitere na decoder
Nibble	Ntọala nke 4 ibe n'ibe bụ isi ọrụ nke nkọwa JESD204C
Gbochie	Akara 66-bit nke atụmatụ ngbanwe 64/66 mepụtara
Ọnụọgụ ahịrị	Ọnụego data dị irè nke njikọ serial Ọnụ ụzọ ahịrị = (Mx Sx N'x 66/64 x FC) / L
Njikọ Elekere	Elekere njikọ = Ọnụ ụzọ ahịrị/66.
Frame	Otu octets dị n'usoro nke enwere ike mata ọnọdụ nke octet ọ bụla site na ntụnye aka na mgbama nhazi etiti.
Oge etiti	Elekere sistemu nke na-agba ọsọ n'ọ̀tụ̀tụ̀ etiti, nke ahụ ga-abụrịrị elekere njikọ 1x na 2x.

Oge	Nkọwa
Samples kwa etiti elekere	Samples kwa elekere, ngụkọta samples na etiti elekere maka ngwaọrụ ntụgharị.
LEMC	A na-eji elekere ime n'usoro n'usoro n'ókè nke multiblock gbatịrị n'etiti okporo ụzọ na n'ime ntụaka mpụga (SYSREF ma ọ bụ Subclass 1).
Klas nke obere 0	Enweghị nkwado maka latency deterministic. Ekwesịrị iwepụta data ozugbo n'okporo ụzọ gaa n'okporo ụzọ deskew na nnata.
Klas nke obere 1	Kpebisie ike latency iji SYSREF.
Njikọ Multipoint	Njikọ ngwaọrụ nwere ngwaọrụ ntụgharị abụọ ma ọ bụ karịa.
Ihe ngbanwe 64B/66B	Koodu ahịrị na-esetịpụ data 64-bit ka ọ bụrụ 66bit iji mepụta ngọngọ. Nhazi data larịị bụ ngọngọ na-amalite na nkụnye eji isi mee mmekọrịta 2-bit.

Isiokwu 4. Ihe nnọchianya

Oge	Nkọwa
L	Ọnụọgụ nke ụzọ kwa ngwaọrụ ntụgharị
M	Ọnụọgụ nke ndị ntụgharị n'otu ngwaọrụ
F	Ọnụọgụ nke octets kwa etiti n'otu ụzọ
S	Ọnụọgụ nke samples ebutere kwa otu Ntụgharị kwa etiti okirikiri
N	Mkpebi ntụgharị
N'	Ngụkọta ọnụọgụ nke ibe n'ibe kwa sample na onye ọrụ data usoro
CS	Ọnụọgụ njikwa n'otu ngbanwe sample
CF	Ọnụọgụ okwu njikwa kwa oge elekere etiti kwa njikọ
HD	Ụdị data onye ọrụ dị elu
E	Ọnụọgụ nke ọtụtụ ngọngọ na multiblock gbatịrị agbatị

F-Tile JESD204C Intel FPGA IP Design Exampna Ntuziaka mmalite ngwa ngwa

F-Tile JESD204C Intel FPGA IP imewe examples maka ngwaọrụ Intel Agilex na-egosipụta testbench simulating yana ngwaike na-akwado mkpokọta na nnwale ngwaike.
Ị nwere ike ịmepụta F-Tile JESD204C imewe examples site na katalọgụ IP dị na Intel Quartus® Prime Pro Edition software.

Ọgụgụ 1. Mmepe Stages maka imewe Example

Imepụta Example Block eserese

Ọgụgụ 2. F-Tile JESD204C Kere ExampEserese ngọngọ nke dị elu

Imewe example mejupụtara modul ndị a:

• Sistemụ Mmebe Platform
  • F-Tile JESD204C Intel FPGA IP
  • JTAG gaa Avalon Master bridge
  • Parallel I/O (PIO) njikwa
  • Oghere Usoro Port Interface (SPI) - modul ukwu- IOPLL
  • SYSREF jenerato
  • Example Design (ED) Control CSR
  • Tọgharịa usoro
• Sistemụ PLL
• Ụdị generator
• Nyocha ụkpụrụ

Tebụl 5. Imepụta Exampna modul

Ngwa	Nkọwa
Sistemụ Mmebe Platform	Sistemụ Onye nrụpụta Platform na-ewepụta ụzọ data F-Tile JESD204C IP yana akụkụ nkwado.
F-Tile JESD204C Intel FPGA IP	Nke a Platform Designer subsystem nwere TX na RX F-Tile JESD204C IPs jikọtara ya na duplex PHY.
JTAG gaa Avalon Master bridge	Àkwà mmiri a na-enye ndị ọbịa sistemu njikwa ohere ịnweta IP nke nwere ebe nchekwa na imewe site na JTAG interface.
Parallel I/O (PIO) njikwa	Ihe njikwa a na-enye interface-mapped ebe nchekwa maka sampling na ịnya ụgbọ mmiri izugbe I/O.
Onye isi SPI	Nke a modul na-ejikwa usoro mbufe data nhazi na interface SPI na njedebe ntụgharị.
SYSREF jenerato	Onye na-emepụta SYSREF na-eji elekere njikọ dị ka elekere ntụnye aka ma na-ewepụta SYSREF pulses maka F-Tile JESD204C IP. Mara: Nke a imewe example na-eji SYSREF jenerato iji gosi duplex F-Tile JESD204C IP njikọ mmalite. N'ime ngwa ọkwa F-Tile JESD204C subclass 1 sistemụ, ị ga-ewepụtarịrị SYSREF site n'otu ebe dị ka elekere ngwaọrụ.
IOPLL	Nke a imewe example na-eji IOPLL wepụta elekere onye ọrụ maka ịnyefe data n'ime F-Tile JESD204C IP.
ED Control CSR	Modul a na-enye njikwa nchọpụta SYSREF na ọkwa, yana nnwale njikwa na ọkwa.
Tọgharịa usoro	Nke a imewe example mejupụtara 2 nrụpụta usoro: Usoro Tọgharia 0-Jikwaa nrụpụta nrụpụta na ngalaba nkwanye TX/RX Avalon®, ngalaba ebe nchekwa Avalon, isi PLL, TX PHY, TX core, na generator SYSREF. Tọgharia Usoro 1-Jikwaa nrụpụta ahụ na RX PHY na RX isi.
Sistemụ PLL	Isi mmalite elekere maka F-tile hard IP na EMIB ngafe.
Ụdị generator	Ihe na-emepụta ụkpụrụ na-emepụta PRBS ma ọ bụ ramp ụkpụrụ.
Nyocha ụkpụrụ	Ihe nlele ụkpụrụ na-enyocha PRBS ma ọ bụ ramp enwetara ụkpụrụ, ma na-esetịpụ mperi mgbe ọ chọtara ndakọrịta nke data sample.

Ngwa ngwa chọrọ

Intel na-eji sọftụwia na-esonụ iji nwalee imewe exampN'ime sistemụ Linux:

• Intel Quartus Prime Pro Edition software
• Questa */ModelSim* ma ọ bụ VCS*/VCS MX simulator

Ịmepụta Nhazi

Iji mepụta imewe example site na nchịkọta akụkọ paramita IP:

1. Mepụta oru ngo ezubere iche maka ezinụlọ ngwaọrụ Intel Agilex F-tile wee họrọ ngwaọrụ achọrọ.
2. Na katalọgụ IP, Ngwaọrụ ➤ IP katalọgụ, họrọ F-Tile JESD204C Intel FPGA IP.
3. Ezipụta aha ọkwa dị elu yana nchekwa maka mgbanwe IP gị nke ọma. Pịa OK. Onye ndezi paramita na-agbakwụnye .ip file na oru ngo nke ugbu a na-akpaghị aka. Ọ bụrụ na a kpaliri gị iji aka tinye .ip file na oru ngo, pịa Project ➤ Tinye / Wepụ Files na Project ịgbakwunye ihe file.
4. N'okpuru Example Design tab, ezipụta imewe example parameters dị ka akọwara na Design Example Parameters.
5. Pịa n'ịwa Example Design.

Akụrụngwa na-emepụta ihe niile files na sub-directories. Ndị a files ka achọrọ iji mee simulation na nchịkọta.

Imepụta Example Parameters
F-Tile JESD204C Intel FPGA IP nchịkọta akụkọ paramita gụnyere Example Kere taabụ n'ihi na ị ezipụta ụfọdụ parameters tupu ha na imewe example.

Tebụl 6. Parameters na Example Design Tab

Oke	Nhọrọ	Nkọwa
Họrọ imewe	Njikwa njikwa sistemụ Ọ dịghị	Họrọ njikwa njikwa sistemu iji nweta imewe example data ụzọ site na sistemụ njikwa.
ịme anwansị	Gbanyụọ, Gbanyụọ	Gbanye maka IP ka ịmepụta ihe dị mkpa files maka simulating imewe example.
Synthesis	Gbanyụọ, Gbanyụọ	Gbanye maka IP ka ịmepụta ihe dị mkpa files maka mkpokọta Intel Quartus Prime na ngosipụta ngwaike.
Ụdị HDL (maka simulation)	Verilog VDHL	Họrọ ụdị HDL nke RTL files maka ịme anwansị.
Ụdị HDL (maka synthesis)	Verilog naanị	Họrọ ụdị HDL nke RTL files maka njikọ.

Oke	Nhọrọ	Nkọwa
Mepụta 3- waya SPI modul	Gbanyụọ, Gbanyụọ	Gbanwuo ka ị mee ka interface SPI nwere waya 3 kama ịbụ waya 4.
Ụdị Sysref	Otu ogbugba Nke oge Ogologo oge	Họrọ ma ịchọrọ nhazi SYSREF ka ọ bụrụ ụdị ụda ọkụ otu oge, nke oge ma ọ bụ nke nwere oghere, dabere na ihe ị chọrọ na ime mgbanwe oge. Otu-shot—Họrọ nhọrọ a iji mee ka SYSREF bụrụ ọnọdụ usu otu agba. The sysref_ctrl[17] aha bit uru bụ 0. Mgbe F-Tile JESD204C IP reset deasserts, gbanwee sysref_ctrl[17] aha uru site 0 gaa na 1, wee gaa na 0, maka otu-ise SYSREF usu. Oge oge—SYSREF n'ụdị oge nwere 50:50 okirikiri ọrụ. Oge SYSREF bụ E*SYSREF_MULP. Gapped periodic — SYSREF nwere usoro mmemme nke granularity nke okirikiri elekere 1 njikọ. Oge SYSREF bụ E*SYSREF_MULP. Maka ntọala okirikiri ọrụ na-anọghị nso, ngọngọ ọgbọ SYSREF ga-ewepụta okirikiri ọrụ 50:50 ozugbo. Tụtụ aka na SYSREF Generator ngalaba maka ozi ndị ọzọ gbasara SYSREF oge.
Họrọ osisi	Ọ dịghị	Họrọ osisi maka imewe example. Ọ dịghị — Nhọrọ a na-ewepu akụkụ ngwaike maka imewe example. A ga-edozi ọrụ ntụtụ niile ka ọ bụrụ ntụtụ mebere.
Ụkpụrụ ule	PRBS-7 PRBS-9 PRBS-15 PRBS-23 Ramp	Họrọ ụkpụrụ generator na checker ụkpụrụ ule. Ụdị Generator-JESD204C na-akwado PRBS ụkpụrụ generator kwa data sample. Nke a pụtara na obosara data bụ nhọrọ N+CS. PRBS ụkpụrụ generator na checker bara uru maka ịmepụta data sample mkpali maka ule na ọ dakọtara na PRBS ule mode na ADC/DAC Ntụgharị. Ramp Ụdị Generator-JESD204C njikọ oyi akwa na-arụ ọrụ nke ọma mana mbufe emechaa nwere nkwarụ ma na-eleghara ntinye sitere na nhazi usoro. Ụzọ ọ bụla na-ebufe iyi iyi octet yiri nke na-esi na 0x00 ruo 0xFF wee na-emegharị. Ramp prbs_test_ctl na-akwado ule ụkpụrụ. PRBS Pattern Checker-JESD204C PRBS scrambler na-emekọrịta onwe ya yana a na-atụ anya na mgbe isi IP nwere ike ịmekọrịta njikọ, mkpụrụ osisi na-emekọrịta ihe emekọrịtalarị. Mkpụrụ osisi PRBS ga-ewe octets 8 iji bido onwe ya. Ramp Onye na-enyocha ụkpụrụ-JESD204C scrambling na-emekọrịta onwe ya yana a na-atụ anya na mgbe isi IP ga-enwe ike ịmekọrịta njikọ elu, mkpụrụ osisi na-emekọrịta ihe emekọrịtalarị. A na-eburu octet izizi dị ka ramp uru mbụ. Data na-esote ga-abawanye ruo 0xFF wee tụgharịa gaa na 0x00. Ramp onye na-enyocha ụkpụrụ kwesịrị ịlele maka otu ụkpụrụ n'ofe ụzọ niile.
Kwado usoro loopback dị n'ime	Gbanyụọ, Gbanyụọ	Họrọ n'ime usoro loopback.
Kwado ọwa iwu	Gbanyụọ, Gbanyụọ	Họrọ ụkpụrụ ọwa iwu.

Ọdịdị ndekọ
F-Tile JESD204C imewe exampakwụkwọ ndekọ aha nwere emepụtara files maka imewe examples.

Onyonyo 3. Akwụkwọ ndekọ aha maka F-Tile JESD204C Intel Agilex Design Example

Tebụl 7. ndekọ Files

Mpempe akwụkwọ	Files
ed/rtl	tx j204c_f_tx_ip.qsys j204c_f tx_ss.qsys altera_s10_user_rst_clkgate_0.ip j204c f_se_outbuf_1bit.ip
ịme anwansị/ndụmọdụ	modelim_sim.tcl tb_top_waveform.do
ịme anwansị / synopsys	vcs vcs_sim.sh tb_top_wave_ed.do vcsmx vcsmx_sim.sh tb_top_wave_ed.do

Ịmepụta atụmatụ Exampna Testbench

Imewe example testbench simulates gị emepụtara imewe.

Ọgụgụ 4. Usoro

Iji mee ka imewe ahụ, mee usoro ndị a:

1. Gbanwee ndekọ ọrụ ka ọ bụrụample_design_directory>/ simulation/ .
2. N'ahịrị iwu, mee script simulation. Tebụlụ dị n'okpuru na-egosi iwu iji mee simulator akwadoro.

Simulator	Iwu
Questa/ModelSim	vsim -do modelim_sim.tcl
	vsim -c-do modelim_sim.tcl (na-enweghị Questa/ModelSim GUI)
VCS	sh vcs_sim.sh
VCS MX	sh vcsmx_sim.sh

Ihe ngosi a na-ejedebe na ozi na-egosi ma ọsọ ahụ ọ gara nke ọma ma ọ bụ na ọ garaghị nke ọma.

Onyonyo 5. Ntugharị na-aga nke ọma
Ọnụọgụ a na-egosi ozi ịme anwansị na-aga nke ọma maka simulator VCS.

Na-achịkọta Design Example

Iji chịkọta mkpokọta-naanị exampna project, soro usoro ndị a:

1. Gbaa mbọ hụ na nhazi mkpokọta example ọgbọ agwụla.
2. Na ngwanrọ Intel Quartus Prime Pro Edition, mepee ọrụ Intel Quartus Prime Pro Editionample_ design_ directory>/ed/quartus.
3. Na nhazi menu, pịa Malite Nchịkọta.

Nkọwa zuru ezu maka F-Tile JESD204C Design Example

F-Tile JESD204C imewe example na-egosi ọrụ nke data gụgharia site na iji loopback mode.
Ị nwere ike ezipụta ntọala paramita nke nhọrọ gị wee mepụta ihe nrụpụta example.
Imewe example dị naanị na ọnọdụ duplex maka ma Base na ụdị PHY. Ị nwere ike ịhọrọ naanị Base ma ọ bụ naanị PHY dị iche iche mana IP ga-emepụta ihe ngosi ahụample maka ma Base na PHY.

Mara:  Ụfọdụ nhazi ọnụego data dị elu nwere ike ịda n'oge. Iji zere ọdịda oge, tulee ịkọwapụta uru ugboro ugboro ugboro obere (FCLK_MULP) na taabụ Configuration nke F-Tile JESD204C Intel FPGA IP parameter editor.

Ngwa sistemu

F-Tile JESD204C imewe example na-enye usoro njikwa dabere na ngwanrọ nke na-eji ngalaba njikwa ike yana ma ọ bụ na-enweghị nkwado njikwa sistemụ.

Imewe exampna-enyere aka njikọ akpaaka na ime na mpụga loopback ụdịdị.

JTAG na Avalon Master Bridge
Ihe JTAG na Avalon Master Bridge na-enye njikọ n'etiti usoro nnabata iji nweta F-Tile JESD204C IP nke ebe nchekwa na-achịkwa yana njikwa ọnọdụ IP na ndekọ aha site na J.TAG interface.

Onyonyo 6. Sistemụ arụmọrụ nwere JTAG na Avalon Master Bridge Core

Mara:  Elekere sistemụ ga-abụrịrị opekata mpe 2X ọsọ ọsọ karịa JTAG elekere. Elekere sistemụ bụ mgmt_clk (100MHz) n'ime imewe a example.

Parallel I/O (PIO) isi
Ihe ntinye / mmepụta ihe (PIO) isi na interface Avalon na-enye ebe nchekwa ihe nchekwa n'etiti ọdụ ụgbọ mmiri Avalon ebe nchekwa na ọdụ ụgbọ mmiri I / O zuru oke. Ọdụ ụgbọ mmiri I/O na-ejikọta ma ọ bụ na mgbagha onye ọrụ on-chip, ma ọ bụ na pin I/O na-ejikọta na ngwaọrụ dị na mpụga FPGA.

Onyonyo 7. PIO Core nwere ọdụ ụgbọ mmiri ntinye, ọdụ ụgbọ mmiri, yana nkwado IRQ
Site na ndabara, akụrụngwa Onye nrụpụta Platform na-ewepụ ahịrị ọrụ nkwụsịtụ (IRQ).

A na-ekenye ọdụ ụgbọ mmiri PIO I/O na ọkwa HDL kacha elu file (ọkwa io_ maka ọdụ ụgbọ mmiri ntinye, njikwa io_ maka ọdụ ụgbọ mmiri mmepụta).

Tebụl dị n'okpuru na-akọwa njikọ mgbaàmà maka ọnọdụ na njikwa ọdụ ụgbọ mmiri I / O na mgba ọkụ DIP na LED na ngwa mmepe.

Isiokwu 8. PIO Core I/O Ports

Port	Bit	Signal
Ọpụpụ_ọdụ ụgbọ mmiri	0	USER_LED SPI emebere ya
	31:1	Echekwara
N'ọdụ ụgbọ mmiri	0	USER_DIP n'ime serial loopback na-enyere Gbanyụọ = 1 Na = 0
	1	USER_DIP FPGA mebere SYSREF gbanyụọ = 1 Na = 0
	31:2	Echekwara.

Onye isi SPI
SPI master modul bụ ihe eji arụ ọrụ Platform Designer na ọba akwụkwọ ọkọlọtọ IP katalọgụ. Modul a na-eji protocol SPI iji kwado nhazi nke ndị ntụgharị mpụga (maka example, ADC, DAC na ndị na-emepụta elekere mpụga) site na oghere aha ahaziri ahazi n'ime ngwaọrụ ndị a.

Nna-ukwu SPI nwere interface Avalon ebe nchekwa-mapped nke jikọtara na Avalon master (JTAG gaa Avalon master bridge) site na njikọ njikọ nke Avalon ebe nchekwa. Onye isi SPI na-enweta ntuziaka nhazi site n'aka onye nwe Avalon.

SPI master modul na-achịkwa ihe ruru ndị ohu SPI 32 nọọrọ onwe ha. A na-ahazi ọnụego baud SCLK ka ọ bụrụ 20 MHz (nke a na-ekewa site na 5).
A haziri modul a ka ọ bụrụ waya 4, obosara 24-bit. Ọ bụrụ na ahọpụtara nhọrọ Module Generate 3-Wire SPI, a na-etinye modul agbakwunyere ngwa ngwa iji gbanwee mmepụta 4-waya nke onye nwe SPI ka ọ bụrụ waya 3.

IOPLL
IOPLL na-ewepụta elekere achọrọ iji mepụta frame_clk na link_clk. A na-ahazi elekere elekere na PLL mana ọ bụ naanị na ọnụego / ihe kpatara data nke 33.

• Maka imewe exampnke na-akwado ọnụego data nke 24.33024 Gbps, ọnụego elekere maka frame_clk na link_clk bụ 368.64 MHz.
• Maka imewe exampnke na-akwado ọnụego data nke 32 Gbps, ọnụego elekere maka frame_clk na link_clk bụ 484.848 MHz.

SYSREF Generator
SYSREF bụ akara oge dị egwu maka ndị ntụgharị data nwere interface F-Tile JESD204C.

The SYSREF generator na imewe exampA na-eji le maka duplex JESD204C IP njikọ mmalite ngosipụta naanị. N'ime ngwa JESD204C subclass 1 sistemụ, ị ga-ewepụtarịrị SYSREF site na otu ebe elekere ngwaọrụ.

Maka F-Tile JESD204C IP, SYSREF multiplier (SYSREF_MULP) nke ndekọ njikwa SYSREF na-akọwa oge SYSREF, nke bụ n-integer multiple nke paramita E.

Ị ga-ahụrịrị E*SYSREF_MULP ≤16. Maka example, ọ bụrụ E=1, ntọala iwu maka SYSREF_MULP ga-abụrịrị n'ime 1–16, ma ọ bụrụ E=3, ọnọdụ iwu maka SYSREF_MULP ga-abụrịrị n'ime 1–5.

Mara:  Ọ bụrụ na ịtọọ SYSREF_MULP na-anọghị nso, onye nrụpụta SYSREF ga-edozi ntọala ahụ na SYSREF_MULP=1.
Ị nwere ike họrọ ma ịchọrọ ka ụdị SYSREF bụrụ otu mkpọ, oge, ma ọ bụ nke nwere oge site na Ex.ample Kere taabụ na F-Tile JESD204C Intel FPGA IP nchịkọta akụkọ paramita.

Tebụl 9. Examples nke oge na nke nwere oge SYSREF Counter

E	SYSREF_MULP	OGE SYSREF (E*SYSREF_MULP* 32)	Usoro ọrụ	Nkọwa
1	1	32	1..31 (Enwere ike ime mmemme)	Ogologo oge
1	1	32	16 (Edoziri)	Nke oge
1	2	64	1..63 (Enwere ike ime mmemme)	Ogologo oge
1	2	64	32 (Edoziri)	Nke oge
1	16	512	1..511 (Enwere ike ime mmemme)	Ogologo oge
1	16	512	256 (Edoziri)	Nke oge
2	3	19	1..191 (Enwere ike ime mmemme)	Ogologo oge
2	3	192	96 (Edoziri)	Nke oge
2	8	512	1..511 (Enwere ike ime mmemme)	Ogologo oge
2	8	512	256 (Edoziri)	Nke oge
2	9 (iwu na-akwadoghị)	64	32 (Edoziri)	Ogologo oge
2	9 (iwu na-akwadoghị)	64	32 (Edoziri)	Nke oge

 

Tebụl 10. Ndị na-edebanye aha njikwa SYSREF
Ị nwere ike ịhazigharị ndekọ njikwa SYSREF ma ọ bụrụ na ntọala ndekọ aha dị iche na ntọala nke akọwapụtara mgbe ị mepụtara ex.ample. Hazie ndekọ SYSREF tupu F-Tile JESD204C Intel FPGA IP adịkwaghị. Ọ bụrụ na ị họrọ mpụta SYSREF generator site na
sysref_ctrl[7] debanye aha bit, ị nwere ike ileghara ntọala maka ụdị SYSREF, multiplier, ọrụ okirikiri na-adọ.

Iberibe	Uru ndabara	Nkọwa
sysref_ctrl [1:0]	2'b00: Otu ogbugba 2'b01: oge 2'b10: Ogologo oge	Ụdị SYSREF. Uru ndabara dabere na ntọala ọnọdụ SYSREF na Example Design taabụ na F-Tile JESD204C Intel FPGA IP nchịkọta akụkọ paramita.
sysref_ctrl [6:2]	5 b00001	ọtụtụ SYSREF. Oghere SYSREF_MULP a dabara na ụdị SYSREF nke oge na nke nwere oghere. Ị ga-ahazirịrị uru bara ụba iji hụ na uru E*SYSREF_MULP dị n'etiti 1 ruo 16 tupu F-Tile JESD204C IP ewepụla. Ọ bụrụ na uru E*SYSREF_MULP esighị na nke a, ọnụọgụ ọnụọgụ na-adaba na 5'b00001.
sysref_ctrl[7]	Ụzọ data Duplex: 1'b1 Simplex TX ma ọ bụ RX data ụzọ: 1'b0	SYSREF họrọ. Uru ndabara dabere na ntọala ụzọ data dị na Example Kere taabụ na F-Tile JESD204C Intel FPGA IP nchịkọta akụkọ paramita. 0: Simplex TX ma ọ bụ RX (SYSREF mpụga) 1: Duplex (SYSREF nke ime)
sysref_ctrl [16:8]	9'h0	SYSREF ọrụ okirikiri mgbe ụdị SYSREF bụ nke oge ma ọ bụ gapped oge. Ị ga-ahazi okirikiri ọrụ tupu F-Tile JESD204C IP anọghị ntọgharị. Ọnụ kacha elu = (E*SYSREF_MULP*32)-1 Maka exampLe: 50% okirikiri ọrụ = (E*SYSREF_MULP*32)/2 Usoro okirikiri ọrụ na-adaba na 50% ma ọ bụrụ na ịhazighị mpaghara ndekọ aha a, ma ọ bụ ọ bụrụ na ị hazie mpaghara ndekọ aha ka 0 ma ọ bụ karịa karịa uru kacha ekwe.
sysref_ctrl[17]	1 b0	Njikwa ntuziaka mgbe ụdị SYSREF bụ otu-ise. Dee 1 ka ịtọọ mgbama SYSREF n'elu. Dee 0 ka ịtọọ mgbama SYSREF ka ọ dị ala. Ịkwesịrị ide 1 wee dee 0 iji mepụta pulse SYSREF n'ụdị otu-shot.
sysref_ctrl [31:18]	22'h0	Echekwara.

Tọgharia usoro
Nke a imewe example mejupụtara abụọ nrụpụta usoro:

• Tọgharia Usoro 0-Jikwaa nrụpụta nrụpụta na ngalaba nkwanye TX/RX Avalon, ngalaba ebe nchekwa Avalon, isi PLL, TX PHY, TX core, na generator SYSREF.
• Tọgharia Usoro 1-Jikwaa nrụpụta ahụ na RX PHY na RX Core.

3- waya SPI
Modul a bụ nhọrọ iji tọghata SPI interface ka ọ bụrụ waya 3.

Sistemụ PLL
F-tile nwere usoro PLL atọ na bọọdụ. Sistemụ PLL ndị a bụ isi mmalite elekere maka IP siri ike (MAC, PCS na FEC) na ngafe EMIB. Nke a pụtara na, mgbe ị na-eji sistemu PLL clocking mode, anaghị ekpuchi ihe mgbochi site na elekere PMA ma adabereghị na elekere na-abịa site na isi FPGA. Sistemu ọ bụla PLL na-ewepụta naanị elekere jikọtara ya na otu ugboro ugboro. Maka exampYa mere, ịchọrọ PLLs sistemu abụọ iji mee otu interface na 1 GHz na otu interface na 500 MHz. Iji sistemụ PLL na-enye gị ohere iji ụzọ ọ bụla n'onwe ya na-enweghị mgbanwe elekere nke na-emetụta okporo ụzọ agbata obi.
Sistemu ọ bụla PLL nwere ike iji nke ọ bụla n'ime elekere asatọ FGT. Sistemu PLL nwere ike kesaa elekere ntụaka ma ọ bụ nwee elekere ntụaka dị iche iche. Onye ọ bụla interface nwere ike họrọ nke usoro PLL ọ na-eji, ma, ozugbo ahọpụtara, ọ na-edozi, ọ bụghị reconfigurable iji ike reconfiguration.

Ozi metụtara
F-tile Architecture na PMA na FEC Direct PHY IP ntuziaka onye ọrụ

Ozi ndị ọzọ gbasara usoro PLL clocking mode na Intel Agilex F-tile ngwaọrụ.

Ụdị Generator na Checker
Ihe na-emepụta ụkpụrụ na onye na-enyocha ihe bara uru maka ịmepụta data samples na nlekota maka ebumnuche ule.
Tebụl 11. Onye na-emepụta ụkpụrụ akwadoro

Ụdị Generator	Nkọwa
PRBS ụkpụrụ generator	F-Tile JESD204C imewe exampOnye na-emepụta ụkpụrụ PRBS na-akwado ogo nke polynomials ndị a: PRBS23: X23+X18+1 PRBS15: X15+X14+1 PRBS9: X9+X5+1 PRBS7: X7+X6+1
Ramp ụkpụrụ generator	Ihe ramp ụkpụrụ ụkpụrụ na-abawanye site na 1 maka s ọ bụla na-esoteample na obosara generator nke N, wee tụgharịa gaa na 0 mgbe ihe niile dị na sample bu 1. Kwado ramp ụkpụrụ generator site na ide 1 ka bit 2 nke tst_ctl ndekọ nke ED akara ngọngọ.
Ọwa iwu ramp ụkpụrụ generator	F-Tile JESD204C imewe example na-akwado ọwa iwu ramp ụkpụrụ generator kwa uzo. Ihe ramp ụkpụrụ ụkpụrụ na-abawanye site na 1 kwa ibe 6 nke okwu iwu. Mkpụrụ mmalite bụ ụkpụrụ mmụba n'akụkụ ụzọ niile.

Tebụl 12. Onye na-enyocha ụkpụrụ na-akwado

Onye na-enyocha ụkpụrụ	Nkọwa
Ihe nlele ụkpụrụ PRBS	A na-emekọrịta mkpụrụ osisi na-akpagharị n'ụdị ihe nleba anya mgbe F-Tile JESD204C IP nwetara nhazi deskew. Onye na-enyocha ụkpụrụ chọrọ octets 8 maka mkpụrụ na-akpagharị ahụ iji mekọrịta onwe ya.
Ramp ihe nlele ụkpụrụ	Data izizi sampA na-eburu le maka onye ntụgharị ọ bụla (M) dị ka uru mbụ nke ramp ụkpụrụ. Na-esote data samples ụkpụrụ ga-abawanye site na 1 n'ime elekere ọ bụla ruo nke kachasị wee tụgharịa gaa na 0.

Onye na-enyocha ụkpụrụ	Nkọwa
	Maka example, mgbe S = 1, N = 16 na WIDTH_MULP = 2, data obosara kwa onye ntụgharị bụ S * WIDTH_MULP * N = 32. Oke data sample uru bụ 0xFFFF. Ihe ramp onye na-enyocha ụkpụrụ na-achọpụta na a na-anata ụkpụrụ ahụ n'ofe ndị ntụgharị niile.
Ọwa iwu ramp ihe nlele ụkpụrụ	F-Tile JESD204C imewe example na-akwado ọwa iwu ramp ihe nlele ụkpụrụ. A na-eburu okwu iwu mbụ (bit 6) enwetara dị ka uru mbụ. Okwu iwu na-esote n'otu ụzọ ahụ ga-abawanye ruo 0x3F wee tụgharịa gaa na 0x00. Ọwa iwu ramp ihe nlele ụkpụrụ maka ramp ụkpụrụ n'ofe ụzọ niile.

F-Tile JESD204C TX na RX IP
Nke a imewe example na-enye gị ohere ịhazi TX/RX ọ bụla na simplex mode ma ọ bụ duplex mode.
Nhazi duplex na-enye ohere ngosi arụmọrụ IP site na iji loopback nke ime ma ọ bụ mpụga. Ndị CSR dị n'ime IP emebeghị ka ha nwee ohere maka njikwa IP na nlele ọkwa.

F-Tile JESD204C imewe Example Elekere na Tọgharia

F-Tile JESD204C imewe example nwere setịpụ elekere na nrụgharị mgbama.

Tebụl 13.Imepụta Exampna Elekere

Mgbama elekere	Ntuziaka	Nkọwa
mgmt_clk	Ntinye	Elekere dị iche nke LVDS nwere ugboro 100 MHz.
refclk_xcvr	Ntinye	Elekere ntụgharị ntụgharị nwere ọnụọgụ data/ihe kpatara 33.
refclk_core	Ntinye	Igwe ntụaka isi nwere otu ugboro dị ka refclk_xcvr.
na sysref	Ntinye	Mgbama SYSREF. Ugboro SYSREF kachasị bụ ọnụọgụ data/(66x32xE).
sysref_out	Mpụta
txlink_clk rxlink_clk	Ime	TX na RX njikọ elekere na ugboro nke data ọnụego/66.
txframe_clk rxframe_clk	Ime	TX na RX etiti elekere nwere ọnụọgụ data/33 (FCLK_MULP=2) TX na RX etiti elekere nwere ọnụọgụ data/66 (FCLK_MULP=1)
tx_fclk rx_fclk	Ime	Oge elekere TX na RX nwere ọnụọgụ data/66 (FCLK_MULP=2) Oge elekere TX na RX na-adị elu mgbe niile (1'b1) mgbe FCLK_MULP=1
spi_SCLK	Mpụta	SPI baud elekere nwere ugboro 20 MHz.

Mgbe ị na-ebu ihe nhazi exampbanye na ngwaọrụ FPGA, ihe omume ime ninit_done na-eme ka o doo anya na JTAG na akwa akwa Avalon Master dị na nrụpụta yana ihe mgbochi ndị ọzọ niile.

Onye nrụpụta SYSREF nwere nrụpụta onwe ya ka ọ banye mmekọrịta asynchronous kpara akpa maka txlink_clk na rxlink_clk clocks. Usoro a zuru oke n'iṅomi akara SYSREF site na mgbawa elekere mpụga.

Tebụl 14. Imepụta Exampna Tọgharia

Tọgharia nrịbama	Ntuziaka	Nkọwa
zuru ụwa ọnụ_rst_n	Ntinye	Ntugharị bọtịnụ zuru ụwa ọnụ maka ngọngọ niile, ewezuga JTAG na Avalon Master Bridge.
emela ya	Ime	Nsonaazụ sitere na Tọgharia Mwepụta IP maka JTAG na Avalon Master Bridge.
edctl_rst_n	Ime	Tọgharịrị ngọngọ Control ED site na JTAG na Avalon Master Bridge. Ọdụ ụgbọ mmiri hw_rst na global_rst_n anaghị ewepụta ngọngọ njikwa ED.
hw_mkpa	Ime	Deassert na deassert hw_rst site na ịdegara aha rst_ctl nke ngọngọ ED Control. mgmt_rst_in_n kwuputara mgbe hw_rst kwadoro.
mgmt_rst_in_n	Ime	Tọgharịa maka oghere ebe nchekwa Avalon nke IP dị iche iche na ntinye nke ndị nrụpụta nrụpụta:  j20c_reconfig_reset maka F-Tile JESD204C IP duplex Native PHY spi_rst_n maka SPI master pio_rst_n maka ọkwa na njikwa PIO reset_in0 ọdụ ụgbọ mmiri nke usoro nrụpụta 0 na 1 nkwuputa nrụpụta ọdụ ụgbọ mmiri global_rst_n, hw_rst ma ọ bụ edctl_rst_n na mgmt_rst_in_n.
sysref_rst_n	Ime	Tọgharịa maka ngọngọ generator SYSREF n'ime ngọngọ njikwa ED site na iji usoro nrụpụta 0 reset_out2. Ihe nrụpụta nrụpụta 0 reset_out2 ọdụ ụgbọ mmiri na-ewepụta nrụpụta nrụpụta ma ọ bụrụ na akpọchiri isi PLL.
isi_pll_rst	Ime	Na-atọgharị isi PLL site na ọdụ nrụpụta nrụpụta 0 reset_out0. Isi PLL na-atọgharị mgbe etinyere nrụpụta mgmt_rst_in_n.
j204c_tx_avs_rst_n	Ime	Na-atọgharịa F-Tile JESD204C TX Avalon ebe nchekwa- mapped interface site nrụpụta usoro 0. TX Avalon ebe nchekwa-mapped interface na-ekwupụta mgbe mgmt_rst_in_n na-kwuputa.
j204c_rx_avs_rst_n	Ime	Na-atọgharịa F-Tile JESD204C TX Avalon ebe nchekwa- mapped interface site nrụpụta usoro 1. The RX Avalon ebe nchekwa-mapped interface na-ekwupụta mgbe mgmt_rst_in_n na-kwuputa.
j204c_tx_rst_n	Ime	Na-atọgharịa njikọ F-Tile JESD204C TX yana ọkwa mbufe na txlink_clk, yana txframe_clk, ngalaba. Ihe nrụpụta nrụpụta 0 reset_out5 ọdụ ụgbọ mmiri na-emegharị j204c_tx_rst_n. Tọgharia deassert a ma ọ bụrụ na akpọchiri isi PLL, yana akara tx_pma_ready na tx_ready na-ekwupụta.
j204c_rx_rst_n	Ime	Na-atọgharịa njikọ F-Tile JESD204C RX yana ọkwa mbufe na ngalaba rxlink_clk na rxframe_clk.

Tọgharia nrịbama	Ntuziaka	Nkọwa
		Ihe nrụpụta nrụpụta 1 reset_out4 ọdụ ụgbọ mmiri na-emegharị j204c_rx_rst_n. Tọgharia deassert a ma ọ bụrụ na akpọchiri isi PLL, yana akara ngosi rx_pma_ready na rx_ready.
j204c_tx_rst_ack_n	Ime	Tọgharia mgbaama aka mmanye na j204c_tx_rst_n.
j204c_rx_rst_ack_n	Ime	Tọgharia mgbaama mmanye aka na j204c_rx_rst_n.

Onyonyo 8. Eserese oge maka imewe Exampna Tọgharia

F-Tile JESD204C imewe Example Signals

Tebụl 15. Sistemu Interface Signals

Signal	Ntuziaka	Nkọwa
Elekere na nrụpụta
mgmt_clk	Ntinye	Elekere 100 MHz maka njikwa sistemụ.
refclk_xcvr	Ntinye	Elekere ntụaka maka F-tile UX QUAD na Sistemụ PLL. Dakọtara na ọnụego data/ihe kpatara nke 33.
refclk_core	Ntinye	Oge ntụaka isi PLL. Na-etinye otu ugboro elekere dịka refclk_xcvr.
na sysref	Ntinye	Mgbama SYSREF sitere na generator SYSREF mpụga maka mmejuputa Subclass 204 JESD1C.
sysref_out	Mpụta	Mgbama SYSREF maka mmejuputa JESD204C Subclass 1 nke ngwaọrụ FPGA mepụtara maka imewe exampnaanị ebumnuche mmalite njikọ.

 

Signal	Ntuziaka	Nkọwa
SPI
spi_SS_n [2:0]	Mpụta	Mgbama na-arụ ọrụ dị ala, ohu SPI họrọ akara.
spi_SCLK	Mpụta	Usoro elekere SPI.
spi_sdio	Ntinye/mmepụta	Mpụta data sitere na nna ukwu gaa na ohu mpụga. Tinye data sitere na ohu mpụga gaa na nna ukwu.

Signal	Ntuziaka	Nkọwa
Mara:Mgbe akwadoro nhọrọ Module 3-Wire SPI.
spi_MISO Rịba ama: Mgbe Mepụta 3-Wire SPI nhọrọ Module adịghị enyere.	Ntinye	Tinye data sitere na ohu mpụga nye onye nwe SPI.
spi_MOSI Mara: Mgbe Mepụta 3-Wire SPI nhọrọ Module adịghị enyere.	Mpụta	Ntinye data sitere na nna ukwu SPI gaa na ohu mpụga.

 

Signal	Ntuziaka	Nkọwa
ADC/DAC
tx_serial_data[LINK*L-1:0]	Mpụta	Ọdịiche dị elu dị elu data mmepụta data na DAC. Agbanyere elekere na iyi data serial.
tx_serial_data_n[LINK*L-1:0]
rx_serial_data[LINK*L-1:0]	Ntinye	Ihe ntinye ọsọ ọsọ dị elu dị iche iche sitere na ADC. A na-enwetaghachi elekere site na iyi data serial.
rx_serial_data_n[LINK*L-1:0]

 

Signal	Ntuziaka	Nkọwa
Ebumnuche I/O zuru oke
onye ọrụ_led[3:0]	Mpụta	Na-egosi ọkwa maka ọnọdụ ndị a: [0]: Emebere mmemme SPI [1]: Njehie njikọ TX [2]: Njehie njikọ RX [3]: Njehie nyocha ụkpụrụ maka data nkwanye Avalon
onye ọrụ[3:0]	Ntinye	Ntinye mgbanwe DIP mode onye ọrụ: [0]: Internal serial loopback na-enyere aka [1]: SYSREF emepụtara FPGA [3:2]: Echekwara

 

Signal	Ntuziaka	Nkọwa
Ọpụpụ (OOB) na Ọnọdụ
rx_patchk_data_error[LINK-1:0]	Mpụta	Mgbe egosipụtara mgbaama a, ọ na-egosi na onye na-enyocha ụkpụrụ achọpụtala mperi.
rx_link_error[LINK-1:0]	Mpụta	Mgbe ekwuputara mgbama a, ọ na-egosi JESD204C RX IP ekwuputala nkwụsị.
tx_link_error[LINK-1:0]	Mpụta	Mgbe ekwuputara mgbama a, ọ na-egosi JESD204C TX IP ekwuputala nkwụsị.
emb_lock_out	Mpụta	Mgbe ekwuputara mgbama a, ọ na-egosi JESD204C RX IP enwetala mkpọchi EMB.
sh_lock_out	Mpụta	Mgbe ekwuputara mgbama a, ọ na-egosi akpọchiri nkụnye eji isi mee mmekọrịta JESD204C RX IP.

 

Signal	Ntuziaka	Nkọwa
Avalon gụgharia
rx_avst_valid[LINK-1:0]	Ntinye	Na-egosi ma onye ntụgharị sample data na oyi akwa ngwa dị irè ma ọ bụ na-ezighi ezi. 0: Data ezighi ezi 1: Data dị irè
rx_avst_data[(TOTAL_SAMPLE*N)-1:0 ]	Ntinye	Ntụgharị sample data na ngwa oyi akwa.

F-Tile JESD204C imewe Exampna Control Registers

F-Tile JESD204C imewe example debanye aha na ED Control ngọngọ were byte-addressing (bits 32).

Tebụl 16. Imepụta ExampMap adreesị
Ihe ndekọ ngọngọ ED Control 32-bit dị na ngalaba mgmt_clk.

Akụkụ	Adreesị
F-Tile JESD204C TX IP	0x000C_0000 – 0x000C_03FF
F-Tile JESD204C RX IP	0x000D_0000 – 0x000D_03FF
Njikwa SPI	0x0102_0000 – 0x0102_001F
Njikwa PIO	0x0102_0020 – 0x0102_002F
Ọnọdụ PIO	0x0102_0040 – 0x0102_004F
Tọgharia usoro 0	0x0102_0100 – 0x0102_01FF
Tọgharia usoro 1	0x0102_0200 – 0x0102_02FF
Njikwa ED	0x0102_0400 – 0x0102_04FF
F-Tile JESD204C IP transceiver PHY Reconfig	0x0200_0000 – 0x023F_FFFF

Tebụl 17. Debanye aha ụdị nnweta na nkọwapụta
Tebụl a na-akọwa ụdị ịnweta aha maka Intel FPGA IP.

Ụdị nnweta	Nkọwa
RO/V	Naanị ịgụ ngwa ngwa (enweghị mmetụta na ide). Uru nwere ike ịdị iche.
RW	Ngwanrọ na-agụ wee weghachi uru ntakịrị dị ugbu a. Ngwanrọ na-ede ma debe ntakịrị ka ọ bụrụ uru achọrọ.
RW1C	Ngwanrọ na-agụ wee weghachi uru ntakịrị dị ugbu a. Ngwanrọ na-ede 0 na enweghị mmetụta. Ngwanrọ na-ede 1 wee kpochapụ ntakịrị ka ọ bụrụ 0 ma ọ bụrụ na ejiri ngwaike edobere bit ahụ ka ọ bụrụ 1. Akụrụngwa na-edobe ntakịrị ka ọ bụrụ 1. Software doro anya nwere mkpa dị elu karịa ntọala ngwaike.

Isiokwu 18. ED Control Adreesị Map

Akwụsịghị	Aha aha
0x00	rst_ctl
0x04	mbụ_st0
gara n'ihu…

Akwụsịghị	Aha aha
0x10	rst_sts_chọpụtara0
0x40	sysref_ctl
0x44	sysref_sts
0x80	tst_ctl
0x8m	tst_err0

Tebụl 19. ED Control Block Control na Ọnọdụ ndekọ

Byte Akwụsịghị	Debanye aha	Aha	Nweta	Tọgharia	Nkọwa
0x00	rst_ctl	mbụ_nkwuputa	RW	0x0	Tọgharịa njikwa. [0]: Dee 1 iji kwupụta nrụpụta. (hw_rst) Dee 0 ọzọ ka ịtọgharịa megharịa. [31:1]: Echekwara.
0x04	mbụ_st0	mbụ_ọnọdụ	RO/V	0x0	Tọgharịa ọkwa. [0]: Isi PLL kpọchiri ọkwa. [31:1]: Echekwara.
0x10	rst_sts_dete cted0	mbụ_sts_set	RW1C	0x0	Ọkwa nchọpụta ihu SYSREF maka n'ime ma ọ bụ mpụga SYSREF generator. [0]: Uru nke 1 na-egosi SYSREF ịrị elu achọpụtara maka ọrụ subclass 1. Ngwanrọ nwere ike dee 1 iji kpochapụ ntakịrị ihe a iji mee ka nchọpụta ihu SYSREF ọhụrụ. [31:1]: Echekwara.
0x40	sysref_ctl	sysref_contr ol	RW	Duplex data ụzọ Otu agba: 0x00080	njikwa SYSREF. Tụtụ aka na Tebụl 10 na ibe 17 maka ozi ndị ọzọ gbasara ojiji nke ndekọ a.
				Nke oge:	Mara: Uru nrụpụta dabere na
				0x00081	ụdị SYSREF na F-Tile
				Ihe na-agbanwe agbanwe:	Ntọala oke data ụzọ JESD204C IP.
				0x00082
				TX ma ọ bụ RX data
				uzo
				Otu agba:
				0x00000
				Nke oge:
				0x00001
				Agbaghara -
				nke oge:
				0x00002
0x44	sysref_sts	sysref_statu s	RO/V	0x0	Ọkwa SYSREF. Ndebanye aha a nwere oge SYSREF kachasị ọhụrụ yana ntọala okirikiri ọrụ nke igwe nrụpụta SYSREF dị n'ime. Tụtụ aka na Tebụl 9 na ibe 16 maka uru iwu nke oge SYSREF na okirikiri ọrụ.
gara n'ihu…

Byte Akwụsịghị	Debanye aha	Aha	Nweta	Tọgharia	Nkọwa
					[8:0]: oge ​​SYSREF. Mgbe uru bụ 0xFF, na Oge SYSREF = 255 Mgbe uru ma ọ bụrụ 0x00, SYSREF oge = 256. [17:9]: SYSREF ọrụ okirikiri. [31:18]: Echekwara.
0x80	tst_ctl	tst_control	RW	0x0	Nyochaa njikwa. Jiri ndebanye aha a iji mee ka usoro nnwale dị iche iche maka onye na-emepụta ụkpụrụ na checker. [1:0] = Ogige echekwara [2] = ramp_nwale_ctl 1'b0 = Na-enyere onye nrụpụta ụkpụrụ PRBS na nlele anya 1'b1 = Na-enyere ramp ụkpụrụ generator na checker [31:3]: Echekwara.
0x8m	tst_err0	tst_error	RW1C	0x0	Ọkọlọtọ mperi maka Njikọ 0. Mgbe bit bụ 1'b1, ọ na-egosi na njehie emela. Ị ga-edozi njehie ahụ tupu ịde 1'b1 na nke ọ bụla iji kpochapụ ọkọlọtọ njehie. [0] = Njehie ihe nleba anya ụkpụrụ [1] = tx_link_error [2] = rx_link_error [3] = Njehie nyocha ụkpụrụ iwu [31:4]: Edobere.

Akụkọ ngbanwe akwụkwọ maka F-Tile JESD204C Intel FPGA IP Design Example ntuziaka onye ọrụ

Ụdị akwụkwọ	Intel Quartus Prime Version	Ụdị IP	Mgbanwe
2021.10.11	21.3	1.0.0	Ntọhapụ mbụ.

Akwụkwọ / akụrụngwa

intel F-Tile JESD204C Intel FPGA IP Design Example [pdf] Ntuziaka onye ọrụ F-Tile JESD204C Intel FPGA IP Design Example, F-Tile JESD204C, Intel FPGA IP Design Example, IP Design Example, Imepụta Example

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